2015-08-21 17:55:36 -06:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/**
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* \file amdgpu_device.c
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*
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* Implementation of functions for AMD GPU device
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*
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*/
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#include <sys/stat.h>
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#include <errno.h>
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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2018-09-13 05:55:15 -06:00
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#include <fcntl.h>
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2015-08-21 17:55:36 -06:00
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#include "xf86drm.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#include "util_math.h"
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#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
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2019-11-26 19:09:48 -07:00
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static pthread_mutex_t dev_mutex = PTHREAD_MUTEX_INITIALIZER;
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static amdgpu_device_handle dev_list;
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2015-08-21 17:55:36 -06:00
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2018-09-13 05:55:15 -06:00
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static int fd_compare(int fd1, int fd2)
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2015-08-21 17:55:36 -06:00
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{
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char *name1 = drmGetPrimaryDeviceNameFromFd(fd1);
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char *name2 = drmGetPrimaryDeviceNameFromFd(fd2);
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int result;
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if (name1 == NULL || name2 == NULL) {
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free(name1);
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free(name2);
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return 0;
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}
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result = strcmp(name1, name2);
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free(name1);
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free(name2);
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return result;
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}
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/**
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* Get the authenticated form fd,
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*
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* \param fd - \c [in] File descriptor for AMD GPU device
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* \param auth - \c [out] Pointer to output the fd is authenticated or not
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* A render node fd, output auth = 0
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* A legacy fd, get the authenticated for compatibility root
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*
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* \return 0 on success\n
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* >0 - AMD specific error code\n
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* <0 - Negative POSIX Error code
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*/
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static int amdgpu_get_auth(int fd, int *auth)
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{
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int r = 0;
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drm_client_t client = {};
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if (drmGetNodeTypeFromFd(fd) == DRM_NODE_RENDER)
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*auth = 0;
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else {
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client.idx = 0;
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r = drmIoctl(fd, DRM_IOCTL_GET_CLIENT, &client);
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if (!r)
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*auth = client.auth;
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}
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return r;
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}
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static void amdgpu_device_free_internal(amdgpu_device_handle dev)
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{
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2019-11-26 19:09:48 -07:00
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amdgpu_device_handle *node = &dev_list;
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2018-09-13 05:55:15 -06:00
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2019-11-26 19:09:48 -07:00
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pthread_mutex_lock(&dev_mutex);
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2018-09-13 05:55:15 -06:00
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while (*node != dev && (*node)->next)
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node = &(*node)->next;
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*node = (*node)->next;
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2018-09-13 05:55:15 -06:00
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2015-08-21 17:55:36 -06:00
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close(dev->fd);
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if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
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close(dev->flink_fd);
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2018-09-13 05:55:15 -06:00
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amdgpu_vamgr_deinit(&dev->vamgr_32);
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amdgpu_vamgr_deinit(&dev->vamgr);
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amdgpu_vamgr_deinit(&dev->vamgr_high_32);
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amdgpu_vamgr_deinit(&dev->vamgr_high);
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handle_table_fini(&dev->bo_handles);
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handle_table_fini(&dev->bo_flink_names);
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pthread_mutex_destroy(&dev->bo_table_mutex);
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2018-02-16 19:24:37 -07:00
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free(dev->marketing_name);
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2015-08-21 17:55:36 -06:00
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free(dev);
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}
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/**
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* Assignment between two amdgpu_device pointers with reference counting.
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*
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* Usage:
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* struct amdgpu_device *dst = ... , *src = ...;
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*
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* dst = src;
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* // No reference counting. Only use this when you need to move
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* // a reference from one pointer to another.
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*
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* amdgpu_device_reference(&dst, src);
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* // Reference counters are updated. dst is decremented and src is
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* // incremented. dst is freed if its reference counter is 0.
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*/
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static void amdgpu_device_reference(struct amdgpu_device **dst,
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2018-11-01 02:22:36 -06:00
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struct amdgpu_device *src)
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2015-08-21 17:55:36 -06:00
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{
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if (update_references(&(*dst)->refcount, &src->refcount))
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amdgpu_device_free_internal(*dst);
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*dst = src;
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}
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2018-11-01 02:22:36 -06:00
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drm_public int amdgpu_device_initialize(int fd,
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uint32_t *major_version,
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uint32_t *minor_version,
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amdgpu_device_handle *device_handle)
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2015-08-21 17:55:36 -06:00
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{
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struct amdgpu_device *dev;
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drmVersionPtr version;
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int r;
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int flag_auth = 0;
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int flag_authexist=0;
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uint32_t accel_working = 0;
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uint64_t start, max;
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*device_handle = NULL;
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2019-11-26 19:09:48 -07:00
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pthread_mutex_lock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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r = amdgpu_get_auth(fd, &flag_auth);
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if (r) {
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2018-02-16 19:24:37 -07:00
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fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
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__func__, r);
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return r;
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}
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2018-09-13 05:55:15 -06:00
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2019-11-26 19:09:48 -07:00
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for (dev = dev_list; dev; dev = dev->next)
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2018-09-13 05:55:15 -06:00
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if (fd_compare(dev->fd, fd) == 0)
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break;
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2015-08-21 17:55:36 -06:00
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if (dev) {
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r = amdgpu_get_auth(dev->fd, &flag_authexist);
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if (r) {
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2018-02-16 19:24:37 -07:00
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fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n",
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__func__, r);
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return r;
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}
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if ((flag_auth) && (!flag_authexist)) {
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2018-09-13 05:55:15 -06:00
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dev->flink_fd = fcntl(fd, F_DUPFD_CLOEXEC, 0);
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2015-08-21 17:55:36 -06:00
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}
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*major_version = dev->major_version;
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*minor_version = dev->minor_version;
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amdgpu_device_reference(device_handle, dev);
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return 0;
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}
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dev = calloc(1, sizeof(struct amdgpu_device));
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if (!dev) {
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2018-02-16 19:24:37 -07:00
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fprintf(stderr, "%s: calloc failed\n", __func__);
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return -ENOMEM;
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}
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dev->fd = -1;
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dev->flink_fd = -1;
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atomic_set(&dev->refcount, 1);
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version = drmGetVersion(fd);
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if (version->version_major != 3) {
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fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
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"only compatible with 3.x.x.\n",
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__func__,
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version->version_major,
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version->version_minor,
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version->version_patchlevel);
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drmFreeVersion(version);
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r = -EBADF;
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goto cleanup;
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}
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2018-09-13 05:55:15 -06:00
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dev->fd = fcntl(fd, F_DUPFD_CLOEXEC, 0);
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2015-08-21 17:55:36 -06:00
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dev->flink_fd = dev->fd;
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dev->major_version = version->version_major;
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dev->minor_version = version->version_minor;
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drmFreeVersion(version);
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pthread_mutex_init(&dev->bo_table_mutex, NULL);
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/* Check if acceleration is working. */
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r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4, &accel_working);
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2018-02-16 19:24:37 -07:00
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if (r) {
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fprintf(stderr, "%s: amdgpu_query_info(ACCEL_WORKING) failed (%i)\n",
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__func__, r);
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2015-08-21 17:55:36 -06:00
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goto cleanup;
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2018-02-16 19:24:37 -07:00
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}
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2015-08-21 17:55:36 -06:00
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if (!accel_working) {
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2018-02-16 19:24:37 -07:00
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fprintf(stderr, "%s: AMDGPU_INFO_ACCEL_WORKING = 0\n", __func__);
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2015-08-21 17:55:36 -06:00
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r = -EBADF;
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goto cleanup;
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}
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r = amdgpu_query_gpu_info_init(dev);
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2018-02-16 19:24:37 -07:00
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if (r) {
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fprintf(stderr, "%s: amdgpu_query_gpu_info_init failed\n", __func__);
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2015-08-21 17:55:36 -06:00
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goto cleanup;
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2018-02-16 19:24:37 -07:00
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}
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2015-08-21 17:55:36 -06:00
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2018-02-16 19:24:37 -07:00
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start = dev->dev_info.virtual_address_offset;
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2018-09-13 05:55:15 -06:00
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max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL);
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2017-04-14 01:45:34 -06:00
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amdgpu_vamgr_init(&dev->vamgr_32, start, max,
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2015-08-21 17:55:36 -06:00
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dev->dev_info.virtual_address_alignment);
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2018-09-13 05:55:15 -06:00
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start = max;
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2018-02-16 19:24:37 -07:00
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max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
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amdgpu_vamgr_init(&dev->vamgr, start, max,
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dev->dev_info.virtual_address_alignment);
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2018-09-13 05:55:15 -06:00
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start = dev->dev_info.high_va_offset;
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max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
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0x100000000ULL);
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amdgpu_vamgr_init(&dev->vamgr_high_32, start, max,
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dev->dev_info.virtual_address_alignment);
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start = max;
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max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
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0x100000000ULL);
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amdgpu_vamgr_init(&dev->vamgr_high, start, max,
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dev->dev_info.virtual_address_alignment);
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2018-02-16 19:24:37 -07:00
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amdgpu_parse_asic_ids(dev);
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2017-08-05 08:15:15 -06:00
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2015-08-21 17:55:36 -06:00
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*major_version = dev->major_version;
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*minor_version = dev->minor_version;
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*device_handle = dev;
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2019-11-26 19:09:48 -07:00
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dev->next = dev_list;
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dev_list = dev;
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return 0;
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cleanup:
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if (dev->fd >= 0)
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close(dev->fd);
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free(dev);
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2019-11-26 19:09:48 -07:00
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pthread_mutex_unlock(&dev_mutex);
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2015-08-21 17:55:36 -06:00
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return r;
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}
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2018-11-01 02:22:36 -06:00
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drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev)
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2015-08-21 17:55:36 -06:00
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{
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amdgpu_device_reference(&dev, NULL);
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return 0;
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}
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2016-11-18 22:36:14 -07:00
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2018-11-01 02:22:36 -06:00
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drm_public const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
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2016-11-18 22:36:14 -07:00
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{
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2018-02-16 19:24:37 -07:00
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return dev->marketing_name;
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2016-11-18 22:36:14 -07:00
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}
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2018-09-13 05:55:15 -06:00
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2018-11-01 02:22:36 -06:00
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drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
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enum amdgpu_sw_info info,
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void *value)
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2018-09-13 05:55:15 -06:00
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{
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uint32_t *val32 = (uint32_t*)value;
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switch (info) {
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case amdgpu_sw_info_address32_hi:
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if (dev->vamgr_high_32.va_max)
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*val32 = (dev->vamgr_high_32.va_max - 1) >> 32;
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else
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*val32 = (dev->vamgr_32.va_max - 1) >> 32;
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return 0;
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}
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return -EINVAL;
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}
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