Import libdrm 2.4.82
This commit is contained in:
jsg
parent
06a1409c9f
commit
fb01c3ceed
@ -30,12 +30,19 @@ AM_CFLAGS = \
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$(PTHREADSTUBS_CFLAGS) \
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-I$(top_srcdir)/include/drm
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libdrmdatadir = @libdrmdatadir@
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ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \
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$(top_srcdir)/data/amdgpu.ids)
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AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \
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-DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES)
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libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
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libdrm_amdgpu_ladir = $(libdir)
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libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
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libdrm_amdgpu_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
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libdrm_amdgpu_la_SOURCES = $(LIBDRM_AMDGPU_FILES)
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amdgpu_asic_id.lo: $(top_srcdir)/data/amdgpu.ids
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libdrm_amdgpuincludedir = ${includedir}/libdrm
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libdrm_amdgpuinclude_HEADERS = $(LIBDRM_AMDGPU_H_FILES)
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@ -1,5 +1,5 @@
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LIBDRM_AMDGPU_FILES := \
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amdgpu_asic_id.h \
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amdgpu_asic_id.c \
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amdgpu_bo.c \
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amdgpu_cs.c \
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amdgpu_device.c \
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@ -25,14 +25,22 @@ amdgpu_bo_va_op
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amdgpu_bo_va_op_raw
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amdgpu_bo_wait_for_idle
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amdgpu_create_bo_from_user_mem
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amdgpu_cs_chunk_fence_info_to_data
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amdgpu_cs_chunk_fence_to_dep
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amdgpu_cs_create_semaphore
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amdgpu_cs_create_syncobj
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amdgpu_cs_ctx_create
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amdgpu_cs_ctx_free
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amdgpu_cs_destroy_semaphore
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amdgpu_cs_destroy_syncobj
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amdgpu_cs_export_syncobj
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amdgpu_cs_import_syncobj
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amdgpu_cs_query_fence_status
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amdgpu_cs_query_reset_state
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amdgpu_cs_signal_semaphore
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amdgpu_cs_submit
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amdgpu_cs_submit_raw
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amdgpu_cs_wait_fences
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amdgpu_cs_wait_semaphore
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amdgpu_device_deinitialize
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amdgpu_device_initialize
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@ -37,6 +37,10 @@
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct drm_amdgpu_info_hw_ip;
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/*--------------------------------------------------------------------------*/
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@ -907,6 +911,29 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
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uint64_t flags,
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uint32_t *expired);
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/**
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* Wait for multiple fences
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*
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* \param fences - \c [in] The fence array to wait
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* \param fence_count - \c [in] The fence count
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* \param wait_all - \c [in] If true, wait all fences to be signaled,
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* otherwise, wait at least one fence
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* \param timeout_ns - \c [in] The timeout to wait, in nanoseconds
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* \param status - \c [out] '1' for signaled, '0' for timeout
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* \param first - \c [out] the index of the first signaled fence from @fences
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*
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* \return 0 on success
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* <0 - Negative POSIX Error code
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*
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* \note Currently it supports only one amdgpu_device. All fences come from
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* the same amdgpu_device with the same fd.
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*/
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int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
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uint32_t fence_count,
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bool wait_all,
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uint64_t timeout_ns,
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uint32_t *status, uint32_t *first);
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/*
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* Query / Info API
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*
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@ -1301,4 +1328,91 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
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*/
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const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
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/**
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* Create kernel sync object
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*
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* \param dev - \c [in] device handle
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* \param syncobj - \c [out] sync object handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
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uint32_t *syncobj);
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/**
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* Destroy kernel sync object
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*
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* \param dev - \c [in] device handle
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* \param syncobj - \c [in] sync object handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
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uint32_t syncobj);
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/**
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* Export kernel sync object to shareable fd.
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*
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* \param dev - \c [in] device handle
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* \param syncobj - \c [in] sync object handle
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* \param shared_fd - \c [out] shared file descriptor.
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
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uint32_t syncobj,
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int *shared_fd);
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/**
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* Import kernel sync object from shareable fd.
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*
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* \param dev - \c [in] device handle
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* \param shared_fd - \c [in] shared file descriptor.
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* \param syncobj - \c [out] sync object handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
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int shared_fd,
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uint32_t *syncobj);
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/**
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* Submit raw command submission to kernel
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*
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* \param dev - \c [in] device handle
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* \param context - \c [in] context handle for context id
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* \param bo_list_handle - \c [in] request bo list handle (0 for none)
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* \param num_chunks - \c [in] number of CS chunks to submit
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* \param chunks - \c [in] array of CS chunks
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* \param seq_no - \c [out] output sequence number for submission.
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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*/
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struct drm_amdgpu_cs_chunk;
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struct drm_amdgpu_cs_chunk_dep;
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struct drm_amdgpu_cs_chunk_data;
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int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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amdgpu_bo_list_handle bo_list_handle,
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int num_chunks,
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struct drm_amdgpu_cs_chunk *chunks,
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uint64_t *seq_no);
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void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
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struct drm_amdgpu_cs_chunk_dep *dep);
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void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
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struct drm_amdgpu_cs_chunk_data *data);
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#ifdef __cplusplus
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}
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#endif
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#endif /* #ifdef _AMDGPU_H_ */
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219
lib/libdrm/amdgpu/amdgpu_asic_id.c
Normal file
219
lib/libdrm/amdgpu/amdgpu_asic_id.c
Normal file
@ -0,0 +1,219 @@
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/*
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* Copyright © 2017 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <ctype.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include "xf86drm.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
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{
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char *buf, *saveptr;
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char *s_did;
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char *s_rid;
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char *s_name;
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char *endptr;
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int r = 0;
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buf = strdup(line);
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if (!buf)
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return -ENOMEM;
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/* ignore empty line and commented line */
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if (strlen(line) == 0 || line[0] == '#') {
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r = -EAGAIN;
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goto out;
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}
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/* device id */
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s_did = strtok_r(buf, ",", &saveptr);
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if (!s_did) {
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r = -EINVAL;
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goto out;
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}
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id->did = strtol(s_did, &endptr, 16);
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if (*endptr) {
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r = -EINVAL;
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goto out;
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}
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/* revision id */
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s_rid = strtok_r(NULL, ",", &saveptr);
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if (!s_rid) {
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r = -EINVAL;
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goto out;
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}
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id->rid = strtol(s_rid, &endptr, 16);
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if (*endptr) {
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r = -EINVAL;
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goto out;
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}
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/* marketing name */
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s_name = strtok_r(NULL, ",", &saveptr);
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if (!s_name) {
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r = -EINVAL;
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goto out;
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}
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/* trim leading whitespaces or tabs */
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while (isblank(*s_name))
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s_name++;
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if (strlen(s_name) == 0) {
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r = -EINVAL;
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goto out;
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}
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id->marketing_name = strdup(s_name);
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if (id->marketing_name == NULL) {
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r = -EINVAL;
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goto out;
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}
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out:
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free(buf);
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return r;
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}
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int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
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{
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struct amdgpu_asic_id *asic_id_table;
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struct amdgpu_asic_id *id;
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FILE *fp;
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char *line = NULL;
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size_t len = 0;
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ssize_t n;
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int line_num = 1;
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size_t table_size = 0;
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size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
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int r = 0;
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fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
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if (!fp) {
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fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
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strerror(errno));
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return -EINVAL;
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}
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asic_id_table = calloc(table_max_size + 1,
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sizeof(struct amdgpu_asic_id));
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if (!asic_id_table) {
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r = -ENOMEM;
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goto close;
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}
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/* 1st valid line is file version */
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while ((n = getline(&line, &len, fp)) != -1) {
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/* trim trailing newline */
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if (line[n - 1] == '\n')
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line[n - 1] = '\0';
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/* ignore empty line and commented line */
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if (strlen(line) == 0 || line[0] == '#') {
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line_num++;
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continue;
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}
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drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
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break;
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}
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while ((n = getline(&line, &len, fp)) != -1) {
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if (table_size > table_max_size) {
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/* double table size */
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table_max_size *= 2;
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id = realloc(asic_id_table, (table_max_size + 1) *
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sizeof(struct amdgpu_asic_id));
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if (!id) {
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r = -ENOMEM;
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goto free;
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}
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asic_id_table = id;
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}
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id = asic_id_table + table_size;
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/* trim trailing newline */
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if (line[n - 1] == '\n')
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line[n - 1] = '\0';
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r = parse_one_line(line, id);
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if (r) {
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if (r == -EAGAIN) {
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line_num++;
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continue;
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}
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fprintf(stderr, "Invalid format: %s: line %d: %s\n",
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AMDGPU_ASIC_ID_TABLE, line_num, line);
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goto free;
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}
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line_num++;
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table_size++;
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}
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/* end of table */
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id = asic_id_table + table_size;
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memset(id, 0, sizeof(struct amdgpu_asic_id));
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if (table_size != table_max_size) {
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id = realloc(asic_id_table, (table_size + 1) *
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sizeof(struct amdgpu_asic_id));
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if (!id)
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r = -ENOMEM;
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else
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asic_id_table = id;
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}
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free:
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free(line);
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if (r && asic_id_table) {
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while (table_size--) {
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id = asic_id_table + table_size;
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free(id->marketing_name);
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}
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free(asic_id_table);
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asic_id_table = NULL;
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}
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close:
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fclose(fp);
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*p_asic_id_table = asic_id_table;
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return r;
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}
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@ -59,13 +59,11 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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int i, j, k;
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int r;
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if (NULL == dev)
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return -EINVAL;
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if (NULL == context)
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if (!dev || !context)
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return -EINVAL;
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gpu_context = calloc(1, sizeof(struct amdgpu_context));
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if (NULL == gpu_context)
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if (!gpu_context)
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return -ENOMEM;
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gpu_context->dev = dev;
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@ -110,7 +108,7 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
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int i, j, k;
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int r;
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if (NULL == context)
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if (!context)
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return -EINVAL;
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pthread_mutex_destroy(&context->sequence_mutex);
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@ -330,9 +328,7 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
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uint32_t i;
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int r;
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if (NULL == context)
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return -EINVAL;
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if (NULL == ibs_request)
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if (!context || !ibs_request)
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return -EINVAL;
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r = 0;
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@ -416,11 +412,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
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bool busy = true;
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int r;
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if (NULL == fence)
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return -EINVAL;
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if (NULL == expired)
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return -EINVAL;
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if (NULL == fence->context)
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if (!fence || !expired || !fence->context)
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return -EINVAL;
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if (fence->ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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@ -443,15 +435,83 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
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return r;
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}
|
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static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
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uint32_t fence_count,
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bool wait_all,
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uint64_t timeout_ns,
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uint32_t *status,
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uint32_t *first)
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{
|
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struct drm_amdgpu_fence *drm_fences;
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amdgpu_device_handle dev = fences[0].context->dev;
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union drm_amdgpu_wait_fences args;
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int r;
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uint32_t i;
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|
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drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count);
|
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for (i = 0; i < fence_count; i++) {
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drm_fences[i].ctx_id = fences[i].context->id;
|
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drm_fences[i].ip_type = fences[i].ip_type;
|
||||
drm_fences[i].ip_instance = fences[i].ip_instance;
|
||||
drm_fences[i].ring = fences[i].ring;
|
||||
drm_fences[i].seq_no = fences[i].fence;
|
||||
}
|
||||
|
||||
memset(&args, 0, sizeof(args));
|
||||
args.in.fences = (uint64_t)(uintptr_t)drm_fences;
|
||||
args.in.fence_count = fence_count;
|
||||
args.in.wait_all = wait_all;
|
||||
args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns);
|
||||
|
||||
r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args);
|
||||
if (r)
|
||||
return -errno;
|
||||
|
||||
*status = args.out.status;
|
||||
|
||||
if (first)
|
||||
*first = args.out.first_signaled;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
|
||||
uint32_t fence_count,
|
||||
bool wait_all,
|
||||
uint64_t timeout_ns,
|
||||
uint32_t *status,
|
||||
uint32_t *first)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
/* Sanity check */
|
||||
if (!fences || !status || !fence_count)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < fence_count; i++) {
|
||||
if (NULL == fences[i].context)
|
||||
return -EINVAL;
|
||||
if (fences[i].ip_type >= AMDGPU_HW_IP_NUM)
|
||||
return -EINVAL;
|
||||
if (fences[i].ring >= AMDGPU_CS_MAX_RINGS)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*status = 0;
|
||||
|
||||
return amdgpu_ioctl_wait_fences(fences, fence_count, wait_all,
|
||||
timeout_ns, status, first);
|
||||
}
|
||||
|
||||
int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
|
||||
{
|
||||
struct amdgpu_semaphore *gpu_semaphore;
|
||||
|
||||
if (NULL == sem)
|
||||
if (!sem)
|
||||
return -EINVAL;
|
||||
|
||||
gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
|
||||
if (NULL == gpu_semaphore)
|
||||
if (!gpu_semaphore)
|
||||
return -ENOMEM;
|
||||
|
||||
atomic_set(&gpu_semaphore->refcount, 1);
|
||||
@ -466,14 +526,12 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
|
||||
uint32_t ring,
|
||||
amdgpu_semaphore_handle sem)
|
||||
{
|
||||
if (NULL == ctx)
|
||||
if (!ctx || !sem)
|
||||
return -EINVAL;
|
||||
if (ip_type >= AMDGPU_HW_IP_NUM)
|
||||
return -EINVAL;
|
||||
if (ring >= AMDGPU_CS_MAX_RINGS)
|
||||
return -EINVAL;
|
||||
if (NULL == sem)
|
||||
return -EINVAL;
|
||||
/* sem has been signaled */
|
||||
if (sem->signal_fence.context)
|
||||
return -EINVAL;
|
||||
@ -494,16 +552,14 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
|
||||
uint32_t ring,
|
||||
amdgpu_semaphore_handle sem)
|
||||
{
|
||||
if (NULL == ctx)
|
||||
if (!ctx || !sem)
|
||||
return -EINVAL;
|
||||
if (ip_type >= AMDGPU_HW_IP_NUM)
|
||||
return -EINVAL;
|
||||
if (ring >= AMDGPU_CS_MAX_RINGS)
|
||||
return -EINVAL;
|
||||
if (NULL == sem)
|
||||
return -EINVAL;
|
||||
/* must signal first */
|
||||
if (NULL == sem->signal_fence.context)
|
||||
if (!sem->signal_fence.context)
|
||||
return -EINVAL;
|
||||
|
||||
pthread_mutex_lock(&ctx->sequence_mutex);
|
||||
@ -514,9 +570,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
|
||||
|
||||
static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
|
||||
{
|
||||
if (NULL == sem)
|
||||
return -EINVAL;
|
||||
if (NULL == sem->signal_fence.context)
|
||||
if (!sem || !sem->signal_fence.context)
|
||||
return -EINVAL;
|
||||
|
||||
sem->signal_fence.context = NULL;;
|
||||
@ -530,7 +584,7 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
|
||||
|
||||
static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
|
||||
{
|
||||
if (NULL == sem)
|
||||
if (!sem)
|
||||
return -EINVAL;
|
||||
|
||||
if (update_references(&sem->refcount, NULL))
|
||||
@ -542,3 +596,88 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
|
||||
{
|
||||
return amdgpu_cs_unreference_sem(sem);
|
||||
}
|
||||
|
||||
int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
|
||||
uint32_t *handle)
|
||||
{
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
|
||||
return drmSyncobjCreate(dev->fd, 0, handle);
|
||||
}
|
||||
|
||||
int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
|
||||
uint32_t handle)
|
||||
{
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
|
||||
return drmSyncobjDestroy(dev->fd, handle);
|
||||
}
|
||||
|
||||
int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
|
||||
uint32_t handle,
|
||||
int *shared_fd)
|
||||
{
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
|
||||
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
|
||||
}
|
||||
|
||||
int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
|
||||
int shared_fd,
|
||||
uint32_t *handle)
|
||||
{
|
||||
if (NULL == dev)
|
||||
return -EINVAL;
|
||||
|
||||
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
|
||||
}
|
||||
|
||||
int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
|
||||
amdgpu_context_handle context,
|
||||
amdgpu_bo_list_handle bo_list_handle,
|
||||
int num_chunks,
|
||||
struct drm_amdgpu_cs_chunk *chunks,
|
||||
uint64_t *seq_no)
|
||||
{
|
||||
union drm_amdgpu_cs cs = {0};
|
||||
uint64_t *chunk_array;
|
||||
int i, r;
|
||||
if (num_chunks == 0)
|
||||
return -EINVAL;
|
||||
|
||||
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
|
||||
for (i = 0; i < num_chunks; i++)
|
||||
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
|
||||
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
|
||||
cs.in.ctx_id = context->id;
|
||||
cs.in.bo_list_handle = bo_list_handle ? bo_list_handle->handle : 0;
|
||||
cs.in.num_chunks = num_chunks;
|
||||
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
|
||||
&cs, sizeof(cs));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (seq_no)
|
||||
*seq_no = cs.out.handle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
|
||||
struct drm_amdgpu_cs_chunk_data *data)
|
||||
{
|
||||
data->fence_data.handle = fence_info->handle->handle;
|
||||
data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
|
||||
}
|
||||
|
||||
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
|
||||
struct drm_amdgpu_cs_chunk_dep *dep)
|
||||
{
|
||||
dep->ip_type = fence->ip_type;
|
||||
dep->ip_instance = fence->ip_instance;
|
||||
dep->ring = fence->ring;
|
||||
dep->ctx_id = fence->context->id;
|
||||
dep->handle = fence->fence;
|
||||
}
|
||||
|
||||
@ -44,7 +44,6 @@
|
||||
#include "amdgpu_internal.h"
|
||||
#include "util_hash_table.h"
|
||||
#include "util_math.h"
|
||||
#include "amdgpu_asic_id.h"
|
||||
|
||||
#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
|
||||
#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
|
||||
@ -131,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth)
|
||||
|
||||
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
|
||||
{
|
||||
const struct amdgpu_asic_id *id;
|
||||
amdgpu_vamgr_deinit(&dev->vamgr_32);
|
||||
amdgpu_vamgr_deinit(&dev->vamgr);
|
||||
util_hash_table_destroy(dev->bo_flink_names);
|
||||
@ -140,6 +140,12 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev)
|
||||
close(dev->fd);
|
||||
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
|
||||
close(dev->flink_fd);
|
||||
if (dev->asic_ids) {
|
||||
for (id = dev->asic_ids; id->did; id++)
|
||||
free(id->marketing_name);
|
||||
|
||||
free(dev->asic_ids);
|
||||
}
|
||||
free(dev);
|
||||
}
|
||||
|
||||
@ -267,6 +273,12 @@ int amdgpu_device_initialize(int fd,
|
||||
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
|
||||
dev->dev_info.virtual_address_alignment);
|
||||
|
||||
r = amdgpu_parse_asic_ids(&dev->asic_ids);
|
||||
if (r) {
|
||||
fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.",
|
||||
__func__, r);
|
||||
}
|
||||
|
||||
*major_version = dev->major_version;
|
||||
*minor_version = dev->minor_version;
|
||||
*device_handle = dev;
|
||||
@ -297,13 +309,15 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev)
|
||||
|
||||
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
|
||||
{
|
||||
const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table;
|
||||
const struct amdgpu_asic_id *id;
|
||||
|
||||
while (t->did) {
|
||||
if ((t->did == dev->info.asic_id) &&
|
||||
(t->rid == dev->info.pci_rev_id))
|
||||
return t->marketing_name;
|
||||
t++;
|
||||
if (!dev->asic_ids)
|
||||
return NULL;
|
||||
|
||||
for (id = dev->asic_ids; id->did; id++) {
|
||||
if ((id->did == dev->info.asic_id) &&
|
||||
(id->rid == dev->info.pci_rev_id))
|
||||
return id->marketing_name;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
|
||||
@ -234,8 +234,9 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
|
||||
int amdgpu_query_gpu_info(amdgpu_device_handle dev,
|
||||
struct amdgpu_gpu_info *info)
|
||||
{
|
||||
if ((dev == NULL) || (info == NULL))
|
||||
if (!dev || !info)
|
||||
return -EINVAL;
|
||||
|
||||
/* Get ASIC info*/
|
||||
*info = dev->info;
|
||||
|
||||
@ -300,7 +301,7 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
|
||||
struct drm_amdgpu_info_gds gds_config = {};
|
||||
int r;
|
||||
|
||||
if (gds_info == NULL)
|
||||
if (!gds_info)
|
||||
return -EINVAL;
|
||||
|
||||
r = amdgpu_query_info(dev, AMDGPU_INFO_GDS_CONFIG,
|
||||
|
||||
@ -69,6 +69,12 @@ struct amdgpu_va {
|
||||
struct amdgpu_bo_va_mgr *vamgr;
|
||||
};
|
||||
|
||||
struct amdgpu_asic_id {
|
||||
uint32_t did;
|
||||
uint32_t rid;
|
||||
char *marketing_name;
|
||||
};
|
||||
|
||||
struct amdgpu_device {
|
||||
atomic_t refcount;
|
||||
int fd;
|
||||
@ -76,6 +82,8 @@ struct amdgpu_device {
|
||||
unsigned major_version;
|
||||
unsigned minor_version;
|
||||
|
||||
/** Lookup table of asic device id, revision id and marketing name */
|
||||
struct amdgpu_asic_id *asic_ids;
|
||||
/** List of buffer handles. Protected by bo_table_mutex. */
|
||||
struct util_hash_table *bo_handles;
|
||||
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
|
||||
@ -149,6 +157,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
|
||||
drm_private void
|
||||
amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size);
|
||||
|
||||
drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids);
|
||||
|
||||
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
|
||||
|
||||
drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
|
||||
|
||||
23
lib/libdrm/data/Makefile.am
Normal file
23
lib/libdrm/data/Makefile.am
Normal file
@ -0,0 +1,23 @@
|
||||
# Copyright © 2017 Advanced Micro Devices, Inc.
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
libdrmdatadir = @libdrmdatadir@
|
||||
dist_libdrmdata_DATA = amdgpu.ids
|
||||
547
lib/libdrm/data/Makefile.in
Normal file
547
lib/libdrm/data/Makefile.in
Normal file
@ -0,0 +1,547 @@
|
||||
# Makefile.in generated by automake 1.15 from Makefile.am.
|
||||
# @configure_input@
|
||||
|
||||
# Copyright (C) 1994-2014 Free Software Foundation, Inc.
|
||||
|
||||
# This Makefile.in is free software; the Free Software Foundation
|
||||
# gives unlimited permission to copy and/or distribute it,
|
||||
# with or without modifications, as long as this notice is preserved.
|
||||
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
|
||||
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
|
||||
# PARTICULAR PURPOSE.
|
||||
|
||||
@SET_MAKE@
|
||||
|
||||
# Copyright © 2017 Advanced Micro Devices, Inc.
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# on the rights to use, copy, modify, merge, publish, distribute, sub
|
||||
# license, and/or sell copies of the Software, and to permit persons to whom
|
||||
# the Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice (including the next
|
||||
# paragraph) shall be included in all copies or substantial portions of the
|
||||
# Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
VPATH = @srcdir@
|
||||
am__is_gnu_make = { \
|
||||
if test -z '$(MAKELEVEL)'; then \
|
||||
false; \
|
||||
elif test -n '$(MAKE_HOST)'; then \
|
||||
true; \
|
||||
elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
|
||||
true; \
|
||||
else \
|
||||
false; \
|
||||
fi; \
|
||||
}
|
||||
am__make_running_with_option = \
|
||||
case $${target_option-} in \
|
||||
?) ;; \
|
||||
*) echo "am__make_running_with_option: internal error: invalid" \
|
||||
"target option '$${target_option-}' specified" >&2; \
|
||||
exit 1;; \
|
||||
esac; \
|
||||
has_opt=no; \
|
||||
sane_makeflags=$$MAKEFLAGS; \
|
||||
if $(am__is_gnu_make); then \
|
||||
sane_makeflags=$$MFLAGS; \
|
||||
else \
|
||||
case $$MAKEFLAGS in \
|
||||
*\\[\ \ ]*) \
|
||||
bs=\\; \
|
||||
sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
|
||||
| sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
|
||||
esac; \
|
||||
fi; \
|
||||
skip_next=no; \
|
||||
strip_trailopt () \
|
||||
{ \
|
||||
flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
|
||||
}; \
|
||||
for flg in $$sane_makeflags; do \
|
||||
test $$skip_next = yes && { skip_next=no; continue; }; \
|
||||
case $$flg in \
|
||||
*=*|--*) continue;; \
|
||||
-*I) strip_trailopt 'I'; skip_next=yes;; \
|
||||
-*I?*) strip_trailopt 'I';; \
|
||||
-*O) strip_trailopt 'O'; skip_next=yes;; \
|
||||
-*O?*) strip_trailopt 'O';; \
|
||||
-*l) strip_trailopt 'l'; skip_next=yes;; \
|
||||
-*l?*) strip_trailopt 'l';; \
|
||||
-[dEDm]) skip_next=yes;; \
|
||||
-[JT]) skip_next=yes;; \
|
||||
esac; \
|
||||
case $$flg in \
|
||||
*$$target_option*) has_opt=yes; break;; \
|
||||
esac; \
|
||||
done; \
|
||||
test $$has_opt = yes
|
||||
am__make_dryrun = (target_option=n; $(am__make_running_with_option))
|
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|
||||
install-html: install-html-am
|
||||
|
||||
install-html-am:
|
||||
|
||||
install-info: install-info-am
|
||||
|
||||
install-info-am:
|
||||
|
||||
install-man:
|
||||
|
||||
install-pdf: install-pdf-am
|
||||
|
||||
install-pdf-am:
|
||||
|
||||
install-ps: install-ps-am
|
||||
|
||||
install-ps-am:
|
||||
|
||||
installcheck-am:
|
||||
|
||||
maintainer-clean: maintainer-clean-am
|
||||
-rm -f Makefile
|
||||
maintainer-clean-am: distclean-am maintainer-clean-generic
|
||||
|
||||
mostlyclean: mostlyclean-am
|
||||
|
||||
mostlyclean-am: mostlyclean-generic mostlyclean-libtool
|
||||
|
||||
pdf: pdf-am
|
||||
|
||||
pdf-am:
|
||||
|
||||
ps: ps-am
|
||||
|
||||
ps-am:
|
||||
|
||||
uninstall-am: uninstall-dist_libdrmdataDATA
|
||||
|
||||
.MAKE: install-am install-strip
|
||||
|
||||
.PHONY: all all-am check check-am clean clean-generic clean-libtool \
|
||||
cscopelist-am ctags-am distclean distclean-generic \
|
||||
distclean-libtool distdir dvi dvi-am html html-am info info-am \
|
||||
install install-am install-data install-data-am \
|
||||
install-dist_libdrmdataDATA install-dvi install-dvi-am \
|
||||
install-exec install-exec-am install-html install-html-am \
|
||||
install-info install-info-am install-man install-pdf \
|
||||
install-pdf-am install-ps install-ps-am install-strip \
|
||||
installcheck installcheck-am installdirs maintainer-clean \
|
||||
maintainer-clean-generic mostlyclean mostlyclean-generic \
|
||||
mostlyclean-libtool pdf pdf-am ps ps-am tags-am uninstall \
|
||||
uninstall-am uninstall-dist_libdrmdataDATA
|
||||
|
||||
.PRECIOUS: Makefile
|
||||
|
||||
|
||||
# Tell versions [3.59,3.63) of GNU make to not export all variables.
|
||||
# Otherwise a system limit (for SysV at least) may be exceeded.
|
||||
.NOEXPORT:
|
||||
159
lib/libdrm/data/amdgpu.ids
Normal file
159
lib/libdrm/data/amdgpu.ids
Normal file
@ -0,0 +1,159 @@
|
||||
# List of AMDGPU IDs
|
||||
#
|
||||
# Syntax:
|
||||
# device_id, revision_id, product_name <-- single tab after comma
|
||||
|
||||
1.0.0
|
||||
6600, 0, AMD Radeon HD 8600/8700M
|
||||
6600, 81, AMD Radeon (TM) R7 M370
|
||||
6601, 0, AMD Radeon (TM) HD 8500M/8700M
|
||||
6604, 0, AMD Radeon R7 M265 Series
|
||||
6604, 81, AMD Radeon (TM) R7 M350
|
||||
6605, 0, AMD Radeon R7 M260 Series
|
||||
6605, 81, AMD Radeon (TM) R7 M340
|
||||
6606, 0, AMD Radeon HD 8790M
|
||||
6607, 0, AMD Radeon (TM) HD8530M
|
||||
6608, 0, AMD FirePro W2100
|
||||
6610, 0, AMD Radeon HD 8600 Series
|
||||
6610, 81, AMD Radeon (TM) R7 350
|
||||
6610, 83, AMD Radeon (TM) R5 340
|
||||
6611, 0, AMD Radeon HD 8500 Series
|
||||
6613, 0, AMD Radeon HD 8500 series
|
||||
6617, C7, AMD Radeon R7 240 Series
|
||||
6640, 0, AMD Radeon HD 8950
|
||||
6640, 80, AMD Radeon (TM) R9 M380
|
||||
6646, 0, AMD Radeon R9 M280X
|
||||
6646, 80, AMD Radeon (TM) R9 M470X
|
||||
6647, 0, AMD Radeon R9 M270X
|
||||
6647, 80, AMD Radeon (TM) R9 M380
|
||||
6649, 0, AMD FirePro W5100
|
||||
6658, 0, AMD Radeon R7 200 Series
|
||||
665C, 0, AMD Radeon HD 7700 Series
|
||||
665D, 0, AMD Radeon R7 200 Series
|
||||
665F, 81, AMD Radeon (TM) R7 300 Series
|
||||
6660, 0, AMD Radeon HD 8600M Series
|
||||
6660, 81, AMD Radeon (TM) R5 M335
|
||||
6660, 83, AMD Radeon (TM) R5 M330
|
||||
6663, 0, AMD Radeon HD 8500M Series
|
||||
6663, 83, AMD Radeon (TM) R5 M320
|
||||
6664, 0, AMD Radeon R5 M200 Series
|
||||
6665, 0, AMD Radeon R5 M200 Series
|
||||
6665, 83, AMD Radeon (TM) R5 M320
|
||||
6667, 0, AMD Radeon R5 M200 Series
|
||||
666F, 0, AMD Radeon HD 8500M
|
||||
6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
|
||||
678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
|
||||
6798, 0, AMD Radeon HD 7900 Series
|
||||
679A, 0, AMD Radeon HD 7900 Series
|
||||
679B, 0, AMD Radeon HD 7900 Series
|
||||
679E, 0, AMD Radeon HD 7800 Series
|
||||
67A0, 0, AMD Radeon FirePro W9100
|
||||
67A1, 0, AMD Radeon FirePro W8100
|
||||
67B0, 0, AMD Radeon R9 200 Series
|
||||
67B0, 80, AMD Radeon (TM) R9 390 Series
|
||||
67B1, 0, AMD Radeon R9 200 Series
|
||||
67B1, 80, AMD Radeon (TM) R9 390 Series
|
||||
67B9, 0, AMD Radeon R9 200 Series
|
||||
67DF, C1, Radeon RX 580 Series
|
||||
67DF, C2, Radeon RX 570 Series
|
||||
67DF, C3, Radeon RX 580 Series
|
||||
67DF, C4, AMD Radeon (TM) RX 480 Graphics
|
||||
67DF, C5, AMD Radeon (TM) RX 470 Graphics
|
||||
67DF, C6, Radeon RX 570 Series
|
||||
67DF, C7, AMD Radeon (TM) RX 480 Graphics
|
||||
67DF, CF, AMD Radeon (TM) RX 470 Graphics
|
||||
67DF, E3, Radeon RX Series
|
||||
67DF, E7, Radeon RX 580 Series
|
||||
67DF, EF, Radeon RX 570 Series
|
||||
67C2, 01, AMD Radeon (TM) Pro V7350x2
|
||||
67C2, 02, AMD Radeon (TM) Pro V7300X
|
||||
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
|
||||
67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics
|
||||
67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics
|
||||
67D0, 01, AMD Radeon (TM) Pro V7350x2
|
||||
67D0, 02, AMD Radeon (TM) Pro V7300X
|
||||
67E0, 00, AMD Radeon (TM) Pro WX Series
|
||||
67E3, 00, AMD Radeon (TM) Pro WX 4100
|
||||
67E8, 00, AMD Radeon (TM) Pro WX Series
|
||||
67E8, 01, AMD Radeon (TM) Pro WX Series
|
||||
67E8, 80, AMD Radeon (TM) E9260 Graphics
|
||||
67EB, 00, AMD Radeon (TM) Pro V5300X
|
||||
67EF, C0, AMD Radeon (TM) RX Graphics
|
||||
67EF, C1, AMD Radeon (TM) RX 460 Graphics
|
||||
67EF, C3, Radeon RX Series
|
||||
67EF, C5, AMD Radeon (TM) RX 460 Graphics
|
||||
67EF, C7, AMD Radeon (TM) RX Graphics
|
||||
67EF, CF, AMD Radeon (TM) RX 460 Graphics
|
||||
67EF, E1, Radeon RX Series
|
||||
67EF, E3, Radeon RX Series
|
||||
67EF, E7, Radeon RX Series
|
||||
67EF, EF, AMD Radeon (TM) RX Graphics
|
||||
67EF, FF, Radeon RX Series
|
||||
67FF, C0, AMD Radeon (TM) RX Graphics
|
||||
67FF, C1, AMD Radeon (TM) RX Graphics
|
||||
67FF, FF, Radeon RX 550 Series
|
||||
6800, 0, AMD Radeon HD 7970M
|
||||
6801, 0, AMD Radeon(TM) HD8970M
|
||||
6808, 0, ATI FirePro V(FireGL V) Graphics Adapter
|
||||
6809, 0, ATI FirePro V(FireGL V) Graphics Adapter
|
||||
6810, 0, AMD Radeon(TM) HD 8800 Series
|
||||
6810, 81, AMD Radeon (TM) R7 370 Series
|
||||
6811, 0, AMD Radeon(TM) HD8800 Series
|
||||
6811, 81, AMD Radeon (TM) R7 300 Series
|
||||
6818, 0, AMD Radeon HD 7800 Series
|
||||
6819, 0, AMD Radeon HD 7800 Series
|
||||
6820, 0, AMD Radeon HD 8800M Series
|
||||
6820, 81, AMD Radeon (TM) R9 M375
|
||||
6820, 83, AMD Radeon (TM) R9 M375X
|
||||
6821, 0, AMD Radeon HD 8800M Series
|
||||
6821, 87, AMD Radeon (TM) R7 M380
|
||||
6821, 83, AMD Radeon R9 (TM) M370X
|
||||
6822, 0, AMD Radeon E8860
|
||||
6823, 0, AMD Radeon HD 8800M Series
|
||||
6825, 0, AMD Radeon HD 7800M Series
|
||||
6827, 0, AMD Radeon HD 7800M Series
|
||||
6828, 0, ATI FirePro V(FireGL V) Graphics Adapter
|
||||
682B, 0, AMD Radeon HD 8800M Series
|
||||
682B, 87, AMD Radeon (TM) R9 M360
|
||||
682C, 0, AMD FirePro W4100
|
||||
682D, 0, AMD Radeon HD 7700M Series
|
||||
682F, 0, AMD Radeon HD 7700M Series
|
||||
6835, 0, AMD Radeon R7 Series / HD 9000 Series
|
||||
6837, 0, AMD Radeon HD7700 Series
|
||||
683D, 0, AMD Radeon HD 7700 Series
|
||||
683F, 0, AMD Radeon HD 7700 Series
|
||||
6900, 0, AMD Radeon R7 M260
|
||||
6900, 81, AMD Radeon (TM) R7 M360
|
||||
6900, 83, AMD Radeon (TM) R7 M340
|
||||
6901, 0, AMD Radeon R5 M255
|
||||
6907, 0, AMD Radeon R5 M255
|
||||
6907, 87, AMD Radeon (TM) R5 M315
|
||||
6920, 0, AMD RADEON R9 M395X
|
||||
6920, 1, AMD RADEON R9 M390X
|
||||
6921, 0, AMD Radeon R9 M295X
|
||||
6929, 0, AMD FirePro S7150
|
||||
692B, 0, AMD FirePro W7100
|
||||
6938, 0, AMD Radeon R9 200 Series
|
||||
6938, F0, AMD Radeon R9 200 Series
|
||||
6938, F1, AMD Radeon (TM) R9 380 Series
|
||||
6939, F0, AMD Radeon R9 200 Series
|
||||
6939, 0, AMD Radeon R9 200 Series
|
||||
6939, F1, AMD Radeon (TM) R9 380 Series
|
||||
6985, 00, AMD Radeon Pro WX3100
|
||||
6995, 00, AMD Radeon Pro WX2100
|
||||
699F, C0, Radeon 500 Series
|
||||
699F, C3, Radeon 500 Series
|
||||
699F, C7, Radeon RX 550 Series
|
||||
7300, C1, AMD FirePro (TM) S9300 x2
|
||||
7300, C8, AMD Radeon (TM) R9 Fury Series
|
||||
7300, C9, Radeon (TM) Pro Duo
|
||||
7300, CB, AMD Radeon (TM) R9 Fury Series
|
||||
7300, CA, AMD Radeon (TM) R9 Fury Series
|
||||
9874, C4, AMD Radeon R7 Graphics
|
||||
9874, C5, AMD Radeon R6 Graphics
|
||||
9874, C6, AMD Radeon R6 Graphics
|
||||
9874, C7, AMD Radeon R5 Graphics
|
||||
9874, 81, AMD Radeon R6 Graphics
|
||||
9874, 87, AMD Radeon R5 Graphics
|
||||
9874, 85, AMD Radeon R6 Graphics
|
||||
9874, 84, AMD Radeon R7 Graphics
|
||||
@ -39,6 +39,7 @@ etna_cmd_stream_new
|
||||
etna_cmd_stream_del
|
||||
etna_cmd_stream_timestamp
|
||||
etna_cmd_stream_flush
|
||||
etna_cmd_stream_flush2
|
||||
etna_cmd_stream_finish
|
||||
etna_cmd_stream_reloc
|
||||
EOF
|
||||
|
||||
@ -177,7 +177,8 @@ static uint32_t bo2idx(struct etna_cmd_stream *stream, struct etna_bo *bo,
|
||||
return idx;
|
||||
}
|
||||
|
||||
static void flush(struct etna_cmd_stream *stream)
|
||||
static void flush(struct etna_cmd_stream *stream, int in_fence_fd,
|
||||
int *out_fence_fd)
|
||||
{
|
||||
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
|
||||
int ret, id = priv->pipe->id;
|
||||
@ -194,6 +195,14 @@ static void flush(struct etna_cmd_stream *stream)
|
||||
.stream_size = stream->offset * 4, /* in bytes */
|
||||
};
|
||||
|
||||
if (in_fence_fd != -1) {
|
||||
req.flags |= ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_NO_IMPLICIT;
|
||||
req.fence_fd = in_fence_fd;
|
||||
}
|
||||
|
||||
if (out_fence_fd)
|
||||
req.flags |= ETNA_SUBMIT_FENCE_FD_OUT;
|
||||
|
||||
ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT,
|
||||
&req, sizeof(req));
|
||||
|
||||
@ -208,11 +217,21 @@ static void flush(struct etna_cmd_stream *stream)
|
||||
bo->current_stream = NULL;
|
||||
etna_bo_del(bo);
|
||||
}
|
||||
|
||||
if (out_fence_fd)
|
||||
*out_fence_fd = req.fence_fd;
|
||||
}
|
||||
|
||||
void etna_cmd_stream_flush(struct etna_cmd_stream *stream)
|
||||
{
|
||||
flush(stream);
|
||||
flush(stream, -1, NULL);
|
||||
reset_buffer(stream);
|
||||
}
|
||||
|
||||
void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd,
|
||||
int *out_fence_fd)
|
||||
{
|
||||
flush(stream, in_fence_fd, out_fence_fd);
|
||||
reset_buffer(stream);
|
||||
}
|
||||
|
||||
@ -220,7 +239,7 @@ void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
|
||||
{
|
||||
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
|
||||
|
||||
flush(stream);
|
||||
flush(stream, -1, NULL);
|
||||
etna_pipe_wait(priv->pipe, priv->last_timestamp, 5000);
|
||||
reset_buffer(stream);
|
||||
}
|
||||
|
||||
@ -154,6 +154,12 @@ struct drm_etnaviv_gem_submit_bo {
|
||||
* one or more cmdstream buffers. This allows for conditional execution
|
||||
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
|
||||
*/
|
||||
#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
|
||||
#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
|
||||
#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
|
||||
#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
|
||||
ETNA_SUBMIT_FENCE_FD_IN | \
|
||||
ETNA_SUBMIT_FENCE_FD_OUT)
|
||||
#define ETNA_PIPE_3D 0x00
|
||||
#define ETNA_PIPE_2D 0x01
|
||||
#define ETNA_PIPE_VG 0x02
|
||||
@ -167,6 +173,8 @@ struct drm_etnaviv_gem_submit {
|
||||
__u64 bos; /* in, ptr to array of submit_bo's */
|
||||
__u64 relocs; /* in, ptr to array of submit_reloc's */
|
||||
__u64 stream; /* in, ptr to cmdstream */
|
||||
__u32 flags; /* in, mask of ETNA_SUBMIT_x */
|
||||
__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
|
||||
};
|
||||
|
||||
/* The normal way to synchronize with the GPU is just to CPU_PREP on
|
||||
|
||||
@ -142,6 +142,8 @@ struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t siz
|
||||
void etna_cmd_stream_del(struct etna_cmd_stream *stream);
|
||||
uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream);
|
||||
void etna_cmd_stream_flush(struct etna_cmd_stream *stream);
|
||||
void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd,
|
||||
int *out_fence_fd);
|
||||
void etna_cmd_stream_finish(struct etna_cmd_stream *stream);
|
||||
|
||||
static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream)
|
||||
|
||||
@ -31,6 +31,10 @@
|
||||
#include <stdint.h>
|
||||
#include "exynos_drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct exynos_device {
|
||||
int fd;
|
||||
};
|
||||
@ -109,4 +113,8 @@ int exynos_handle_event(struct exynos_device *dev,
|
||||
struct exynos_event_context *ctx);
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* EXYNOS_DRMIF_H_ */
|
||||
|
||||
@ -112,13 +112,13 @@ struct fd_device * fd_device_ref(struct fd_device *dev)
|
||||
|
||||
static void fd_device_del_impl(struct fd_device *dev)
|
||||
{
|
||||
int close_fd = dev->closefd ? dev->fd : -1;
|
||||
fd_bo_cache_cleanup(&dev->bo_cache, 0);
|
||||
drmHashDestroy(dev->handle_table);
|
||||
drmHashDestroy(dev->name_table);
|
||||
dev->funcs->destroy(dev);
|
||||
if (dev->closefd)
|
||||
close(dev->fd);
|
||||
free(dev);
|
||||
if (close_fd >= 0)
|
||||
close(close_fd);
|
||||
}
|
||||
|
||||
drm_private void fd_device_del_locked(struct fd_device *dev)
|
||||
|
||||
@ -51,6 +51,7 @@ extern "C" {
|
||||
#define DRM_AMDGPU_GEM_OP 0x10
|
||||
#define DRM_AMDGPU_GEM_USERPTR 0x11
|
||||
#define DRM_AMDGPU_WAIT_FENCES 0x12
|
||||
#define DRM_AMDGPU_VM 0x13
|
||||
|
||||
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
|
||||
@ -65,6 +66,7 @@ extern "C" {
|
||||
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
|
||||
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
|
||||
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
|
||||
|
||||
#define AMDGPU_GEM_DOMAIN_CPU 0x1
|
||||
#define AMDGPU_GEM_DOMAIN_GTT 0x2
|
||||
@ -190,6 +192,26 @@ union drm_amdgpu_ctx {
|
||||
union drm_amdgpu_ctx_out out;
|
||||
};
|
||||
|
||||
/* vm ioctl */
|
||||
#define AMDGPU_VM_OP_RESERVE_VMID 1
|
||||
#define AMDGPU_VM_OP_UNRESERVE_VMID 2
|
||||
|
||||
struct drm_amdgpu_vm_in {
|
||||
/** AMDGPU_VM_OP_* */
|
||||
__u32 op;
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_vm_out {
|
||||
/** For future use, no flags defined so far */
|
||||
__u64 flags;
|
||||
};
|
||||
|
||||
union drm_amdgpu_vm {
|
||||
struct drm_amdgpu_vm_in in;
|
||||
struct drm_amdgpu_vm_out out;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is not a reliable API and you should expect it to fail for any
|
||||
* number of reasons and have fallback path that do not use userptr to
|
||||
@ -295,7 +317,10 @@ union drm_amdgpu_gem_wait_idle {
|
||||
};
|
||||
|
||||
struct drm_amdgpu_wait_cs_in {
|
||||
/** Command submission handle */
|
||||
/* Command submission handle
|
||||
* handle equals 0 means none to wait for
|
||||
* handle equals ~0ull means wait for the latest sequence number
|
||||
*/
|
||||
__u64 handle;
|
||||
/** Absolute timeout to wait */
|
||||
__u64 timeout;
|
||||
@ -406,13 +431,17 @@ struct drm_amdgpu_gem_va {
|
||||
#define AMDGPU_HW_IP_UVD 3
|
||||
#define AMDGPU_HW_IP_VCE 4
|
||||
#define AMDGPU_HW_IP_UVD_ENC 5
|
||||
#define AMDGPU_HW_IP_NUM 6
|
||||
#define AMDGPU_HW_IP_VCN_DEC 6
|
||||
#define AMDGPU_HW_IP_VCN_ENC 7
|
||||
#define AMDGPU_HW_IP_NUM 8
|
||||
|
||||
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
|
||||
|
||||
#define AMDGPU_CHUNK_ID_IB 0x01
|
||||
#define AMDGPU_CHUNK_ID_FENCE 0x02
|
||||
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
|
||||
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
|
||||
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
|
||||
|
||||
struct drm_amdgpu_cs_chunk {
|
||||
__u32 chunk_id;
|
||||
@ -480,6 +509,10 @@ struct drm_amdgpu_cs_chunk_fence {
|
||||
__u32 offset;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_chunk_sem {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_chunk_data {
|
||||
union {
|
||||
struct drm_amdgpu_cs_chunk_ib ib_data;
|
||||
@ -576,6 +609,8 @@ struct drm_amdgpu_cs_chunk_data {
|
||||
#define AMDGPU_INFO_SENSOR_VDDNB 0x6
|
||||
/* Subquery id: Query graphics voltage */
|
||||
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
|
||||
/* Number of VRAM page faults on CPU access. */
|
||||
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
|
||||
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
||||
@ -764,6 +799,25 @@ struct drm_amdgpu_info_device {
|
||||
__u64 cntl_sb_buf_gpu_addr;
|
||||
/* NGG Parameter Cache */
|
||||
__u64 param_buf_gpu_addr;
|
||||
__u32 prim_buf_size;
|
||||
__u32 pos_buf_size;
|
||||
__u32 cntl_sb_buf_size;
|
||||
__u32 param_buf_size;
|
||||
/* wavefront size*/
|
||||
__u32 wave_front_size;
|
||||
/* shader visible vgprs*/
|
||||
__u32 num_shader_visible_vgprs;
|
||||
/* CU per shader array*/
|
||||
__u32 num_cu_per_sh;
|
||||
/* number of tcc blocks*/
|
||||
__u32 num_tcc_blocks;
|
||||
/* gs vgt table depth*/
|
||||
__u32 gs_vgt_table_depth;
|
||||
/* gs primitive buffer depth*/
|
||||
__u32 gs_prim_buffer_depth;
|
||||
/* max gs wavefront per vgt*/
|
||||
__u32 max_gs_waves_per_vgt;
|
||||
__u32 _pad1;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
@ -816,6 +870,7 @@ struct drm_amdgpu_info_vce_clock_table {
|
||||
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
|
||||
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
|
||||
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
|
||||
#define AMDGPU_FAMILY_RV 142 /* Raven */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
@ -26,6 +26,10 @@
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
|
||||
((__u32)(c) << 16) | ((__u32)(d) << 24))
|
||||
|
||||
@ -37,10 +41,17 @@
|
||||
/* 8 bpp Red */
|
||||
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
|
||||
|
||||
/* 16 bpp Red */
|
||||
#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
|
||||
|
||||
/* 16 bpp RG */
|
||||
#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
|
||||
#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
|
||||
|
||||
/* 32 bpp RG */
|
||||
#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
|
||||
#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
|
||||
|
||||
/* 8 bpp RGB */
|
||||
#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
|
||||
#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
|
||||
@ -102,6 +113,20 @@
|
||||
|
||||
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
|
||||
|
||||
/*
|
||||
* 2 plane RGB + A
|
||||
* index 0 = RGB plane, same format as the corresponding non _A8 format has
|
||||
* index 1 = A plane, [7:0] A
|
||||
*/
|
||||
#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
|
||||
#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
|
||||
#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
|
||||
#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
|
||||
#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
|
||||
#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
|
||||
#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
|
||||
#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
|
||||
|
||||
/*
|
||||
* 2 plane YCbCr
|
||||
* index 0 = Y plane, [7:0] Y
|
||||
@ -150,11 +175,14 @@
|
||||
|
||||
/* Vendor Ids: */
|
||||
#define DRM_FORMAT_MOD_NONE 0
|
||||
#define DRM_FORMAT_MOD_VENDOR_NONE 0
|
||||
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
|
||||
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
|
||||
#define DRM_FORMAT_MOD_VENDOR_NV 0x03
|
||||
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
|
||||
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
|
||||
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
|
||||
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
|
||||
/* add more to the end as needed */
|
||||
|
||||
#define fourcc_mod_code(vendor, val) \
|
||||
@ -168,6 +196,16 @@
|
||||
* authoritative source for all of these.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Linear Layout
|
||||
*
|
||||
* Just plain linear layout. Note that this is different from no specifying any
|
||||
* modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
|
||||
* which tells the driver to also take driver-internal information into account
|
||||
* and so might actually result in a tiled framebuffer.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
|
||||
|
||||
/* Intel framebuffer modifiers */
|
||||
|
||||
/*
|
||||
@ -229,4 +267,113 @@
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
|
||||
|
||||
/* Vivante framebuffer modifiers */
|
||||
|
||||
/*
|
||||
* Vivante 4x4 tiling layout
|
||||
*
|
||||
* This is a simple tiled layout using tiles of 4x4 pixels in a row-major
|
||||
* layout.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
|
||||
|
||||
/*
|
||||
* Vivante 64x64 super-tiling layout
|
||||
*
|
||||
* This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
|
||||
* contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
|
||||
* major layout.
|
||||
*
|
||||
* For more information: see
|
||||
* https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
|
||||
|
||||
/*
|
||||
* Vivante 4x4 tiling layout for dual-pipe
|
||||
*
|
||||
* Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
|
||||
* different base address. Offsets from the base addresses are therefore halved
|
||||
* compared to the non-split tiled layout.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
|
||||
|
||||
/*
|
||||
* Vivante 64x64 super-tiling layout for dual-pipe
|
||||
*
|
||||
* Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
|
||||
* starts at a different base address. Offsets from the base addresses are
|
||||
* therefore halved compared to the non-split super-tiled layout.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
|
||||
|
||||
/* NVIDIA Tegra frame buffer modifiers */
|
||||
|
||||
/*
|
||||
* Some modifiers take parameters, for example the number of vertical GOBs in
|
||||
* a block. Reserve the lower 32 bits for parameters
|
||||
*/
|
||||
#define __fourcc_mod_tegra_mode_shift 32
|
||||
#define fourcc_mod_tegra_code(val, params) \
|
||||
fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
|
||||
#define fourcc_mod_tegra_mod(m) \
|
||||
(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
|
||||
#define fourcc_mod_tegra_param(m) \
|
||||
(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
|
||||
|
||||
/*
|
||||
* Tegra Tiled Layout, used by Tegra 2, 3 and 4.
|
||||
*
|
||||
* Pixels are arranged in simple tiles of 16 x 16 bytes.
|
||||
*/
|
||||
#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
|
||||
|
||||
/*
|
||||
* Tegra 16Bx2 Block Linear layout, used by TK1/TX1
|
||||
*
|
||||
* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
|
||||
* vertically by a power of 2 (1 to 32 GOBs) to form a block.
|
||||
*
|
||||
* Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
|
||||
*
|
||||
* Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
|
||||
* Valid values are:
|
||||
*
|
||||
* 0 == ONE_GOB
|
||||
* 1 == TWO_GOBS
|
||||
* 2 == FOUR_GOBS
|
||||
* 3 == EIGHT_GOBS
|
||||
* 4 == SIXTEEN_GOBS
|
||||
* 5 == THIRTYTWO_GOBS
|
||||
*
|
||||
* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
|
||||
* in full detail.
|
||||
*/
|
||||
#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
|
||||
|
||||
/*
|
||||
* Broadcom VC4 "T" format
|
||||
*
|
||||
* This is the primary layout that the V3D GPU can texture from (it
|
||||
* can't do linear). The T format has:
|
||||
*
|
||||
* - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
|
||||
* pixels at 32 bit depth.
|
||||
*
|
||||
* - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
|
||||
* 16x16 pixels).
|
||||
*
|
||||
* - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
|
||||
* even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
|
||||
* they're (TR, BR, BL, TL), where bottom left is start of memory.
|
||||
*
|
||||
* - an image made of 4k tiles in rows either left-to-right (even rows of 4k
|
||||
* tiles) or right-to-left (odd rows of 4k tiles).
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRM_FOURCC_H */
|
||||
|
||||
@ -34,6 +34,10 @@
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* SAREA area needs to be at least a page */
|
||||
#if defined(__alpha__)
|
||||
#define SAREA_MAX 0x2000U
|
||||
@ -81,4 +85,8 @@ typedef struct drm_sarea_drawable drm_sarea_drawable_t;
|
||||
typedef struct drm_sarea_frame drm_sarea_frame_t;
|
||||
typedef struct drm_sarea drm_sarea_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRM_SAREA_H_ */
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
* IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _VC4_DRM_H_
|
||||
#define _VC4_DRM_H_
|
||||
#ifndef _UAPI_VC4_DRM_H_
|
||||
#define _UAPI_VC4_DRM_H_
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
@ -38,6 +38,8 @@ extern "C" {
|
||||
#define DRM_VC4_CREATE_SHADER_BO 0x05
|
||||
#define DRM_VC4_GET_HANG_STATE 0x06
|
||||
#define DRM_VC4_GET_PARAM 0x07
|
||||
#define DRM_VC4_SET_TILING 0x08
|
||||
#define DRM_VC4_GET_TILING 0x09
|
||||
|
||||
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
|
||||
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
|
||||
@ -47,6 +49,8 @@ extern "C" {
|
||||
#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
|
||||
#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
|
||||
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
|
||||
#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
|
||||
#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
|
||||
|
||||
struct drm_vc4_submit_rcl_surface {
|
||||
__u32 hindex; /* Handle index, or ~0 if not present. */
|
||||
@ -295,8 +299,20 @@ struct drm_vc4_get_param {
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
struct drm_vc4_get_tiling {
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
__u64 modifier;
|
||||
};
|
||||
|
||||
struct drm_vc4_set_tiling {
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
__u64 modifier;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _VC4_DRM_H_ */
|
||||
#endif /* _UAPI_VC4_DRM_H_ */
|
||||
|
||||
@ -23,7 +23,8 @@ amdgpu_test_SOURCES = \
|
||||
basic_tests.c \
|
||||
bo_tests.c \
|
||||
cs_tests.c \
|
||||
uvd_messages.h \
|
||||
decode_messages.h \
|
||||
vce_tests.c \
|
||||
vce_ib.h \
|
||||
frame.h
|
||||
frame.h \
|
||||
vcn_tests.c
|
||||
|
||||
@ -85,6 +85,12 @@ static CU_SuiteInfo suites[] = {
|
||||
.pCleanupFunc = suite_vce_tests_clean,
|
||||
.pTests = vce_tests,
|
||||
},
|
||||
{
|
||||
.pName = "VCN Tests",
|
||||
.pInitFunc = suite_vcn_tests_init,
|
||||
.pCleanupFunc = suite_vcn_tests_clean,
|
||||
.pTests = vcn_tests,
|
||||
},
|
||||
CU_SUITE_INFO_NULL,
|
||||
};
|
||||
|
||||
@ -264,25 +270,25 @@ static void amdgpu_print_devices()
|
||||
/* Find a match AMD device in PCI bus
|
||||
* Return the index of the device or -1 if not found
|
||||
*/
|
||||
static int amdgpu_find_device(uint8_t bus, uint8_t dev)
|
||||
static int amdgpu_find_device(uint8_t bus, uint16_t dev)
|
||||
{
|
||||
int i;
|
||||
drmDevicePtr device;
|
||||
|
||||
for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++)
|
||||
for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
|
||||
if (drmGetDevice2(drm_amdgpu[i],
|
||||
DRM_DEVICE_GET_PCI_REVISION,
|
||||
&device) == 0) {
|
||||
if (device->bustype == DRM_BUS_PCI)
|
||||
if (device->businfo.pci->bus == bus &&
|
||||
device->businfo.pci->dev == dev) {
|
||||
|
||||
if ((bus == 0xFF || device->businfo.pci->bus == bus) &&
|
||||
device->deviceinfo.pci->device_id == dev) {
|
||||
drmFreeDevice(&device);
|
||||
return i;
|
||||
}
|
||||
|
||||
drmFreeDevice(&device);
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
@ -325,7 +331,7 @@ int main(int argc, char **argv)
|
||||
pci_bus_id = atoi(optarg);
|
||||
break;
|
||||
case 'd':
|
||||
pci_device_id = atoi(optarg);
|
||||
sscanf(optarg, "%x", &pci_device_id);
|
||||
break;
|
||||
case 'p':
|
||||
display_devices = 1;
|
||||
@ -359,10 +365,10 @@ int main(int argc, char **argv)
|
||||
exit(EXIT_SUCCESS);
|
||||
}
|
||||
|
||||
if (pci_bus_id > 0) {
|
||||
if (pci_bus_id > 0 || pci_device_id) {
|
||||
/* A device was specified to run the test */
|
||||
test_device_index = amdgpu_find_device((uint8_t)pci_bus_id,
|
||||
(uint8_t)pci_device_id);
|
||||
test_device_index = amdgpu_find_device(pci_bus_id,
|
||||
pci_device_id);
|
||||
|
||||
if (test_device_index >= 0) {
|
||||
/* Most tests run on device of drm_amdgpu[0].
|
||||
|
||||
@ -104,6 +104,21 @@ int suite_vce_tests_clean();
|
||||
*/
|
||||
extern CU_TestInfo vce_tests[];
|
||||
|
||||
/**
|
||||
+ * Initialize vcn test suite
|
||||
+ */
|
||||
int suite_vcn_tests_init();
|
||||
|
||||
/**
|
||||
+ * Deinitialize vcn test suite
|
||||
+ */
|
||||
int suite_vcn_tests_clean();
|
||||
|
||||
/**
|
||||
+ * Tests in vcn test suite
|
||||
+ */
|
||||
extern CU_TestInfo vcn_tests[];
|
||||
|
||||
/**
|
||||
* Helper functions
|
||||
*/
|
||||
|
||||
@ -45,6 +45,7 @@ static void amdgpu_query_info_test(void);
|
||||
static void amdgpu_memory_alloc(void);
|
||||
static void amdgpu_command_submission_gfx(void);
|
||||
static void amdgpu_command_submission_compute(void);
|
||||
static void amdgpu_command_submission_multi_fence(void);
|
||||
static void amdgpu_command_submission_sdma(void);
|
||||
static void amdgpu_userptr_test(void);
|
||||
static void amdgpu_semaphore_test(void);
|
||||
@ -59,6 +60,7 @@ CU_TestInfo basic_tests[] = {
|
||||
{ "Userptr Test", amdgpu_userptr_test },
|
||||
{ "Command submission Test (GFX)", amdgpu_command_submission_gfx },
|
||||
{ "Command submission Test (Compute)", amdgpu_command_submission_compute },
|
||||
{ "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
|
||||
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
|
||||
{ "SW semaphore Test", amdgpu_semaphore_test },
|
||||
CU_TEST_INFO_NULL,
|
||||
@ -1149,6 +1151,104 @@ static void amdgpu_command_submission_sdma(void)
|
||||
amdgpu_command_submission_sdma_copy_linear();
|
||||
}
|
||||
|
||||
static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all)
|
||||
{
|
||||
amdgpu_context_handle context_handle;
|
||||
amdgpu_bo_handle ib_result_handle, ib_result_ce_handle;
|
||||
void *ib_result_cpu, *ib_result_ce_cpu;
|
||||
uint64_t ib_result_mc_address, ib_result_ce_mc_address;
|
||||
struct amdgpu_cs_request ibs_request[2] = {0};
|
||||
struct amdgpu_cs_ib_info ib_info[2];
|
||||
struct amdgpu_cs_fence fence_status[2] = {0};
|
||||
uint32_t *ptr;
|
||||
uint32_t expired;
|
||||
amdgpu_bo_list_handle bo_list;
|
||||
amdgpu_va_handle va_handle, va_handle_ce;
|
||||
int r;
|
||||
int i, ib_cs_num = 2;
|
||||
|
||||
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_result_handle, &ib_result_cpu,
|
||||
&ib_result_mc_address, &va_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_result_ce_handle, &ib_result_ce_cpu,
|
||||
&ib_result_ce_mc_address, &va_handle_ce);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_get_bo_list(device_handle, ib_result_handle,
|
||||
ib_result_ce_handle, &bo_list);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info));
|
||||
|
||||
/* IT_SET_CE_DE_COUNTERS */
|
||||
ptr = ib_result_ce_cpu;
|
||||
ptr[0] = 0xc0008900;
|
||||
ptr[1] = 0;
|
||||
ptr[2] = 0xc0008400;
|
||||
ptr[3] = 1;
|
||||
ib_info[0].ib_mc_address = ib_result_ce_mc_address;
|
||||
ib_info[0].size = 4;
|
||||
ib_info[0].flags = AMDGPU_IB_FLAG_CE;
|
||||
|
||||
/* IT_WAIT_ON_CE_COUNTER */
|
||||
ptr = ib_result_cpu;
|
||||
ptr[0] = 0xc0008600;
|
||||
ptr[1] = 0x00000001;
|
||||
ib_info[1].ib_mc_address = ib_result_mc_address;
|
||||
ib_info[1].size = 2;
|
||||
|
||||
for (i = 0; i < ib_cs_num; i++) {
|
||||
ibs_request[i].ip_type = AMDGPU_HW_IP_GFX;
|
||||
ibs_request[i].number_of_ibs = 2;
|
||||
ibs_request[i].ibs = ib_info;
|
||||
ibs_request[i].resources = bo_list;
|
||||
ibs_request[i].fence_info.handle = NULL;
|
||||
}
|
||||
|
||||
r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num);
|
||||
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
for (i = 0; i < ib_cs_num; i++) {
|
||||
fence_status[i].context = context_handle;
|
||||
fence_status[i].ip_type = AMDGPU_HW_IP_GFX;
|
||||
fence_status[i].fence = ibs_request[i].seq_no;
|
||||
}
|
||||
|
||||
r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all,
|
||||
AMDGPU_TIMEOUT_INFINITE,
|
||||
&expired, NULL);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
|
||||
ib_result_mc_address, 4096);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce,
|
||||
ib_result_ce_mc_address, 4096);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_list_destroy(bo_list);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void amdgpu_command_submission_multi_fence(void)
|
||||
{
|
||||
amdgpu_command_submission_multi_fence_wait_all(true);
|
||||
amdgpu_command_submission_multi_fence_wait_all(false);
|
||||
}
|
||||
|
||||
static void amdgpu_userptr_test(void)
|
||||
{
|
||||
int i, r, j;
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
#include "util_math.h"
|
||||
|
||||
#include "amdgpu_test.h"
|
||||
#include "uvd_messages.h"
|
||||
#include "decode_messages.h"
|
||||
#include "amdgpu_drm.h"
|
||||
#include "amdgpu_internal.h"
|
||||
|
||||
@ -289,7 +289,8 @@ static void amdgpu_cs_uvd_decode(void)
|
||||
r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
|
||||
memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg));
|
||||
memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg));
|
||||
|
||||
if (family_id >= AMDGPU_FAMILY_VI) {
|
||||
ptr[0x10] = 7;
|
||||
@ -377,7 +378,7 @@ static void amdgpu_cs_uvd_decode(void)
|
||||
/* TODO: use a real CRC32 */
|
||||
for (i = 0, sum = 0; i < dt_size; ++i)
|
||||
sum += ptr[i];
|
||||
CU_ASSERT_EQUAL(sum, 0x20345d8);
|
||||
CU_ASSERT_EQUAL(sum, SUM_DECODE);
|
||||
|
||||
r = amdgpu_bo_cpu_unmap(buf_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
848
lib/libdrm/tests/amdgpu/decode_messages.h
Normal file
848
lib/libdrm/tests/amdgpu/decode_messages.h
Normal file
@ -0,0 +1,848 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DECODE_MESSAGES_H_
|
||||
#define _DECODE_MESSAGES_H_
|
||||
|
||||
#define SUM_DECODE 0x20345d8
|
||||
|
||||
static const uint8_t uvd_create_msg[] = {
|
||||
0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00,
|
||||
0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t uvd_bitstream[] ={
|
||||
0x00,0x00,0x01,0x25,0xb8,0x20,0x20,0x21,0x44,0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,
|
||||
0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
|
||||
0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
|
||||
0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,
|
||||
0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,0x00,0xa2,0xb8,0x20,0x20,0x21,0x44,
|
||||
0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
|
||||
0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
|
||||
0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,
|
||||
0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,
|
||||
0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,
|
||||
0x00,0x51,0x2e,0x08,0x08,0x08,0x51,0x31,0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,
|
||||
0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
|
||||
0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
|
||||
0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,
|
||||
0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,0x00,0x79,0xae,0x08,0x08,0x08,0x51,0x31,
|
||||
0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
|
||||
0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
|
||||
0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,
|
||||
0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,
|
||||
0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,
|
||||
0x00,0x28,0x8b,0x82,0x02,0x02,0x14,0x4c,0x50,0x00,0x15,0x79,0xbe,0xfb,0xef,0xbe,
|
||||
0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
|
||||
0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
|
||||
0xbe,0xfb,0xef,0xf8,0x7f,0xfc,0x25,0x80,0xe0,0x00,0x20,0x2a,0x00,0x02,0x03,0xa0,
|
||||
0x00,0xd0,0x00,0x10,0x1a,0x4c,0xb9,0x47,0x3e,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
|
||||
0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
|
||||
0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
|
||||
0xeb,0xae,0xba,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t uvd_decode_msg[] = {
|
||||
0xe4,0x0d,0x00,0x00,0x01,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t avc_decode_msg[] = {
|
||||
0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t uvd_destroy_msg[] = {
|
||||
0xe4,0x0d,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t uvd_it_scaling_table[] = {
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
|
||||
};
|
||||
|
||||
static const uint8_t vcn_dec_create_msg[] = {
|
||||
0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00,
|
||||
0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t vcn_dec_decode_msg[] = {
|
||||
0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
|
||||
0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00,
|
||||
0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00,
|
||||
0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
|
||||
0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00,
|
||||
0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00,
|
||||
0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
|
||||
0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
static const uint8_t vcn_dec_destroy_msg[] = {
|
||||
0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,
|
||||
0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
#endif /* _DECODE_MESSAGES_H_ */
|
||||
410
lib/libdrm/tests/amdgpu/vcn_tests.c
Normal file
410
lib/libdrm/tests/amdgpu/vcn_tests.c
Normal file
@ -0,0 +1,410 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "CUnit/Basic.h"
|
||||
|
||||
#include "util_math.h"
|
||||
|
||||
#include "amdgpu_test.h"
|
||||
#include "amdgpu_drm.h"
|
||||
#include "amdgpu_internal.h"
|
||||
#include "decode_messages.h"
|
||||
|
||||
#define IB_SIZE 4096
|
||||
#define MAX_RESOURCES 16
|
||||
|
||||
struct amdgpu_vcn_bo {
|
||||
amdgpu_bo_handle handle;
|
||||
amdgpu_va_handle va_handle;
|
||||
uint64_t addr;
|
||||
uint64_t size;
|
||||
uint8_t *ptr;
|
||||
};
|
||||
|
||||
static amdgpu_device_handle device_handle;
|
||||
static uint32_t major_version;
|
||||
static uint32_t minor_version;
|
||||
static uint32_t family_id;
|
||||
|
||||
static amdgpu_context_handle context_handle;
|
||||
static amdgpu_bo_handle ib_handle;
|
||||
static amdgpu_va_handle ib_va_handle;
|
||||
static uint64_t ib_mc_address;
|
||||
static uint32_t *ib_cpu;
|
||||
|
||||
static amdgpu_bo_handle resources[MAX_RESOURCES];
|
||||
static unsigned num_resources;
|
||||
|
||||
static void amdgpu_cs_vcn_dec_create(void);
|
||||
static void amdgpu_cs_vcn_dec_decode(void);
|
||||
static void amdgpu_cs_vcn_dec_destroy(void);
|
||||
|
||||
static void amdgpu_cs_vcn_enc_create(void);
|
||||
static void amdgpu_cs_vcn_enc_encode(void);
|
||||
static void amdgpu_cs_vcn_enc_destroy(void);
|
||||
|
||||
CU_TestInfo vcn_tests[] = {
|
||||
|
||||
{ "VCN DEC create", amdgpu_cs_vcn_dec_create },
|
||||
{ "VCN DEC decode", amdgpu_cs_vcn_dec_decode },
|
||||
{ "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy },
|
||||
|
||||
{ "VCN ENC create", amdgpu_cs_vcn_enc_create },
|
||||
{ "VCN ENC decode", amdgpu_cs_vcn_enc_encode },
|
||||
{ "VCN ENC destroy", amdgpu_cs_vcn_enc_destroy },
|
||||
CU_TEST_INFO_NULL,
|
||||
};
|
||||
|
||||
int suite_vcn_tests_init(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
|
||||
&minor_version, &device_handle);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
family_id = device_handle->info.family_id;
|
||||
|
||||
if (family_id < AMDGPU_FAMILY_RV) {
|
||||
printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
|
||||
return CUE_SUCCESS;
|
||||
}
|
||||
|
||||
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
|
||||
AMDGPU_GEM_DOMAIN_GTT, 0,
|
||||
&ib_handle, (void**)&ib_cpu,
|
||||
&ib_mc_address, &ib_va_handle);
|
||||
if (r)
|
||||
return CUE_SINIT_FAILED;
|
||||
|
||||
return CUE_SUCCESS;
|
||||
}
|
||||
|
||||
int suite_vcn_tests_clean(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (family_id < AMDGPU_FAMILY_RV) {
|
||||
r = amdgpu_device_deinitialize(device_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
} else {
|
||||
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
|
||||
ib_mc_address, IB_SIZE);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
r = amdgpu_cs_ctx_free(context_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
|
||||
r = amdgpu_device_deinitialize(device_handle);
|
||||
if (r)
|
||||
return CUE_SCLEAN_FAILED;
|
||||
}
|
||||
|
||||
return CUE_SUCCESS;
|
||||
}
|
||||
|
||||
static int submit(unsigned ndw, unsigned ip)
|
||||
{
|
||||
struct amdgpu_cs_request ibs_request = {0};
|
||||
struct amdgpu_cs_ib_info ib_info = {0};
|
||||
struct amdgpu_cs_fence fence_status = {0};
|
||||
uint32_t expired;
|
||||
int r;
|
||||
|
||||
ib_info.ib_mc_address = ib_mc_address;
|
||||
ib_info.size = ndw;
|
||||
|
||||
ibs_request.ip_type = ip;
|
||||
|
||||
r = amdgpu_bo_list_create(device_handle, num_resources, resources,
|
||||
NULL, &ibs_request.resources);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ibs_request.number_of_ibs = 1;
|
||||
ibs_request.ibs = &ib_info;
|
||||
ibs_request.fence_info.handle = NULL;
|
||||
|
||||
r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = amdgpu_bo_list_destroy(ibs_request.resources);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
fence_status.context = context_handle;
|
||||
fence_status.ip_type = ip;
|
||||
fence_status.fence = ibs_request.seq_no;
|
||||
|
||||
r = amdgpu_cs_query_fence_status(&fence_status,
|
||||
AMDGPU_TIMEOUT_INFINITE,
|
||||
0, &expired);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
|
||||
unsigned size, unsigned domain)
|
||||
{
|
||||
struct amdgpu_bo_alloc_request req = {0};
|
||||
amdgpu_bo_handle buf_handle;
|
||||
amdgpu_va_handle va_handle;
|
||||
uint64_t va = 0;
|
||||
int r;
|
||||
|
||||
req.alloc_size = ALIGN(size, 4096);
|
||||
req.preferred_heap = domain;
|
||||
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
r = amdgpu_va_range_alloc(device_handle,
|
||||
amdgpu_gpu_va_range_general,
|
||||
req.alloc_size, 1, 0, &va,
|
||||
&va_handle, 0);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
|
||||
AMDGPU_VA_OP_MAP);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
vcn_bo->addr = va;
|
||||
vcn_bo->handle = buf_handle;
|
||||
vcn_bo->size = req.alloc_size;
|
||||
vcn_bo->va_handle = va_handle;
|
||||
r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
memset(vcn_bo->ptr, 0, size);
|
||||
r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
}
|
||||
|
||||
static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
|
||||
vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_va_range_free(vcn_bo->va_handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
r = amdgpu_bo_free(vcn_bo->handle);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
memset(vcn_bo, 0, sizeof(*vcn_bo));
|
||||
}
|
||||
|
||||
static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
|
||||
{
|
||||
ib_cpu[(*idx)++] = 0x81C4;
|
||||
ib_cpu[(*idx)++] = addr;
|
||||
ib_cpu[(*idx)++] = 0x81C5;
|
||||
ib_cpu[(*idx)++] = addr >> 32;
|
||||
ib_cpu[(*idx)++] = 0x81C3;
|
||||
ib_cpu[(*idx)++] = cmd << 1;
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_dec_create(void)
|
||||
{
|
||||
struct amdgpu_vcn_bo msg_buf;
|
||||
int len, r;
|
||||
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = msg_buf.handle;
|
||||
resources[num_resources++] = ib_handle;
|
||||
|
||||
r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
memset(msg_buf.ptr, 0, 4096);
|
||||
memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
|
||||
|
||||
len = 0;
|
||||
ib_cpu[len++] = 0x81C4;
|
||||
ib_cpu[len++] = msg_buf.addr;
|
||||
ib_cpu[len++] = 0x81C5;
|
||||
ib_cpu[len++] = msg_buf.addr >> 32;
|
||||
ib_cpu[len++] = 0x81C3;
|
||||
ib_cpu[len++] = 0;
|
||||
for (; len % 16; ++len)
|
||||
ib_cpu[len] = 0x81ff;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
free_resource(&msg_buf);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_dec_decode(void)
|
||||
{
|
||||
const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
|
||||
uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
|
||||
struct amdgpu_vcn_bo dec_buf;
|
||||
int size, len, i, r;
|
||||
uint8_t *dec;
|
||||
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
size = 4*1024; /* msg */
|
||||
size += 4*1024; /* fb */
|
||||
size += 4096; /*it_scaling_table*/
|
||||
size += ALIGN(sizeof(uvd_bitstream), 4*1024);
|
||||
size += ALIGN(dpb_size, 4*1024);
|
||||
size += ALIGN(dt_size, 4*1024);
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = dec_buf.handle;
|
||||
resources[num_resources++] = ib_handle;
|
||||
|
||||
r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
|
||||
dec = dec_buf.ptr;
|
||||
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
memset(dec_buf.ptr, 0, size);
|
||||
memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
|
||||
memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
|
||||
avc_decode_msg, sizeof(avc_decode_msg));
|
||||
|
||||
dec += 4*1024;
|
||||
dec += 4*1024;
|
||||
memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
|
||||
|
||||
dec += 4*1024;
|
||||
memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
|
||||
|
||||
dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
|
||||
|
||||
dec += ALIGN(dpb_size, 4*1024);
|
||||
|
||||
msg_addr = dec_buf.addr;
|
||||
fb_addr = msg_addr + 4*1024;
|
||||
it_addr = fb_addr + 4*1024;
|
||||
bs_addr = it_addr + 4*1024;
|
||||
dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
|
||||
ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
|
||||
dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
|
||||
|
||||
len = 0;
|
||||
vcn_dec_cmd(msg_addr, 0x0, &len);
|
||||
vcn_dec_cmd(dpb_addr, 0x1, &len);
|
||||
vcn_dec_cmd(dt_addr, 0x2, &len);
|
||||
vcn_dec_cmd(fb_addr, 0x3, &len);
|
||||
vcn_dec_cmd(bs_addr, 0x100, &len);
|
||||
vcn_dec_cmd(it_addr, 0x204, &len);
|
||||
vcn_dec_cmd(ctx_addr, 0x206, &len);
|
||||
|
||||
ib_cpu[len++] = 0x81C6;
|
||||
ib_cpu[len++] = 0x1;
|
||||
for (; len % 16; ++len)
|
||||
ib_cpu[len] = 0x80000000;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
for (i = 0, sum = 0; i < dt_size; ++i)
|
||||
sum += dec[i];
|
||||
|
||||
CU_ASSERT_EQUAL(sum, SUM_DECODE);
|
||||
|
||||
free_resource(&dec_buf);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_dec_destroy(void)
|
||||
{
|
||||
struct amdgpu_vcn_bo msg_buf;
|
||||
int len, r;
|
||||
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
num_resources = 0;
|
||||
alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
|
||||
resources[num_resources++] = msg_buf.handle;
|
||||
resources[num_resources++] = ib_handle;
|
||||
|
||||
r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
memset(msg_buf.ptr, 0, 1024);
|
||||
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
|
||||
|
||||
len = 0;
|
||||
ib_cpu[len++] = 0x81C4;
|
||||
ib_cpu[len++] = msg_buf.addr;
|
||||
ib_cpu[len++] = 0x81C5;
|
||||
ib_cpu[len++] = msg_buf.addr >> 32;
|
||||
ib_cpu[len++] = 0x81C3;
|
||||
ib_cpu[len++] = 0;
|
||||
for (; len % 16; ++len)
|
||||
ib_cpu[len] = 0x80000000;
|
||||
|
||||
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
|
||||
CU_ASSERT_EQUAL(r, 0);
|
||||
|
||||
free_resource(&msg_buf);
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_enc_create(void)
|
||||
{
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_enc_encode(void)
|
||||
{
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static void amdgpu_cs_vcn_enc_destroy(void)
|
||||
{
|
||||
if (family_id < AMDGPU_FAMILY_RV)
|
||||
return;
|
||||
|
||||
/* TODO */
|
||||
}
|
||||
@ -174,6 +174,15 @@ static const char *mode_flag_names[] = {
|
||||
|
||||
static bit_name_fn(mode_flag)
|
||||
|
||||
static void dump_fourcc(uint32_t fourcc)
|
||||
{
|
||||
printf(" %c%c%c%c",
|
||||
fourcc,
|
||||
fourcc >> 8,
|
||||
fourcc >> 16,
|
||||
fourcc >> 24);
|
||||
}
|
||||
|
||||
static void dump_encoders(struct device *dev)
|
||||
{
|
||||
drmModeEncoder *encoder;
|
||||
@ -443,7 +452,7 @@ static void dump_planes(struct device *dev)
|
||||
|
||||
printf(" formats:");
|
||||
for (j = 0; j < ovr->count_formats; j++)
|
||||
printf(" %4.4s", (char *)&ovr->formats[j]);
|
||||
dump_fourcc(ovr->formats[j]);
|
||||
printf("\n");
|
||||
|
||||
if (plane->props) {
|
||||
|
||||
@ -79,6 +79,7 @@ static const struct type_name encoder_type_names[] = {
|
||||
{ DRM_MODE_ENCODER_VIRTUAL, "Virtual" },
|
||||
{ DRM_MODE_ENCODER_DSI, "DSI" },
|
||||
{ DRM_MODE_ENCODER_DPMST, "DPMST" },
|
||||
{ DRM_MODE_ENCODER_DPI, "DPI" },
|
||||
};
|
||||
|
||||
const char *util_lookup_encoder_type_name(unsigned int type)
|
||||
@ -117,6 +118,7 @@ static const struct type_name connector_type_names[] = {
|
||||
{ DRM_MODE_CONNECTOR_eDP, "eDP" },
|
||||
{ DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" },
|
||||
{ DRM_MODE_CONNECTOR_DSI, "DSI" },
|
||||
{ DRM_MODE_CONNECTOR_DPI, "DPI" },
|
||||
};
|
||||
|
||||
const char *util_lookup_connector_type_name(unsigned int type)
|
||||
@ -145,6 +147,7 @@ static const char * const modules[] = {
|
||||
"virtio_gpu",
|
||||
"mediatek",
|
||||
"meson",
|
||||
"pl111",
|
||||
};
|
||||
|
||||
int util_open(const char *device, const char *module)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user