366 lines
9.3 KiB
C
366 lines
9.3 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include <pthread.h>
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#include <sched.h>
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#include <sys/ioctl.h>
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#ifdef HAVE_ALLOCA_H
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# include <alloca.h>
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#endif
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#include "xf86drm.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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/**
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* Create command submission context
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*
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* \param dev - \c [in] amdgpu device handle
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* \param context - \c [out] amdgpu context handle
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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amdgpu_context_handle *context)
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{
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struct amdgpu_context *gpu_context;
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union drm_amdgpu_ctx args;
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int r;
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if (NULL == dev)
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return -EINVAL;
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if (NULL == context)
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return -EINVAL;
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gpu_context = calloc(1, sizeof(struct amdgpu_context));
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if (NULL == gpu_context)
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return -ENOMEM;
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gpu_context->dev = dev;
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/* Create the context */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
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if (r)
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goto error;
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gpu_context->id = args.out.alloc.ctx_id;
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*context = (amdgpu_context_handle)gpu_context;
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return 0;
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error:
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free(gpu_context);
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return r;
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}
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/**
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* Release command submission context
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*
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* \param dev - \c [in] amdgpu device handle
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* \param context - \c [in] amdgpu context handle
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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int amdgpu_cs_ctx_free(amdgpu_context_handle context)
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{
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union drm_amdgpu_ctx args;
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int r;
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if (NULL == context)
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return -EINVAL;
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/* now deal with kernel side */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_FREE_CTX;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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free(context);
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return r;
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}
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int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
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uint32_t *state, uint32_t *hangs)
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{
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union drm_amdgpu_ctx args;
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int r;
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if (!context)
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return -EINVAL;
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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if (!r) {
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*state = args.out.state.reset_status;
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*hangs = args.out.state.hangs;
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}
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return r;
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}
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/**
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* Submit command to kernel DRM
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* \param dev - \c [in] Device handle
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* \param context - \c [in] GPU Context
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* \param ibs_request - \c [in] Pointer to submission requests
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* \param fence - \c [out] return fence for this submission
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*
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* \return 0 on success otherwise POSIX Error code
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* \sa amdgpu_cs_submit()
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*/
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static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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struct amdgpu_cs_request *ibs_request)
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{
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union drm_amdgpu_cs cs;
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uint64_t *chunk_array;
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struct drm_amdgpu_cs_chunk *chunks;
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struct drm_amdgpu_cs_chunk_data *chunk_data;
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struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
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uint32_t i, size;
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bool user_fence;
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int r = 0;
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if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
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return -EINVAL;
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if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT)
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return -EINVAL;
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user_fence = (ibs_request->fence_info.handle != NULL);
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size = ibs_request->number_of_ibs + (user_fence ? 2 : 1);
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chunk_array = alloca(sizeof(uint64_t) * size);
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chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
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size = ibs_request->number_of_ibs + (user_fence ? 1 : 0);
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chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
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memset(&cs, 0, sizeof(cs));
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cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
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cs.in.ctx_id = context->id;
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if (ibs_request->resources)
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cs.in.bo_list_handle = ibs_request->resources->handle;
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cs.in.num_chunks = ibs_request->number_of_ibs;
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/* IB chunks */
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for (i = 0; i < ibs_request->number_of_ibs; i++) {
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struct amdgpu_cs_ib_info *ib;
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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ib = &ibs_request->ibs[i];
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chunk_data[i].ib_data._pad = 0;
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chunk_data[i].ib_data.va_start = ib->ib_mc_address;
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chunk_data[i].ib_data.ib_bytes = ib->size * 4;
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chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
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chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
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chunk_data[i].ib_data.ring = ibs_request->ring;
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chunk_data[i].ib_data.flags = ib->flags;
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}
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if (user_fence) {
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i = cs.in.num_chunks++;
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/* fence chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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/* fence bo handle */
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chunk_data[i].fence_data.handle = ibs_request->fence_info.handle->handle;
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/* offset */
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chunk_data[i].fence_data.offset =
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ibs_request->fence_info.offset * sizeof(uint64_t);
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}
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if (ibs_request->number_of_dependencies) {
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dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) *
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ibs_request->number_of_dependencies);
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if (!dependencies) {
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r = -ENOMEM;
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goto error_unlock;
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}
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for (i = 0; i < ibs_request->number_of_dependencies; ++i) {
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struct amdgpu_cs_fence *info = &ibs_request->dependencies[i];
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struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i];
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dep->ip_type = info->ip_type;
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dep->ip_instance = info->ip_instance;
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dep->ring = info->ring;
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dep->ctx_id = info->context->id;
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dep->handle = info->fence;
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}
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i = cs.in.num_chunks++;
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/* dependencies chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
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* ibs_request->number_of_dependencies;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies;
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}
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
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&cs, sizeof(cs));
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if (r)
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goto error_unlock;
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ibs_request->seq_no = cs.out.handle;
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error_unlock:
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free(dependencies);
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return r;
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}
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int amdgpu_cs_submit(amdgpu_context_handle context,
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uint64_t flags,
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struct amdgpu_cs_request *ibs_request,
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uint32_t number_of_requests)
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{
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uint32_t i;
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int r;
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if (NULL == context)
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return -EINVAL;
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if (NULL == ibs_request)
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return -EINVAL;
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r = 0;
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for (i = 0; i < number_of_requests; i++) {
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r = amdgpu_cs_submit_one(context, ibs_request);
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if (r)
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break;
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ibs_request++;
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}
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return r;
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}
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/**
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* Calculate absolute timeout.
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*
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* \param timeout - \c [in] timeout in nanoseconds.
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*
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* \return absolute timeout in nanoseconds
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*/
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drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
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{
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int r;
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if (timeout != AMDGPU_TIMEOUT_INFINITE) {
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struct timespec current;
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r = clock_gettime(CLOCK_MONOTONIC, ¤t);
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if (r)
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return r;
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timeout += ((uint64_t)current.tv_sec) * 1000000000ull;
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timeout += current.tv_nsec;
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}
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return timeout;
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}
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static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
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unsigned ip,
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unsigned ip_instance,
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uint32_t ring,
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uint64_t handle,
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uint64_t timeout_ns,
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uint64_t flags,
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bool *busy)
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{
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amdgpu_device_handle dev = context->dev;
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union drm_amdgpu_wait_cs args;
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int r;
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memset(&args, 0, sizeof(args));
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args.in.handle = handle;
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args.in.ip_type = ip;
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args.in.ip_instance = ip_instance;
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args.in.ring = ring;
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args.in.ctx_id = context->id;
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if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE)
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args.in.timeout = timeout_ns;
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else
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args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
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r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
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if (r)
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return -errno;
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*busy = args.out.status;
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return 0;
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}
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int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
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uint64_t timeout_ns,
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uint64_t flags,
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uint32_t *expired)
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{
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bool busy = true;
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int r;
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if (NULL == fence)
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return -EINVAL;
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if (NULL == expired)
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return -EINVAL;
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if (NULL == fence->context)
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return -EINVAL;
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if (fence->ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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if (fence->ring >= AMDGPU_CS_MAX_RINGS)
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return -EINVAL;
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*expired = false;
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r = amdgpu_ioctl_wait_cs(fence->context, fence->ip_type,
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fence->ip_instance, fence->ring,
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fence->fence, timeout_ns, flags, &busy);
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if (!r && !busy)
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*expired = true;
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return r;
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}
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