411 lines
10 KiB
C
411 lines
10 KiB
C
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdio.h>
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#include <inttypes.h>
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#include "CUnit/Basic.h"
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#include "util_math.h"
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#include "amdgpu_test.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#include "decode_messages.h"
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#define IB_SIZE 4096
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#define MAX_RESOURCES 16
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struct amdgpu_vcn_bo {
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amdgpu_bo_handle handle;
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amdgpu_va_handle va_handle;
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uint64_t addr;
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uint64_t size;
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uint8_t *ptr;
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};
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static amdgpu_device_handle device_handle;
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static uint32_t major_version;
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static uint32_t minor_version;
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static uint32_t family_id;
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static amdgpu_context_handle context_handle;
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static amdgpu_bo_handle ib_handle;
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static amdgpu_va_handle ib_va_handle;
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static uint64_t ib_mc_address;
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static uint32_t *ib_cpu;
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static amdgpu_bo_handle resources[MAX_RESOURCES];
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static unsigned num_resources;
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static void amdgpu_cs_vcn_dec_create(void);
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static void amdgpu_cs_vcn_dec_decode(void);
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static void amdgpu_cs_vcn_dec_destroy(void);
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static void amdgpu_cs_vcn_enc_create(void);
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static void amdgpu_cs_vcn_enc_encode(void);
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static void amdgpu_cs_vcn_enc_destroy(void);
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CU_TestInfo vcn_tests[] = {
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{ "VCN DEC create", amdgpu_cs_vcn_dec_create },
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{ "VCN DEC decode", amdgpu_cs_vcn_dec_decode },
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{ "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy },
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{ "VCN ENC create", amdgpu_cs_vcn_enc_create },
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{ "VCN ENC decode", amdgpu_cs_vcn_enc_encode },
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{ "VCN ENC destroy", amdgpu_cs_vcn_enc_destroy },
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CU_TEST_INFO_NULL,
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};
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int suite_vcn_tests_init(void)
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{
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int r;
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r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
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&minor_version, &device_handle);
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if (r)
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return CUE_SINIT_FAILED;
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family_id = device_handle->info.family_id;
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if (family_id < AMDGPU_FAMILY_RV) {
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printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
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return CUE_SUCCESS;
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}
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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if (r)
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return CUE_SINIT_FAILED;
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r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_handle, (void**)&ib_cpu,
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&ib_mc_address, &ib_va_handle);
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if (r)
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return CUE_SINIT_FAILED;
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return CUE_SUCCESS;
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}
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int suite_vcn_tests_clean(void)
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{
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int r;
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if (family_id < AMDGPU_FAMILY_RV) {
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r = amdgpu_device_deinitialize(device_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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} else {
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r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
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ib_mc_address, IB_SIZE);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_cs_ctx_free(context_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_device_deinitialize(device_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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}
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return CUE_SUCCESS;
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}
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static int submit(unsigned ndw, unsigned ip)
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{
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info = {0};
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struct amdgpu_cs_fence fence_status = {0};
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uint32_t expired;
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int r;
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ib_info.ib_mc_address = ib_mc_address;
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ib_info.size = ndw;
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ibs_request.ip_type = ip;
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r = amdgpu_bo_list_create(device_handle, num_resources, resources,
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NULL, &ibs_request.resources);
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if (r)
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return r;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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if (r)
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return r;
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r = amdgpu_bo_list_destroy(ibs_request.resources);
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if (r)
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return r;
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fence_status.context = context_handle;
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fence_status.ip_type = ip;
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fence_status.fence = ibs_request.seq_no;
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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if (r)
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return r;
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return 0;
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}
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static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
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unsigned size, unsigned domain)
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{
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struct amdgpu_bo_alloc_request req = {0};
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle va_handle;
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uint64_t va = 0;
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int r;
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req.alloc_size = ALIGN(size, 4096);
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req.preferred_heap = domain;
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r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_alloc(device_handle,
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amdgpu_gpu_va_range_general,
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req.alloc_size, 1, 0, &va,
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&va_handle, 0);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
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AMDGPU_VA_OP_MAP);
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CU_ASSERT_EQUAL(r, 0);
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vcn_bo->addr = va;
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vcn_bo->handle = buf_handle;
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vcn_bo->size = req.alloc_size;
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vcn_bo->va_handle = va_handle;
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r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
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CU_ASSERT_EQUAL(r, 0);
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memset(vcn_bo->ptr, 0, size);
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r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
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{
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int r;
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r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
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vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_free(vcn_bo->va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_free(vcn_bo->handle);
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CU_ASSERT_EQUAL(r, 0);
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memset(vcn_bo, 0, sizeof(*vcn_bo));
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}
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static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
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{
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ib_cpu[(*idx)++] = 0x81C4;
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ib_cpu[(*idx)++] = addr;
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ib_cpu[(*idx)++] = 0x81C5;
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ib_cpu[(*idx)++] = addr >> 32;
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ib_cpu[(*idx)++] = 0x81C3;
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ib_cpu[(*idx)++] = cmd << 1;
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}
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static void amdgpu_cs_vcn_dec_create(void)
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{
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struct amdgpu_vcn_bo msg_buf;
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int len, r;
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if (family_id < AMDGPU_FAMILY_RV)
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return;
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num_resources = 0;
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alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
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resources[num_resources++] = msg_buf.handle;
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resources[num_resources++] = ib_handle;
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r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
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CU_ASSERT_EQUAL(r, 0);
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memset(msg_buf.ptr, 0, 4096);
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memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
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len = 0;
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ib_cpu[len++] = 0x81C4;
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ib_cpu[len++] = msg_buf.addr;
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ib_cpu[len++] = 0x81C5;
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ib_cpu[len++] = msg_buf.addr >> 32;
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ib_cpu[len++] = 0x81C3;
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ib_cpu[len++] = 0;
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for (; len % 16; ++len)
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ib_cpu[len] = 0x81ff;
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r = submit(len, AMDGPU_HW_IP_VCN_DEC);
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CU_ASSERT_EQUAL(r, 0);
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free_resource(&msg_buf);
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}
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static void amdgpu_cs_vcn_dec_decode(void)
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{
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const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
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uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
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struct amdgpu_vcn_bo dec_buf;
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int size, len, i, r;
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uint8_t *dec;
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if (family_id < AMDGPU_FAMILY_RV)
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return;
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size = 4*1024; /* msg */
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size += 4*1024; /* fb */
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size += 4096; /*it_scaling_table*/
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size += ALIGN(sizeof(uvd_bitstream), 4*1024);
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size += ALIGN(dpb_size, 4*1024);
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size += ALIGN(dt_size, 4*1024);
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num_resources = 0;
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alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
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resources[num_resources++] = dec_buf.handle;
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resources[num_resources++] = ib_handle;
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r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
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dec = dec_buf.ptr;
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CU_ASSERT_EQUAL(r, 0);
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memset(dec_buf.ptr, 0, size);
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memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
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memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
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avc_decode_msg, sizeof(avc_decode_msg));
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dec += 4*1024;
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dec += 4*1024;
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memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
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dec += 4*1024;
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memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
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dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
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dec += ALIGN(dpb_size, 4*1024);
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msg_addr = dec_buf.addr;
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fb_addr = msg_addr + 4*1024;
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it_addr = fb_addr + 4*1024;
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bs_addr = it_addr + 4*1024;
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dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
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ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
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dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
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len = 0;
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vcn_dec_cmd(msg_addr, 0x0, &len);
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vcn_dec_cmd(dpb_addr, 0x1, &len);
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vcn_dec_cmd(dt_addr, 0x2, &len);
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vcn_dec_cmd(fb_addr, 0x3, &len);
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vcn_dec_cmd(bs_addr, 0x100, &len);
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vcn_dec_cmd(it_addr, 0x204, &len);
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vcn_dec_cmd(ctx_addr, 0x206, &len);
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ib_cpu[len++] = 0x81C6;
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ib_cpu[len++] = 0x1;
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for (; len % 16; ++len)
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ib_cpu[len] = 0x80000000;
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r = submit(len, AMDGPU_HW_IP_VCN_DEC);
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CU_ASSERT_EQUAL(r, 0);
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for (i = 0, sum = 0; i < dt_size; ++i)
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sum += dec[i];
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CU_ASSERT_EQUAL(sum, SUM_DECODE);
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free_resource(&dec_buf);
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}
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static void amdgpu_cs_vcn_dec_destroy(void)
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{
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struct amdgpu_vcn_bo msg_buf;
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int len, r;
|
||
|
|
|
||
|
|
if (family_id < AMDGPU_FAMILY_RV)
|
||
|
|
return;
|
||
|
|
|
||
|
|
num_resources = 0;
|
||
|
|
alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
|
||
|
|
resources[num_resources++] = msg_buf.handle;
|
||
|
|
resources[num_resources++] = ib_handle;
|
||
|
|
|
||
|
|
r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
|
||
|
|
CU_ASSERT_EQUAL(r, 0);
|
||
|
|
|
||
|
|
memset(msg_buf.ptr, 0, 1024);
|
||
|
|
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
|
||
|
|
|
||
|
|
len = 0;
|
||
|
|
ib_cpu[len++] = 0x81C4;
|
||
|
|
ib_cpu[len++] = msg_buf.addr;
|
||
|
|
ib_cpu[len++] = 0x81C5;
|
||
|
|
ib_cpu[len++] = msg_buf.addr >> 32;
|
||
|
|
ib_cpu[len++] = 0x81C3;
|
||
|
|
ib_cpu[len++] = 0;
|
||
|
|
for (; len % 16; ++len)
|
||
|
|
ib_cpu[len] = 0x80000000;
|
||
|
|
|
||
|
|
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
|
||
|
|
CU_ASSERT_EQUAL(r, 0);
|
||
|
|
|
||
|
|
free_resource(&msg_buf);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void amdgpu_cs_vcn_enc_create(void)
|
||
|
|
{
|
||
|
|
if (family_id < AMDGPU_FAMILY_RV)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* TODO */
|
||
|
|
}
|
||
|
|
|
||
|
|
static void amdgpu_cs_vcn_enc_encode(void)
|
||
|
|
{
|
||
|
|
if (family_id < AMDGPU_FAMILY_RV)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* TODO */
|
||
|
|
}
|
||
|
|
|
||
|
|
static void amdgpu_cs_vcn_enc_destroy(void)
|
||
|
|
{
|
||
|
|
if (family_id < AMDGPU_FAMILY_RV)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* TODO */
|
||
|
|
}
|