mirror of
https://github.com/golang/go
synced 2024-11-19 16:24:45 -07:00
7b9873b9b9
Updates #15365. Change-Id: I372a5617c2c7d91de545cac0464809b96711b63a Reviewed-on: https://go-review.googlesource.com/24646 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
656 lines
16 KiB
Go
656 lines
16 KiB
Go
// Copyright 2009 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Software floating point interpretation of ARM 7500 FP instructions.
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// The interpretation is not bit compatible with the 7500.
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// It uses true little-endian doubles, while the 7500 used mixed-endian.
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package runtime
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import "unsafe"
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const (
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_CPSR = 14
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_FLAGS_N = 1 << 31
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_FLAGS_Z = 1 << 30
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_FLAGS_C = 1 << 29
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_FLAGS_V = 1 << 28
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)
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var fptrace = 0
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func fabort() {
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throw("unsupported floating point instruction")
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}
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func fputf(reg uint32, val uint32) {
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_g_ := getg()
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_g_.m.freglo[reg] = val
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}
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func fputd(reg uint32, val uint64) {
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_g_ := getg()
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_g_.m.freglo[reg] = uint32(val)
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_g_.m.freghi[reg] = uint32(val >> 32)
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}
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func fgetd(reg uint32) uint64 {
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_g_ := getg()
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return uint64(_g_.m.freglo[reg]) | uint64(_g_.m.freghi[reg])<<32
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}
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func fprintregs() {
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_g_ := getg()
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for i := range _g_.m.freglo {
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print("\tf", i, ":\t", hex(_g_.m.freghi[i]), " ", hex(_g_.m.freglo[i]), "\n")
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}
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}
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func fstatus(nan bool, cmp int32) uint32 {
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if nan {
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return _FLAGS_C | _FLAGS_V
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}
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if cmp == 0 {
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return _FLAGS_Z | _FLAGS_C
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}
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if cmp < 0 {
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return _FLAGS_N
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}
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return _FLAGS_C
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}
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// conditions array record the required CPSR cond field for the
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// first 5 pairs of conditional execution opcodes
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// higher 4 bits are must set, lower 4 bits are must clear
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var conditions = [10 / 2]uint32{
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0 / 2: _FLAGS_Z>>24 | 0, // 0: EQ (Z set), 1: NE (Z clear)
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2 / 2: _FLAGS_C>>24 | 0, // 2: CS/HS (C set), 3: CC/LO (C clear)
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4 / 2: _FLAGS_N>>24 | 0, // 4: MI (N set), 5: PL (N clear)
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6 / 2: _FLAGS_V>>24 | 0, // 6: VS (V set), 7: VC (V clear)
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8 / 2: _FLAGS_C>>24 |
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_FLAGS_Z>>28,
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}
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const _FAULT = 0x80000000 // impossible PC offset
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// returns number of words that the fp instruction
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// is occupying, 0 if next instruction isn't float.
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func stepflt(pc *uint32, regs *[15]uint32) uint32 {
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var i, opc, regd, regm, regn, cpsr uint32
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// m is locked in vlop_arm.s, so g.m cannot change during this function call,
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// so caching it in a local variable is safe.
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m := getg().m
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i = *pc
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if fptrace > 0 {
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print("stepflt ", pc, " ", hex(i), " (cpsr ", hex(regs[_CPSR]>>28), ")\n")
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}
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opc = i >> 28
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if opc == 14 { // common case first
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goto execute
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}
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cpsr = regs[_CPSR] >> 28
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switch opc {
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case 0, 1, 2, 3, 4, 5, 6, 7, 8, 9:
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if cpsr&(conditions[opc/2]>>4) == conditions[opc/2]>>4 &&
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cpsr&(conditions[opc/2]&0xf) == 0 {
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if opc&1 != 0 {
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return 1
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}
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} else {
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if opc&1 == 0 {
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return 1
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}
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}
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case 10, 11: // GE (N == V), LT (N != V)
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if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) {
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if opc&1 != 0 {
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return 1
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}
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} else {
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if opc&1 == 0 {
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return 1
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}
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}
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case 12, 13: // GT (N == V and Z == 0), LE (N != V or Z == 1)
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if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) &&
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cpsr&(_FLAGS_Z>>28) == 0 {
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if opc&1 != 0 {
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return 1
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}
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} else {
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if opc&1 == 0 {
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return 1
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}
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}
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case 14: // AL
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// ok
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case 15: // shouldn't happen
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return 0
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}
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if fptrace > 0 {
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print("conditional ", hex(opc), " (cpsr ", hex(cpsr), ") pass\n")
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}
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i = 0xe<<28 | i&(1<<28-1)
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execute:
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// special cases
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if i&0xfffff000 == 0xe59fb000 {
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// load r11 from pc-relative address.
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// might be part of a floating point move
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// (or might not, but no harm in simulating
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// one instruction too many).
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addr := (*[1]uint32)(add(unsafe.Pointer(pc), uintptr(i&0xfff+8)))
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regs[11] = addr[0]
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if fptrace > 0 {
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print("*** cpu R[11] = *(", addr, ") ", hex(regs[11]), "\n")
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}
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return 1
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}
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if i == 0xe08fb00b {
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// add pc to r11
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// might be part of a PIC floating point move
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// (or might not, but again no harm done).
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regs[11] += uint32(uintptr(unsafe.Pointer(pc))) + 8
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if fptrace > 0 {
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print("*** cpu R[11] += pc ", hex(regs[11]), "\n")
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}
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return 1
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}
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if i&0xfffffff0 == 0xe08bb000 {
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r := i & 0xf
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// add r to r11.
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// might be part of a large offset address calculation
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// (or might not, but again no harm done).
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regs[11] += regs[r]
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if fptrace > 0 {
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print("*** cpu R[11] += R[", r, "] ", hex(regs[11]), "\n")
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}
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return 1
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}
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if i == 0xeef1fa10 {
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regs[_CPSR] = regs[_CPSR]&0x0fffffff | m.fflag
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if fptrace > 0 {
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print("*** fpsr R[CPSR] = F[CPSR] ", hex(regs[_CPSR]), "\n")
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}
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return 1
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}
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if i&0xff000000 == 0xea000000 {
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// unconditional branch
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// can happen in the middle of floating point
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// if the linker decides it is time to lay down
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// a sequence of instruction stream constants.
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delta := int32(i&0xffffff) << 8 >> 8 // sign extend
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if fptrace > 0 {
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print("*** cpu PC += ", hex((delta+2)*4), "\n")
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}
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return uint32(delta + 2)
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}
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// load/store regn is cpureg, regm is 8bit offset
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regd = i >> 12 & 0xf
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regn = i >> 16 & 0xf
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regm = i & 0xff << 2 // PLUS or MINUS ??
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switch i & 0xfff00f00 {
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case 0xed900a00: // single load
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uaddr := uintptr(regs[regn] + regm)
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if uaddr < 4096 {
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if fptrace > 0 {
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print("*** load @", hex(uaddr), " => fault\n")
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}
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return _FAULT
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}
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addr := (*[1]uint32)(unsafe.Pointer(uaddr))
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m.freglo[regd] = addr[0]
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if fptrace > 0 {
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print("*** load F[", regd, "] = ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xed900b00: // double load
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uaddr := uintptr(regs[regn] + regm)
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if uaddr < 4096 {
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if fptrace > 0 {
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print("*** double load @", hex(uaddr), " => fault\n")
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}
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return _FAULT
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}
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addr := (*[2]uint32)(unsafe.Pointer(uaddr))
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m.freglo[regd] = addr[0]
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m.freghi[regd] = addr[1]
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if fptrace > 0 {
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print("*** load D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xed800a00: // single store
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uaddr := uintptr(regs[regn] + regm)
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if uaddr < 4096 {
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if fptrace > 0 {
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print("*** store @", hex(uaddr), " => fault\n")
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}
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return _FAULT
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}
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addr := (*[1]uint32)(unsafe.Pointer(uaddr))
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addr[0] = m.freglo[regd]
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if fptrace > 0 {
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print("*** *(", addr, ") = ", hex(addr[0]), "\n")
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}
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return 1
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case 0xed800b00: // double store
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uaddr := uintptr(regs[regn] + regm)
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if uaddr < 4096 {
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if fptrace > 0 {
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print("*** double store @", hex(uaddr), " => fault\n")
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}
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return _FAULT
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}
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addr := (*[2]uint32)(unsafe.Pointer(uaddr))
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addr[0] = m.freglo[regd]
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addr[1] = m.freghi[regd]
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if fptrace > 0 {
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print("*** *(", addr, ") = ", hex(addr[1]), "-", hex(addr[0]), "\n")
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}
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return 1
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}
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// regd, regm, regn are 4bit variables
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regm = i >> 0 & 0xf
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switch i & 0xfff00ff0 {
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case 0xf3000110: // veor
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m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn]
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m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn]
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if fptrace > 0 {
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print("*** veor D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb00b00: // D[regd] = const(regn,regm)
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regn = regn<<4 | regm
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regm = 0x40000000
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if regn&0x80 != 0 {
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regm |= 0x80000000
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}
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if regn&0x40 != 0 {
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regm ^= 0x7fc00000
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}
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regm |= regn & 0x3f << 16
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m.freglo[regd] = 0
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m.freghi[regd] = regm
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if fptrace > 0 {
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print("*** immed D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb00a00: // F[regd] = const(regn,regm)
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regn = regn<<4 | regm
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regm = 0x40000000
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if regn&0x80 != 0 {
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regm |= 0x80000000
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}
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if regn&0x40 != 0 {
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regm ^= 0x7e000000
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}
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regm |= regn & 0x3f << 19
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m.freglo[regd] = regm
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if fptrace > 0 {
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print("*** immed D[", regd, "] = ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee300b00: // D[regd] = D[regn]+D[regm]
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fputd(regd, fadd64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee300a00: // F[regd] = F[regn]+F[regm]
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m.freglo[regd] = f64to32(fadd64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee300b40: // D[regd] = D[regn]-D[regm]
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fputd(regd, fsub64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee300a40: // F[regd] = F[regn]-F[regm]
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m.freglo[regd] = f64to32(fsub64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee200b00: // D[regd] = D[regn]*D[regm]
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fputd(regd, fmul64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee200a00: // F[regd] = F[regn]*F[regm]
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m.freglo[regd] = f64to32(fmul64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee800b00: // D[regd] = D[regn]/D[regm]
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fputd(regd, fdiv64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee800a00: // F[regd] = F[regn]/F[regm]
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m.freglo[regd] = f64to32(fdiv64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
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m.freglo[regn] = regs[regd]
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if fptrace > 0 {
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print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n")
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}
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return 1
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case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
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regs[regd] = m.freglo[regn]
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if fptrace > 0 {
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print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n")
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}
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return 1
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}
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// regd, regm are 4bit variables
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switch i & 0xffff0ff0 {
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case 0xeeb00a40: // F[regd] = F[regm] (MOVF)
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m.freglo[regd] = m.freglo[regm]
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if fptrace > 0 {
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print("*** F[", regd, "] = F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb00b40: // D[regd] = D[regm] (MOVD)
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m.freglo[regd] = m.freglo[regm]
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m.freghi[regd] = m.freghi[regm]
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if fptrace > 0 {
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print("*** D[", regd, "] = D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb10bc0: // D[regd] = sqrt D[regm]
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fputd(regd, sqrt(fgetd(regm)))
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if fptrace > 0 {
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print("*** D[", regd, "] = sqrt D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb00bc0: // D[regd] = abs D[regm]
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m.freglo[regd] = m.freglo[regm]
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m.freghi[regd] = m.freghi[regm] & (1<<31 - 1)
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if fptrace > 0 {
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print("*** D[", regd, "] = abs D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb00ac0: // F[regd] = abs F[regm]
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m.freglo[regd] = m.freglo[regm] & (1<<31 - 1)
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if fptrace > 0 {
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print("*** F[", regd, "] = abs F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb10b40: // D[regd] = neg D[regm]
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m.freglo[regd] = m.freglo[regm]
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m.freghi[regd] = m.freghi[regm] ^ 1<<31
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if fptrace > 0 {
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print("*** D[", regd, "] = neg D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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return 1
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case 0xeeb10a40: // F[regd] = neg F[regm]
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m.freglo[regd] = m.freglo[regm] ^ 1<<31
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|
|
if fptrace > 0 {
|
|
print("*** F[", regd, "] = neg F[", regm, "] ", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD)
|
|
cmp, nan := fcmp64(fgetd(regd), fgetd(regm))
|
|
m.fflag = fstatus(nan, cmp)
|
|
|
|
if fptrace > 0 {
|
|
print("*** cmp D[", regd, "]::D[", regm, "] ", hex(m.fflag), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF)
|
|
cmp, nan := fcmp64(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]))
|
|
m.fflag = fstatus(nan, cmp)
|
|
|
|
if fptrace > 0 {
|
|
print("*** cmp F[", regd, "]::F[", regm, "] ", hex(m.fflag), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb50bc0: // D[regd] :: 0 (CMPD)
|
|
cmp, nan := fcmp64(fgetd(regd), 0)
|
|
m.fflag = fstatus(nan, cmp)
|
|
|
|
if fptrace > 0 {
|
|
print("*** cmp D[", regd, "]::0 ", hex(m.fflag), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb50ac0: // F[regd] :: 0 (CMPF)
|
|
cmp, nan := fcmp64(f32to64(m.freglo[regd]), 0)
|
|
m.fflag = fstatus(nan, cmp)
|
|
|
|
if fptrace > 0 {
|
|
print("*** cmp F[", regd, "]::0 ", hex(m.fflag), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD)
|
|
fputd(regd, f32to64(m.freglo[regm]))
|
|
|
|
if fptrace > 0 {
|
|
print("*** f2d D[", regd, "]=F[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF)
|
|
m.freglo[regd] = f64to32(fgetd(regm))
|
|
|
|
if fptrace > 0 {
|
|
print("*** d2f F[", regd, "]=D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW)
|
|
sval, ok := f64toint(f32to64(m.freglo[regm]))
|
|
if !ok || int64(int32(sval)) != sval {
|
|
sval = 0
|
|
}
|
|
m.freglo[regd] = uint32(sval)
|
|
if fptrace > 0 {
|
|
print("*** fix S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U)
|
|
sval, ok := f64toint(f32to64(m.freglo[regm]))
|
|
if !ok || int64(uint32(sval)) != sval {
|
|
sval = 0
|
|
}
|
|
m.freglo[regd] = uint32(sval)
|
|
|
|
if fptrace > 0 {
|
|
print("*** fix unsigned S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW)
|
|
sval, ok := f64toint(fgetd(regm))
|
|
if !ok || int64(int32(sval)) != sval {
|
|
sval = 0
|
|
}
|
|
m.freglo[regd] = uint32(sval)
|
|
|
|
if fptrace > 0 {
|
|
print("*** fix S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U)
|
|
sval, ok := f64toint(fgetd(regm))
|
|
if !ok || int64(uint32(sval)) != sval {
|
|
sval = 0
|
|
}
|
|
m.freglo[regd] = uint32(sval)
|
|
|
|
if fptrace > 0 {
|
|
print("*** fix unsigned S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF)
|
|
cmp := int32(m.freglo[regm])
|
|
if cmp < 0 {
|
|
fputf(regd, f64to32(fintto64(-int64(cmp))))
|
|
m.freglo[regd] ^= 0x80000000
|
|
} else {
|
|
fputf(regd, f64to32(fintto64(int64(cmp))))
|
|
}
|
|
|
|
if fptrace > 0 {
|
|
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U)
|
|
fputf(regd, f64to32(fintto64(int64(m.freglo[regm]))))
|
|
|
|
if fptrace > 0 {
|
|
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD)
|
|
cmp := int32(m.freglo[regm])
|
|
if cmp < 0 {
|
|
fputd(regd, fintto64(-int64(cmp)))
|
|
m.freghi[regd] ^= 0x80000000
|
|
} else {
|
|
fputd(regd, fintto64(int64(cmp)))
|
|
}
|
|
|
|
if fptrace > 0 {
|
|
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
|
|
case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U)
|
|
fputd(regd, fintto64(int64(m.freglo[regm])))
|
|
|
|
if fptrace > 0 {
|
|
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
|
}
|
|
return 1
|
|
}
|
|
|
|
if i&0xff000000 == 0xee000000 || i&0xff000000 == 0xed000000 {
|
|
print("stepflt ", pc, " ", hex(i), "\n")
|
|
fabort()
|
|
}
|
|
return 0
|
|
}
|
|
|
|
//go:nosplit
|
|
func _sfloat2(pc uint32, regs [15]uint32) (newpc uint32) {
|
|
systemstack(func() {
|
|
newpc = sfloat2(pc, ®s)
|
|
})
|
|
return
|
|
}
|
|
|
|
func _sfloatpanic()
|
|
|
|
func sfloat2(pc uint32, regs *[15]uint32) uint32 {
|
|
first := true
|
|
for {
|
|
skip := stepflt((*uint32)(unsafe.Pointer(uintptr(pc))), regs)
|
|
if skip == 0 {
|
|
break
|
|
}
|
|
first = false
|
|
if skip == _FAULT {
|
|
// Encountered bad address in store/load.
|
|
// Record signal information and return to assembly
|
|
// trampoline that fakes the call.
|
|
const SIGSEGV = 11
|
|
curg := getg().m.curg
|
|
curg.sig = SIGSEGV
|
|
curg.sigcode0 = 0
|
|
curg.sigcode1 = 0
|
|
curg.sigpc = uintptr(pc)
|
|
pc = uint32(funcPC(_sfloatpanic))
|
|
break
|
|
}
|
|
pc += 4 * skip
|
|
}
|
|
if first {
|
|
print("sfloat2 ", pc, " ", hex(*(*uint32)(unsafe.Pointer(uintptr(pc)))), "\n")
|
|
fabort() // not ok to fail first instruction
|
|
}
|
|
return pc
|
|
}
|