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cmd/asm: restore supporting of *1 scaling on ARM64
On ARM64, instruction like "MOVD (R1)(R2*1), R3" is accepted and assembles correctly with Go 1.16, but errors out on tip with "arm64 doesn't support scaled register format", since CL 289589. "MOVD (R1)(R2), R3" is the preferred form. But the *1 form works before and assembles correctly. Keep supporting it. Fixes #46766. Change-Id: I0f7fd71fa87ea698919a936b6c68aa5a91afd486 Reviewed-on: https://go-review.googlesource.com/c/go/+/328229 Trust: Cherry Mui <cherryyz@google.com> Trust: Cuong Manh Le <cuong.manhle.vn@gmail.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: eric fang <eric.fang@arm.com>
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@ -1003,7 +1003,8 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
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p.errorf("unimplemented two-register form")
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}
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a.Index = r1
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if scale != 0 && p.arch.Family == sys.ARM64 {
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if scale != 0 && scale != 1 && p.arch.Family == sys.ARM64 {
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// Support (R1)(R2) (no scaling) and (R1)(R2*1).
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p.errorf("arm64 doesn't support scaled register format")
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} else {
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a.Scale = int16(scale)
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2
src/cmd/asm/internal/asm/testdata/arm64.s
vendored
2
src/cmd/asm/internal/asm/testdata/arm64.s
vendored
@ -547,6 +547,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
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// shifted or extended register offset.
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MOVD (R2)(R6.SXTW), R4 // 44c866f8
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MOVD (R3)(R6), R5 // 656866f8
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MOVD (R3)(R6*1), R5 // 656866f8
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MOVD (R2)(R6), R4 // 446866f8
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MOVWU (R19)(R20<<2), R20 // 747a74b8
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MOVD (R2)(R6<<3), R4 // 447866f8
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@ -579,6 +580,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
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MOVB R4, (R2)(R6.SXTX) // 44e82638
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MOVB R8, (R3)(R9.UXTW) // 68482938
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MOVB R10, (R5)(R8) // aa682838
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MOVB R10, (R5)(R8*1) // aa682838
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MOVH R11, (R2)(R7.SXTW<<1) // 4bd82778
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MOVH R5, (R1)(R2<<1) // 25782278
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MOVH R7, (R2)(R5.SXTX<<1) // 47f82578
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