From a6a853f94cf00d8f581d0e6fbcc28898e39557b2 Mon Sep 17 00:00:00 2001 From: Cherry Mui Date: Tue, 15 Jun 2021 12:47:57 -0400 Subject: [PATCH] cmd/asm: restore supporting of *1 scaling on ARM64 On ARM64, instruction like "MOVD (R1)(R2*1), R3" is accepted and assembles correctly with Go 1.16, but errors out on tip with "arm64 doesn't support scaled register format", since CL 289589. "MOVD (R1)(R2), R3" is the preferred form. But the *1 form works before and assembles correctly. Keep supporting it. Fixes #46766. Change-Id: I0f7fd71fa87ea698919a936b6c68aa5a91afd486 Reviewed-on: https://go-review.googlesource.com/c/go/+/328229 Trust: Cherry Mui Trust: Cuong Manh Le Run-TryBot: Cherry Mui TryBot-Result: Go Bot Reviewed-by: eric fang --- src/cmd/asm/internal/asm/parse.go | 3 ++- src/cmd/asm/internal/asm/testdata/arm64.s | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go index ab48632a44..4cddcf48a4 100644 --- a/src/cmd/asm/internal/asm/parse.go +++ b/src/cmd/asm/internal/asm/parse.go @@ -1003,7 +1003,8 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) { p.errorf("unimplemented two-register form") } a.Index = r1 - if scale != 0 && p.arch.Family == sys.ARM64 { + if scale != 0 && scale != 1 && p.arch.Family == sys.ARM64 { + // Support (R1)(R2) (no scaling) and (R1)(R2*1). p.errorf("arm64 doesn't support scaled register format") } else { a.Scale = int16(scale) diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 1146c1a789..5f1e68545b 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -547,6 +547,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 // shifted or extended register offset. MOVD (R2)(R6.SXTW), R4 // 44c866f8 MOVD (R3)(R6), R5 // 656866f8 + MOVD (R3)(R6*1), R5 // 656866f8 MOVD (R2)(R6), R4 // 446866f8 MOVWU (R19)(R20<<2), R20 // 747a74b8 MOVD (R2)(R6<<3), R4 // 447866f8 @@ -579,6 +580,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVB R4, (R2)(R6.SXTX) // 44e82638 MOVB R8, (R3)(R9.UXTW) // 68482938 MOVB R10, (R5)(R8) // aa682838 + MOVB R10, (R5)(R8*1) // aa682838 MOVH R11, (R2)(R7.SXTW<<1) // 4bd82778 MOVH R5, (R1)(R2<<1) // 25782278 MOVH R7, (R2)(R5.SXTX<<1) // 47f82578