compile: X1 is named as RA under RISC-V, not LR

Ref: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#general-registers

This commit does not modify any working code, it only alter one line of comment to enhance readability.

src/cmd/compile/internal/riscv64/ssa.go

@@ -18,7 +18,7 @@ import (
 // ssaRegToReg maps ssa register numbers to obj register numbers.
 var ssaRegToReg = []int16{
 	riscv.REG_X0,
-	// X1 (LR): unused
+	// X1 (ra): unused
 	riscv.REG_X2,
 	riscv.REG_X3,
 	riscv.REG_X4,