413 lines
10 KiB
C
413 lines
10 KiB
C
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/****************************************************************************
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For Alpha Linux, BusToMem() and MemToBus() can be simply memcpy(), BUT:
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we need to prevent unaligned operations when accessing DENSE space on the BUS,
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as the video memory is mmap'd that way. The below code does this.
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NOTE: we could simply use the "memcpy()" from LIBC here, but that, currently, is
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not as fast.
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Thanks to Linus Torvalds for contributing this code.
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****************************************************************************/
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#ifdef HAVE_XORG_CONFIG_H
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#include <xorg-config.h>
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#endif
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#include <X11/X.h>
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86_OSlib.h"
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#ifdef __alpha__
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#include "compiler.h"
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/*
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* The Jensen lacks dense memory, thus we have to address the bus via
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* the sparse addressing scheme. These routines are only used in s3im.c
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* Non time critical code uses SlowBCopy_{from/to} bus.
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*
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* Martin Ostermann (ost@comnets.rwth-aachen.de) - Apr.-Sep. 1996
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*/
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#ifdef TEST_JENSEN_CODE /* define to test the Sparse addressing on a non-Jensen */
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#define LWORD_CODING (0x18)
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#define SPARSE (5)
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#else
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#define LWORD_CODING (0x60)
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#define SPARSE (7)
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#endif
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void
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xf86JensenMemToBus(char *Base, long dst, long src, int count)
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{
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if( ((long)src^((long)dst)) & 3) {
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/* src & dst are NOT aligned to each other */
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unsigned long addr;
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unsigned long low_word, high_word,last_read;
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long rm,loop;
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unsigned long tmp,org,org2,mask,src_org,count_org;
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src_org=src;
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count_org=count;
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/* add EISA longword coding and round off*/
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addr = (long)(Base+(dst<<SPARSE) + LWORD_CODING) & ~(3<<SPARSE);
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rm = (long)dst & 3;
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count += rm;
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count = count_org + rm;
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org = *(volatile unsigned int *)addr;
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__asm__("ldq_u %0,%1"
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:"=r" (low_word):"m" (*(unsigned long *)(src_org)));
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src = src_org - rm;
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if( count > 4 ) {
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last_read = src_org+count_org - 1;
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__asm__("ldq_u %0,%1"
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:"=r" (high_word):"m" (*(unsigned long *)(src+4)));
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__asm__("extll %1,%2,%0"
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:"=r" (low_word)
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:"r" (low_word), "r" ((unsigned long)(src)));
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__asm__("extlh %1,%2,%0"
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:"=r" (tmp)
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:"r" (high_word), "r" ((unsigned long)(src)));
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tmp |= low_word;
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src += 4;
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__asm__("mskqh %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" (rm));
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__asm__("mskql %1,%2,%0"
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:"=r" (org2)
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:"r" (org), "r" (rm));
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tmp |= org2;
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loop = (count-4) >> 2; /* loop eqv. count>=4 ; count -= 4 */
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while (loop) {
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/* tmp to be stored completly -- need to read next word*/
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low_word = high_word;
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*(volatile unsigned int *) (addr) = tmp;
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__asm__("ldq_u %0,%1"
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:"=r" (high_word):"m" (*(unsigned long*)(src+4)));
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loop --;
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__asm__("extll %1,%2,%0"
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:"=r" (low_word)
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:"r" (low_word), "r" ((unsigned long)src));
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__asm__("extlh %1,%2,%0"
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:"=r" (tmp)
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:"r" (high_word), "r" ((unsigned long)src));
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src += 4;
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tmp |= low_word;
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addr += 4<<SPARSE;
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}
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if ( count & 3 ) {
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/* Store tmp completly, and possibly read one more word.*/
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*(volatile unsigned int *) (addr) = tmp;
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__asm__("ldq_u %0,%1"
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:"=r" (tmp):"m" (*((unsigned long *)(last_read)) ));
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addr += 4<<SPARSE;
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__asm__("extll %1,%2,%0"
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:"=r" (low_word)
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:"r" (high_word), "r" ((unsigned long)src));
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__asm__("extlh %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" ((unsigned long)src));
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tmp |= low_word;
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org = *(volatile unsigned int *)addr;
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__asm__("mskql %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" (count&3));
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__asm__("mskqh %1,%2,%0"
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:"=r" (org)
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:"r" (org), "r" (count&3));
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tmp |= org;
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}
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*(volatile unsigned int *) (addr) = tmp;
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return;
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} else { /* count > 4 */
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__asm__("ldq_u %0,%1"
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:"=r" (high_word):"m" (*(unsigned long *)(src+4)));
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__asm__("extll %1,%2,%0"
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:"=r" (low_word)
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:"r" (low_word), "r" ((unsigned long)(src)));
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__asm__("extlh %1,%2,%0"
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:"=r" (tmp)
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:"r" (high_word), "r" ((unsigned long)(src)));
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tmp |= low_word;
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if( count < 4 ) {
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mask = -1;
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__asm__("mskqh %1,%2,%0"
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:"=r" (mask)
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:"r" (mask), "r" (rm));
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__asm__("mskql %1,%2,%0"
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:"=r" (mask)
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:"r" (mask), "r" (count));
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tmp = (tmp & mask) | (org & ~mask);
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*(volatile unsigned int *) (addr) = tmp;
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return;
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} else {
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__asm__("mskqh %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" (rm));
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__asm__("mskql %1,%2,%0"
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:"=r" (org2)
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:"r" (org), "r" (rm));
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tmp |= org2;
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*(volatile unsigned int *) (addr) = tmp;
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return;
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}
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}
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} else { /* src & dst are aligned to each other */
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unsigned long addr;
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unsigned int tmp,org,rm;
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unsigned int *src_r;
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/* add EISA longword coding and round off*/
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addr = (long)(Base+(dst<<SPARSE) + LWORD_CODING) & ~(3<<SPARSE);
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src_r = (unsigned int*)((long)src & ~3L);
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rm=(long)src & 3;
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count += rm;
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tmp = *src_r;
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org = *(volatile unsigned int *)addr;
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__asm__("mskqh %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" (rm));
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__asm__("mskql %1,%2,%0"
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:"=r" (org)
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:"r" (org), "r" (rm));
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tmp |= org;
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while (count > 4) {
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*(volatile unsigned int *) addr = tmp;
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addr += 4<<SPARSE;
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src_r += 1;
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tmp = *src_r;
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count -= 4;
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}
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org = *(volatile unsigned int *)addr;
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__asm__("mskql %1,%2,%0"
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:"=r" (tmp)
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:"r" (tmp), "r" (count));
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__asm__("mskqh %1,%2,%0"
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:"=r" (org)
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:"r" (org), "r" (count));
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tmp |= org;
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*(volatile unsigned int *) (addr) = tmp;
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}
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}
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void
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xf86JensenBusToMem(char *Base, char *dst, unsigned long src, int count)
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{
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#if 0
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/* Optimization of BusToMem() is left as an exercise to the reader ;-)
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* Consider that ldq_u/extlh/extll won't work because of the bus being
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* only 4 bytes wide!
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*/
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#else
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unsigned long addr;
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long result;
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addr = (unsigned long)(Base+(src<<SPARSE)) ;
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while( addr & (3<<SPARSE) ){
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if(count <= 0) return;
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result = *(volatile int *) addr;
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result >>= ((addr>>SPARSE) & 3) * 8;
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*dst++ = (char) result;
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addr += 1<<SPARSE;
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count--;
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}
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count -=4;
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while(count >= 0){
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int i;
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result = *(volatile int *) (addr+LWORD_CODING);
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for(i=4;i--;) {
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*dst++ = (char) result;
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result >>= 8;
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}
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addr += 4<<SPARSE;
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count -= 4;
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}
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count +=4;
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while( count ){
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result = *(volatile int *) addr;
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result >>= ((addr>>SPARSE) & 3) * 8;
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*dst++ = (char) result;
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addr += 1<<SPARSE;
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count--;
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}
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#endif
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}
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static unsigned long __memcpy(unsigned long dest, unsigned long src, int n);
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_X_EXPORT void
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xf86BusToMem(unsigned char *dst, unsigned char *src, int len)
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{
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__memcpy((unsigned long)dst, (unsigned long)src, len);
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}
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_X_EXPORT void
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xf86MemToBus(unsigned char *dst, unsigned char *src, int len)
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{
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if (len == sizeof(int))
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if (!(((long)src | (long)dst) & 3))
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*((unsigned int*)dst) = *((unsigned int*)(src));
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else {
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int i;
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if (((long)src) & 3)
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i = ldl_u((unsigned int*)src);
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else
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i = *(unsigned int*)src;
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if (((long)dst) & 3)
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stl_u(i,(unsigned int*)dst);
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else
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*(unsigned int*)dst = i;
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}
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else
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__memcpy((unsigned long)dst, (unsigned long)src, len);
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}
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/*
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* linux/arch/alpha/lib/memcpy.c
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*
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* Copyright (C) 1995 Linus Torvalds, used with his permission.
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*/
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/*
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* This is a reasonably optimized memcpy() routine.
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*/
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/*
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* Note that the C code is written to be optimized into good assembly. However,
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* at this point gcc is unable to sanely compile "if (n >= 0)", resulting in a
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* explicit compare against 0 (instead of just using the proper "blt reg, xx" or
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* "bge reg, xx"). I hope alpha-gcc will be fixed to notice this eventually..
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*/
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/*
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* This should be done in one go with ldq_u*2/mask/stq_u. Do it
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* with a macro so that we can fix it up later..
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*/
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#define ALIGN_DEST_TO8(d,s,n) \
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while (d & 7) { \
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if (n <= 0) return; \
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n--; \
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*(char *) d = *(char *) s; \
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d++; s++; \
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}
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/*
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* This should similarly be done with ldq_u*2/mask/stq. The destination
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* is aligned, but we don't fill in a full quad-word
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*/
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#define DO_REST(d,s,n) \
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while (n > 0) { \
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n--; \
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*(char *) d = *(char *) s; \
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d++; s++; \
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}
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/*
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* This should be done with ldq/mask/stq. The source and destination are
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* aligned, but we don't fill in a full quad-word
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*/
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#define DO_REST_ALIGNED(d,s,n) DO_REST(d,s,n)
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/*
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* This does unaligned memory copies. We want to avoid storing to
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* an unaligned address, as that would do a read-modify-write cycle.
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* We also want to avoid double-reading the unaligned reads.
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*
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* Note the ordering to try to avoid load (and address generation) latencies.
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*/
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static __inline__ void __memcpy_unaligned(unsigned long d, unsigned long s, long n)
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{
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ALIGN_DEST_TO8(d,s,n);
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n -= 8; /* to avoid compare against 8 in the loop */
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if (n >= 0) {
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unsigned long low_word, high_word;
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__asm__("ldq_u %0,%1":"=r" (low_word):"m" (*(unsigned long *) s));
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do {
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unsigned long tmp;
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__asm__("ldq_u %0,%1":"=r" (high_word):"m" (*(unsigned long *)(s+8)));
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n -= 8;
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__asm__("extql %1,%2,%0"
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:"=r" (low_word)
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:"r" (low_word), "r" (s));
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__asm__("extqh %1,%2,%0"
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:"=r" (tmp)
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:"r" (high_word), "r" (s));
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s += 8;
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*(unsigned long *) d = low_word | tmp;
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d += 8;
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low_word = high_word;
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} while (n >= 0);
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}
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n += 8;
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DO_REST(d,s,n);
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}
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/*
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* Hmm.. Strange. The __asm__ here is there to make gcc use a integer register
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* for the load-store. I don't know why, but it would seem that using a floating
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* point register for the move seems to slow things down (very small difference,
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* though).
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*
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* Note the ordering to try to avoid load (and address generation) latencies.
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*/
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static __inline__ void __memcpy_aligned(unsigned long d, unsigned long s, long n)
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{
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ALIGN_DEST_TO8(d,s,n);
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n -= 8;
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while (n >= 0) {
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unsigned long tmp;
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__asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
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n -= 8;
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s += 8;
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*(unsigned long *) d = tmp;
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d += 8;
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}
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n += 8;
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DO_REST_ALIGNED(d,s,n);
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}
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static unsigned long __memcpy(unsigned long dest, unsigned long src, int n)
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{
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if (!((dest ^ src) & 7)) {
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__memcpy_aligned(dest, src, n);
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return dest;
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}
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__memcpy_unaligned(dest, src, n);
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return dest;
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}
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#else /* __alpha__ */
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void
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xf86BusToMem(unsigned char *dst, unsigned char *src, int len)
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{
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memcpy(dst, src, len);
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}
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void
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xf86MemToBus(unsigned char *dst, unsigned char *src, int len)
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{
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memcpy(dst, src, len);
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}
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#endif /* __alpha__ */
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