524 lines
13 KiB
C
524 lines
13 KiB
C
/*
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* Created 1998 by David Bateman <dbateman@eng.uts.edu.au>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of the authors not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. The authors makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as is" without express or implied warranty.
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*
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* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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/*
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* The functions in this file are used to read/write the C&T extension register
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* and supply MMIO replacements of the VGA register access functions in
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* vgaHW.c for chips that support MMIO access (eg 69000). Unlike the MGA
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* chips, for instance, the C&T chipsets don't have a direct mapping between
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* the MMIO mapped vga registers and the PIO versions.
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*
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* In General, these are the ONLY supported way of access the video processors
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* registers. Exception are
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*
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* 1) chipsFindIsaDevice, where we don't know the chipset and so we don't know
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* if the chipset supports MMIO access to its VGA registers, and we don't
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* know the chips MemBase address and so can't map the VGA registers even
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* if the chip did support MMIO. This effectively limits the use of non-PCI
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* MMIO and multihead to a single card accessing 0x3D6/0x3D7. I.E. You can
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* only have a single C&T card in a non-PCI multihead arrangement. Also as
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* ISA has no method to disable I/O access to a card ISA multihead will
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* never be supported.
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*
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* 2) ct_Blitter.h, ct_BlitMM.h and ct_BltHiQV.h, where speed is crucial and
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* we know exactly whether we are using MMIO or PIO.
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*
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* 3) The 6554x 32bit DRxx in ct_cursor.c where the choice between MMIO and
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* PIO is made explicitly
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*/
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/* All drivers should typically include these */
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#include "xf86.h"
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#include "xf86_OSproc.h"
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/* Everything using inb/outb, etc needs "compiler.h" */
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#include "compiler.h"
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/* Drivers that need to access the PCI config space directly need this */
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#include "xf86Pci.h"
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/* Driver specific headers */
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#include "ct_driver.h"
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#define CHIPS_MONO_STAT_1 0x3BA
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#define CHIPS_STAT_0 0x3BA
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#define CHIPS_MSS 0x3CB
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#define CHIPS_IOSS 0x3CD
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#define CHIPS_FR_INDEX 0x3D0
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#define CHIPS_FR_DATA 0x3D1
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#define CHIPS_MR_INDEX 0x3D2
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#define CHIPS_MR_DATA 0x3D3
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#define CHIPS_XR_INDEX 0x3D6
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#define CHIPS_XR_DATA 0x3D7
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#define CHIPS_COLOR_STAT_1 0x3DA
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#define CHIPS_MMIO_MONO_CRTC_INDEX 0x768
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#define CHIPS_MMIO_MONO_CRTC_DATA 0x769
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#define CHIPS_MMIO_MONO_STAT_1 0x774
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#define CHIPS_MMIO_ATTR_INDEX 0x780
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#define CHIPS_MMIO_ATTR_DATA_W 0x780
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#define CHIPS_MMIO_ATTR_DATA_R 0x781
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#define CHIPS_MMIO_STAT_0 0x784
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#define CHIPS_MMIO_MISC_OUT_W 0x784
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#define CHIPS_MMIO_SEQ_INDEX 0x788
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#define CHIPS_MMIO_SEQ_DATA 0x789
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#define CHIPS_MMIO_DAC_MASK 0x78C
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#define CHIPS_MMIO_DAC_READ_ADDR 0x78D
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#define CHIPS_MMIO_DAC_WRITE_ADDR 0x790
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#define CHIPS_MMIO_DAC_DATA 0x791
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#define CHIPS_MMIO_FEATURE_R 0x794
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#define CHIPS_MMIO_MSS 0x795
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#define CHIPS_MMIO_MISC_OUT_R 0x798
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#define CHIPS_MMIO_IOSS 0x799
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#define CHIPS_MMIO_GRAPH_INDEX 0x79C
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#define CHIPS_MMIO_GRAPH_DATA 0x79D
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#define CHIPS_MMIO_FR_INDEX 0x7A0
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#define CHIPS_MMIO_FR_DATA 0x7A1
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#define CHIPS_MMIO_MR_INDEX 0x7A4
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#define CHIPS_MMIO_MR_DATA 0x7A5
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#define CHIPS_MMIO_COLOR_CRTC_INDEX 0x7A8
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#define CHIPS_MMIO_COLOR_CRTC_DATA 0x7A9
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#define CHIPS_MMIO_XR_INDEX 0x7AC
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#define CHIPS_MMIO_XR_DATA 0x7AD
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#define CHIPS_MMIO_COLOR_STAT_1 0x7B4
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/*
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* PIO Access to the C&T extension registers
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*/
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void
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chipsStdWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
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outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
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}
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static CARD8
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chipsStdReadXR(CHIPSPtr cPtr, CARD8 index)
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{
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outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
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return inb(cPtr->PIOBase + CHIPS_XR_DATA);
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}
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static void
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chipsStdWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
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outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
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}
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static CARD8
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chipsStdReadFR(CHIPSPtr cPtr, CARD8 index)
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{
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outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
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return inb(cPtr->PIOBase + CHIPS_FR_DATA);
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}
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static void
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chipsStdWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
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outb(cPtr->PIOBase + CHIPS_MR_DATA, value);
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}
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static CARD8
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chipsStdReadMR(CHIPSPtr cPtr, CARD8 index)
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{
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outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
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return inb(cPtr->PIOBase + CHIPS_MR_DATA);
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}
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static void
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chipsStdWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
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{
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outb(cPtr->PIOBase + CHIPS_MSS, value);
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}
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static CARD8
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chipsStdReadMSS(CHIPSPtr cPtr)
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{
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return inb(cPtr->PIOBase + CHIPS_MSS);
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}
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static void
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chipsStdWriteIOSS(CHIPSPtr cPtr, CARD8 value)
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{
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outb(cPtr->PIOBase + CHIPS_IOSS, value);
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}
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static CARD8
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chipsStdReadIOSS(CHIPSPtr cPtr)
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{
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return inb(cPtr->PIOBase + CHIPS_IOSS);
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}
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void
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CHIPSSetStdExtFuncs(CHIPSPtr cPtr)
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{
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cPtr->writeFR = chipsStdWriteFR;
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cPtr->readFR = chipsStdReadFR;
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cPtr->writeMR = chipsStdWriteMR;
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cPtr->readMR = chipsStdReadMR;
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cPtr->writeXR = chipsStdWriteXR;
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cPtr->readXR = chipsStdReadXR;
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cPtr->writeMSS = chipsStdWriteMSS;
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cPtr->readMSS = chipsStdReadMSS;
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cPtr->writeIOSS = chipsStdWriteIOSS;
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cPtr->readIOSS = chipsStdReadIOSS;
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}
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/*
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* MMIO Access to the C&T extension registers
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*/
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#define chipsminb(p) MMIO_IN8(cPtr->MMIOBaseVGA, (p))
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#define chipsmoutb(p,v) MMIO_OUT8(cPtr->MMIOBaseVGA, (p),(v))
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static void
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chipsMmioWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
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chipsmoutb(CHIPS_MMIO_XR_DATA, value);
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}
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static CARD8
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chipsMmioReadXR(CHIPSPtr cPtr, CARD8 index)
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{
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chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
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return chipsminb(CHIPS_MMIO_XR_DATA);
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}
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static void
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chipsMmioWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
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chipsmoutb(CHIPS_MMIO_FR_DATA, value);
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}
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static CARD8
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chipsMmioReadFR(CHIPSPtr cPtr, CARD8 index)
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{
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chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
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return chipsminb(CHIPS_MMIO_FR_DATA);
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}
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static void
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chipsMmioWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
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{
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chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
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chipsmoutb(CHIPS_MMIO_MR_DATA, value);
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}
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static CARD8
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chipsMmioReadMR(CHIPSPtr cPtr, CARD8 index)
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{
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chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
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return chipsminb(CHIPS_MMIO_MR_DATA);
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}
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static void
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chipsMmioWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
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{
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/* 69030 MMIO Fix.
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*
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* <value> determines which MMIOBase to use; either
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* Pipe A or Pipe B. -GHB
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*/
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if ((value & MSS_SHADOW) == MSS_PIPE_B)
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cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeB;
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else
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cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeA;
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hwp->MMIOBase = cPtr->MMIOBaseVGA;
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/* Since our Pipe constants don't set bit 3 of MSS, the value
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* written here has no effect on the hardware's behavior. It
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* does allow us to use the value returned by readMSS() to key
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* the above logic, though. -GHB
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*/
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chipsmoutb(CHIPS_MMIO_MSS, value);
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}
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static CARD8
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chipsMmioReadMSS(CHIPSPtr cPtr)
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{
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return chipsminb(CHIPS_MMIO_MSS);
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}
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static void
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chipsMmioWriteIOSS(CHIPSPtr cPtr, CARD8 value)
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{
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chipsmoutb(CHIPS_MMIO_IOSS, value);
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}
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static CARD8
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chipsMmioReadIOSS(CHIPSPtr cPtr)
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{
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return chipsminb(CHIPS_MMIO_IOSS);
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}
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void
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CHIPSSetMmioExtFuncs(CHIPSPtr cPtr)
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{
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cPtr->writeFR = chipsMmioWriteFR;
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cPtr->readFR = chipsMmioReadFR;
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cPtr->writeMR = chipsMmioWriteMR;
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cPtr->readMR = chipsMmioReadMR;
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cPtr->writeXR = chipsMmioWriteXR;
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cPtr->readXR = chipsMmioReadXR;
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cPtr->writeMSS = chipsMmioWriteMSS;
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cPtr->readMSS = chipsMmioReadMSS;
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cPtr->writeIOSS = chipsMmioWriteIOSS;
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cPtr->readIOSS = chipsMmioReadIOSS;
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}
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/*
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* MMIO versions of the VGA register access functions.
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*/
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#define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
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#define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
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static void
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chipsMmioWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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if (hwp->IOBase == VGA_IOBASE_MONO) {
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moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
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moutb(CHIPS_MMIO_MONO_CRTC_DATA, value);
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} else {
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moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
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moutb(CHIPS_MMIO_COLOR_CRTC_DATA, value);
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}
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}
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static CARD8
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chipsMmioReadCrtc(vgaHWPtr hwp, CARD8 index)
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{
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if (hwp->IOBase == VGA_IOBASE_MONO) {
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moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
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return minb(CHIPS_MMIO_MONO_CRTC_DATA);
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} else {
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moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
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return minb(CHIPS_MMIO_COLOR_CRTC_DATA);
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}
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}
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static void
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chipsMmioWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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moutb(CHIPS_MMIO_GRAPH_INDEX, index);
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moutb(CHIPS_MMIO_GRAPH_DATA, value);
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}
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static CARD8
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chipsMmioReadGr(vgaHWPtr hwp, CARD8 index)
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{
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moutb(CHIPS_MMIO_GRAPH_INDEX, index);
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return minb(CHIPS_MMIO_GRAPH_DATA);
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}
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static void
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chipsMmioWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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moutb(CHIPS_MMIO_SEQ_INDEX, index);
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moutb(CHIPS_MMIO_SEQ_DATA, value);
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}
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static CARD8
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chipsMmioReadSeq(vgaHWPtr hwp, CARD8 index)
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{
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moutb(CHIPS_MMIO_SEQ_INDEX, index);
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return minb(CHIPS_MMIO_SEQ_DATA);
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}
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static void
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chipsMmioWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
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{
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if (hwp->paletteEnabled)
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index &= ~0x20;
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else
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index |= 0x20;
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if (hwp->IOBase == VGA_IOBASE_MONO)
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(void) minb(CHIPS_MMIO_MONO_STAT_1);
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else
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(void) minb(CHIPS_MMIO_COLOR_STAT_1);
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moutb(CHIPS_MMIO_ATTR_INDEX, index);
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moutb(CHIPS_MMIO_ATTR_DATA_W, value);
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}
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static CARD8
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chipsMmioReadAttr(vgaHWPtr hwp, CARD8 index)
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{
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if (hwp->paletteEnabled)
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index &= ~0x20;
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else
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index |= 0x20;
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if (hwp->IOBase == VGA_IOBASE_MONO)
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(void) minb(CHIPS_MMIO_MONO_STAT_1);
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else
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(void) minb(CHIPS_MMIO_COLOR_STAT_1);
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moutb(CHIPS_MMIO_ATTR_INDEX, index);
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return minb(CHIPS_MMIO_ATTR_DATA_R);
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}
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static void
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chipsMmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
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{
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moutb(CHIPS_MMIO_MISC_OUT_W, value);
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}
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static CARD8
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chipsMmioReadMiscOut(vgaHWPtr hwp)
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{
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return minb(CHIPS_MMIO_MISC_OUT_R);
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}
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static void
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chipsMmioEnablePalette(vgaHWPtr hwp)
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{
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if (hwp->IOBase == VGA_IOBASE_MONO)
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(void) minb(CHIPS_MMIO_MONO_STAT_1);
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else
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(void) minb(CHIPS_MMIO_COLOR_STAT_1);
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moutb(CHIPS_MMIO_ATTR_INDEX, 0x00);
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hwp->paletteEnabled = TRUE;
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}
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static void
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chipsMmioDisablePalette(vgaHWPtr hwp)
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{
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if (hwp->IOBase == VGA_IOBASE_MONO)
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(void) minb(CHIPS_MMIO_MONO_STAT_1);
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else
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(void) minb(CHIPS_MMIO_COLOR_STAT_1);
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moutb(CHIPS_MMIO_ATTR_INDEX, 0x20);
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hwp->paletteEnabled = FALSE;
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}
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static void
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chipsMmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
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{
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moutb(CHIPS_MMIO_DAC_MASK, value);
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}
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static CARD8
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chipsMmioReadDacMask(vgaHWPtr hwp)
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{
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return minb(CHIPS_MMIO_DAC_MASK);
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}
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static void
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chipsMmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
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{
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moutb(CHIPS_MMIO_DAC_READ_ADDR, value);
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}
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static void
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chipsMmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
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{
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moutb(CHIPS_MMIO_DAC_WRITE_ADDR, value);
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}
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static void
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chipsMmioWriteDacData(vgaHWPtr hwp, CARD8 value)
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{
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moutb(CHIPS_MMIO_DAC_DATA, value);
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}
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static CARD8
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chipsMmioReadDacData(vgaHWPtr hwp)
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{
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return minb(CHIPS_MMIO_DAC_DATA);
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}
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static CARD8
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chipsMmioReadST00(vgaHWPtr hwp)
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{
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return minb(CHIPS_MMIO_STAT_0);
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}
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static CARD8
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chipsMmioReadST01(vgaHWPtr hwp)
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{
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if (hwp->IOBase == VGA_IOBASE_MONO)
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return minb(CHIPS_MMIO_MONO_STAT_1);
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else
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return minb(CHIPS_MMIO_COLOR_STAT_1);
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}
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static CARD8
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chipsMmioReadFCR(vgaHWPtr hwp)
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{
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return minb(CHIPS_MMIO_FEATURE_R);
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}
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|
|
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static void
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|
chipsMmioWriteFCR(vgaHWPtr hwp, CARD8 value)
|
|
{
|
|
if (hwp->IOBase == VGA_IOBASE_MONO) {
|
|
moutb(CHIPS_MMIO_MONO_STAT_1, value);
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} else {
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|
moutb(CHIPS_MMIO_COLOR_STAT_1, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset)
|
|
{
|
|
vgaHWPtr hwp = VGAHWPTR(pScrn);
|
|
|
|
hwp->writeCrtc = chipsMmioWriteCrtc;
|
|
hwp->readCrtc = chipsMmioReadCrtc;
|
|
hwp->writeGr = chipsMmioWriteGr;
|
|
hwp->readGr = chipsMmioReadGr;
|
|
hwp->writeAttr = chipsMmioWriteAttr;
|
|
hwp->readAttr = chipsMmioReadAttr;
|
|
hwp->writeSeq = chipsMmioWriteSeq;
|
|
hwp->readSeq = chipsMmioReadSeq;
|
|
hwp->writeMiscOut = chipsMmioWriteMiscOut;
|
|
hwp->readMiscOut = chipsMmioReadMiscOut;
|
|
hwp->enablePalette = chipsMmioEnablePalette;
|
|
hwp->disablePalette = chipsMmioDisablePalette;
|
|
hwp->writeDacMask = chipsMmioWriteDacMask;
|
|
hwp->readDacMask = chipsMmioReadDacMask;
|
|
hwp->writeDacWriteAddr = chipsMmioWriteDacWriteAddr;
|
|
hwp->writeDacReadAddr = chipsMmioWriteDacReadAddr;
|
|
hwp->writeDacData = chipsMmioWriteDacData;
|
|
hwp->readDacData = chipsMmioReadDacData;
|
|
hwp->readST00 = chipsMmioReadST00;
|
|
hwp->readST01 = chipsMmioReadST01;
|
|
hwp->readFCR = chipsMmioReadFCR;
|
|
hwp->writeFCR = chipsMmioWriteFCR;
|
|
hwp->MMIOBase = base;
|
|
hwp->MMIOOffset = offset;
|
|
}
|
|
|
|
|
|
|
|
|