134 lines
4.3 KiB
C
134 lines
4.3 KiB
C
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v 1.2 2003/07/08 15:39:48 tsi Exp $ */
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/*
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
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* VA Linux Systems Inc., Fremont, California.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors:
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* Kevin E. Martin <martin@xfree86.org>
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* Rickard E. Faith <faith@valinux.com>
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* Alan Hourihane <alanh@fairlite.demon.co.uk>
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*
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* References:
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*
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* !!!! FIXME !!!!
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* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
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* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
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* 1999.
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*
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* !!!! FIXME !!!!
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* RAGE 128 Software Development Manual (Technical Reference Manual P/N
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* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
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*
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*/
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#ifndef _RADEON_MACROS_H_
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#define _RADEON_MACROS_H_
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#include "compiler.h"
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#define RADEON_BIOS8(v) (info->VBIOS[v])
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#define RADEON_BIOS16(v) (info->VBIOS[v] | \
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(info->VBIOS[(v) + 1] << 8))
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#define RADEON_BIOS32(v) (info->VBIOS[v] | \
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(info->VBIOS[(v) + 1] << 8) | \
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(info->VBIOS[(v) + 2] << 16) | \
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(info->VBIOS[(v) + 3] << 24))
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/* Memory mapped register access macros */
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#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
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#define INREG16(addr) MMIO_IN16(RADEONMMIO, addr)
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#define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
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#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
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#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val)
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#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)
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#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr)))
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#define OUTREGP(addr, val, mask) \
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do { \
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CARD32 tmp = INREG(addr); \
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tmp &= (mask); \
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tmp |= ((val) & ~(mask)); \
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OUTREG(addr, tmp); \
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} while (0)
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#define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr)
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#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val)
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#define OUTPLLP(pScrn, addr, val, mask) \
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do { \
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CARD32 tmp_ = INPLL(pScrn, addr); \
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tmp_ &= (mask); \
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tmp_ |= ((val) & ~(mask)); \
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OUTPLL(pScrn, addr, tmp_); \
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} while (0)
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#define OUTPAL_START(idx) \
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do { \
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OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
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} while (0)
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#define OUTPAL_NEXT(r, g, b) \
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do { \
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OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
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} while (0)
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#define OUTPAL_NEXT_CARD32(v) \
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do { \
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OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
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} while (0)
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#define OUTPAL(idx, r, g, b) \
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do { \
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OUTPAL_START((idx)); \
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OUTPAL_NEXT((r), (g), (b)); \
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} while (0)
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#define INPAL_START(idx) \
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do { \
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OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
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} while (0)
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#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
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#define PAL_SELECT(idx) \
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do { \
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if (!idx) { \
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OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
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(CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \
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} else { \
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OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
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RADEON_DAC2_PALETTE_ACC_CTL); \
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} \
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} while (0)
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#endif
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