222 lines
7.0 KiB
C
222 lines
7.0 KiB
C
/*
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
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* VA Linux Systems Inc., Fremont, California.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors:
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* Kevin E. Martin <martin@xfree86.org>
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* Gareth Hughes <gareth@valinux.com>
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*
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*/
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#ifndef _RADEON_SAREA_H_
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#define _RADEON_SAREA_H_
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the kernel file (radeon_drm.h)
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*/
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#ifndef __RADEON_SAREA_DEFINES__
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#define __RADEON_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer? */
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#define RADEON_UPLOAD_CONTEXT 0x00000001
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#define RADEON_UPLOAD_VERTFMT 0x00000002
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#define RADEON_UPLOAD_LINE 0x00000004
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#define RADEON_UPLOAD_BUMPMAP 0x00000008
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#define RADEON_UPLOAD_MASKS 0x00000010
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#define RADEON_UPLOAD_VIEWPORT 0x00000020
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#define RADEON_UPLOAD_SETUP 0x00000040
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#define RADEON_UPLOAD_TCL 0x00000080
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#define RADEON_UPLOAD_MISC 0x00000100
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#define RADEON_UPLOAD_TEX0 0x00000200
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#define RADEON_UPLOAD_TEX1 0x00000400
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#define RADEON_UPLOAD_TEX2 0x00000800
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#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
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#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
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#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
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#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
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#define RADEON_REQUIRE_QUIESCENCE 0x00010000
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#define RADEON_UPLOAD_ZBIAS 0x00020000
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#define RADEON_UPLOAD_ALL 0x0002ffff
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#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff
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#define RADEON_FRONT 0x1
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#define RADEON_BACK 0x2
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#define RADEON_DEPTH 0x4
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#define RADEON_STENCIL 0x8
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/* Primitive types */
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#define RADEON_POINTS 0x1
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#define RADEON_LINES 0x2
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#define RADEON_LINE_STRIP 0x3
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#define RADEON_TRIANGLES 0x4
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#define RADEON_TRIANGLE_FAN 0x5
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#define RADEON_TRIANGLE_STRIP 0x6
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#define RADEON_3VTX_POINTS 0x9
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#define RADEON_3VTX_LINES 0xa
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/* Vertex/indirect buffer size */
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#define RADEON_BUFFER_SIZE 65536
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/* Byte offsets for indirect buffer data */
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#define RADEON_INDEX_PRIM_OFFSET 20
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#define RADEON_HOSTDATA_BLIT_OFFSET 32
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#define RADEON_SCRATCH_REG_OFFSET 32
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/* Keep these small for testing */
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#define RADEON_NR_SAREA_CLIPRECTS 12
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#define RADEON_MAX_TEXTURE_LEVELS 12
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#define RADEON_MAX_TEXTURE_UNITS 3
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/* Blits have strict offset rules. All blit offset must be aligned on
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* a 1K-byte boundary.
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*/
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#define RADEON_OFFSET_SHIFT 10
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#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
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#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
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#endif /* __RADEON_SAREA_DEFINES__ */
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typedef struct {
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unsigned int red;
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unsigned int green;
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unsigned int blue;
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unsigned int alpha;
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} radeon_color_regs_t;
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typedef struct {
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/* Context state */
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unsigned int pp_misc;
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unsigned int pp_fog_color;
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unsigned int re_solid_color;
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unsigned int rb3d_blendcntl;
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unsigned int rb3d_depthoffset;
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unsigned int rb3d_depthpitch;
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unsigned int rb3d_zstencilcntl;
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unsigned int pp_cntl;
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unsigned int rb3d_cntl;
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unsigned int rb3d_coloroffset;
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unsigned int re_width_height;
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unsigned int rb3d_colorpitch;
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unsigned int se_cntl;
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/* Vertex format state */
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unsigned int se_coord_fmt;
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/* Line state */
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unsigned int re_line_pattern;
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unsigned int re_line_state;
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unsigned int se_line_width;
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/* Bumpmap state */
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unsigned int pp_lum_matrix;
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unsigned int pp_rot_matrix_0;
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unsigned int pp_rot_matrix_1;
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/* Mask state */
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unsigned int rb3d_stencilrefmask;
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unsigned int rb3d_ropcntl;
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unsigned int rb3d_planemask;
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/* Viewport state */
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unsigned int se_vport_xscale;
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unsigned int se_vport_xoffset;
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unsigned int se_vport_yscale;
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unsigned int se_vport_yoffset;
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unsigned int se_vport_zscale;
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unsigned int se_vport_zoffset;
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/* Setup state */
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unsigned int se_cntl_status;
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/* Misc state */
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unsigned int re_top_left;
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unsigned int re_misc;
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} radeon_context_regs_t;
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/* Setup registers for each texture unit */
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typedef struct {
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unsigned int pp_txfilter;
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unsigned int pp_txformat;
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unsigned int pp_txoffset;
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unsigned int pp_txcblend;
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unsigned int pp_txablend;
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unsigned int pp_tfactor;
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unsigned int pp_border_color;
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} radeon_texture_regs_t;
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typedef struct {
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/* The channel for communication of state information to the kernel
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* on firing a vertex buffer.
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*/
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radeon_context_regs_t ContextState;
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radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
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unsigned int dirty;
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unsigned int vertsize;
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unsigned int vc_format;
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/* The current cliprects, or a subset thereof */
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XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Counters for throttling of rendering clients */
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unsigned int last_frame;
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unsigned int last_dispatch;
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unsigned int last_clear;
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/* Maintain an LRU of contiguous regions of texture space. If you
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* think you own a region of texture memory, and it has an age
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* different to the one you set, then you are mistaken and it has
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* been stolen by another client. If global texAge hasn't changed,
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* there is no need to walk the list.
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*
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* These regions can be used as a proxy for the fine-grained texture
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* information of other clients - by maintaining them in the same
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* lru which is used to age their own textures, clients have an
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* approximate lru for the whole of global texture space, and can
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* make informed decisions as to which areas to kick out. There is
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* no need to choose whether to kick out your own texture or someone
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* else's - simply eject them all in LRU order.
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*/
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/* Last elt is sentinal */
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drmTextureRegion texList[ATI_NR_TEX_HEAPS][ATI_NR_TEX_REGIONS+1];
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/* last time texture was uploaded */
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unsigned int texAge[ATI_NR_TEX_HEAPS];
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int ctxOwner; /* last context to upload state */
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int pfAllowPageFlip; /* set by the 2d driver, read by the client */
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int pfCurrentPage; /* set by kernel, read by others */
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int crtc2_base; /* for pageflipping with CloneMode */
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} RADEONSAREAPriv, *RADEONSAREAPrivPtr;
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#endif
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