727 lines
26 KiB
C
727 lines
26 KiB
C
/*
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* Copyright 1998 by Alan Hourihane, Wigan, England.
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Alan Hourihane not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Alan Hourihane makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as is" without express or implied warranty.
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*
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* ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*
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* Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
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*
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* Modified from IBM.c to support TI RAMDAC routines
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* by Jens Owen, <jens@tungstengraphics.com>.
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*/
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#ifdef HAVE_XORG_CONFIG_H
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#include <xorg-config.h>
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#endif
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#include "xf86.h"
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#include "xf86_OSproc.h"
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#include "xf86Cursor.h"
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#define INIT_TI_RAMDAC_INFO
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#include "TIPriv.h"
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#include "xf86RamDacPriv.h"
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/* The following values are in kHz */
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#define TI_MIN_VCO_FREQ 110000
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#define TI_MAX_VCO_FREQ 220000
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unsigned long
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TIramdacCalculateMNPForClock(unsigned long RefClock, /* In 100Hz units */
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unsigned long ReqClock, /* In 100Hz units */
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char IsPixClock, /* boolean, is this the pixel or the sys clock */
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unsigned long MinClock, /* Min VCO rating */
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unsigned long MaxClock, /* Max VCO rating */
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unsigned long *rM, /* M Out */
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unsigned long *rN, /* N Out */
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unsigned long *rP /* Min P In, P Out */
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)
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{
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unsigned long n, p;
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unsigned long best_m = 0, best_n = 0;
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double VCO, IntRef = (double) RefClock;
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double m_err, inc_m, calc_m;
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unsigned long ActualClock;
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/* Make sure that MinClock <= ReqClock <= MaxClock */
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if (ReqClock < MinClock)
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ReqClock = MinClock;
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if (ReqClock > MaxClock)
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ReqClock = MaxClock;
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/*
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* ActualClock = VCO / 2 ^ p
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* Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ
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* Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
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* we don't have to bother checking for this maximum limit.
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*/
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VCO = (double) ReqClock;
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for (p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; (p)++)
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VCO *= 2.0;
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/*
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* We avoid doing multiplications by ( 65 - n ),
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* and add an increment instead - this keeps any error small.
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*/
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inc_m = VCO / (IntRef * 8.0);
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/* Initial value of calc_m for the loop */
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calc_m = inc_m + inc_m + inc_m;
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/* Initial amount of error for an integer - impossibly large */
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m_err = 2.0;
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/* Search for the closest INTEGER value of ( 65 - m ) */
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for (n = 3; n <= 25; (n)++, calc_m += inc_m) {
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/* Ignore values of ( 65 - m ) which we can't use */
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if (calc_m < 3.0 || calc_m > 64.0)
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continue;
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/*
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* Pick the closest INTEGER (has smallest fractional part).
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* The optimizer should clean this up for us.
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*/
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if ((calc_m - (int) calc_m) < m_err) {
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m_err = calc_m - (int) calc_m;
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best_m = (int) calc_m;
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best_n = n;
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}
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}
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/* 65 - ( 65 - x ) = x */
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*rM = 65 - best_m;
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*rN = 65 - best_n;
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*rP = p;
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/* Now all the calculations can be completed */
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VCO = 8.0 * IntRef * best_m / best_n;
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ActualClock = VCO / (1 << p);
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DebugF("f_out=%ld f_vco=%.1f n=%lu m=%lu p=%lu\n",
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ActualClock, VCO, *rN, *rM, *rP);
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return ActualClock;
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}
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void
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TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
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RamDacRegRecPtr ramdacReg)
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{
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int i;
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unsigned long status;
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/* Here we pass a short, so that we can evaluate a mask too
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* So that the mask is the high byte and the data the low byte
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* Order is important
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*/
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TIRESTORE(TIDAC_latch_ctrl);
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TIRESTORE(TIDAC_true_color_ctrl);
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TIRESTORE(TIDAC_multiplex_ctrl);
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TIRESTORE(TIDAC_clock_select);
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TIRESTORE(TIDAC_palette_page);
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TIRESTORE(TIDAC_general_ctrl);
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TIRESTORE(TIDAC_misc_ctrl);
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/* 0x2A & 0x2B are reserved */
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TIRESTORE(TIDAC_key_over_low);
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TIRESTORE(TIDAC_key_over_high);
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TIRESTORE(TIDAC_key_red_low);
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TIRESTORE(TIDAC_key_red_high);
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TIRESTORE(TIDAC_key_green_low);
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TIRESTORE(TIDAC_key_green_high);
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TIRESTORE(TIDAC_key_blue_low);
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TIRESTORE(TIDAC_key_blue_high);
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TIRESTORE(TIDAC_key_ctrl);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x30);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x38);
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TIRESTORE(TIDAC_clock_ctrl);
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TIRESTORE(TIDAC_sense_test);
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TIRESTORE(TIDAC_ind_curs_ctrl);
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/* only restore clocks if they were valid to begin with */
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if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
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/* Reset pixel clock */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
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/* Restore N, M & P values for pixel clocks */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
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ramdacReg->DacRegs[TIDAC_PIXEL_N]);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
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ramdacReg->DacRegs[TIDAC_PIXEL_M]);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
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ramdacReg->DacRegs[TIDAC_PIXEL_P]);
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/* wait for pixel clock to lock */
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i = 1000000;
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do {
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status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
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} while ((!(status & 0x40)) && (--i));
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if (!(status & 0x40)) {
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xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
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"Pixel clock setup timed out\n");
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return;
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}
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}
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if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
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/* Reset loop clock */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, 0x70);
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/* Restore N, M & P values for pixel clocks */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
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ramdacReg->DacRegs[TIDAC_LOOP_N]);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
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ramdacReg->DacRegs[TIDAC_LOOP_M]);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
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ramdacReg->DacRegs[TIDAC_LOOP_P]);
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/* wait for loop clock to lock */
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i = 1000000;
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do {
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status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
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} while ((!(status & 0x40)) && (--i));
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if (!(status & 0x40)) {
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xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
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"Loop clock setup timed out\n");
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return;
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}
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}
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/* restore palette */
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(*ramdacPtr->WriteAddress) (pScrn, 0);
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#ifndef NOT_DONE
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for (i = 0; i < 768; i++)
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(*ramdacPtr->WriteData) (pScrn, ramdacReg->DAC[i]);
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#else
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(*ramdacPtr->WriteData) (pScrn, 0);
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(*ramdacPtr->WriteData) (pScrn, 0);
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(*ramdacPtr->WriteData) (pScrn, 0);
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for (i = 0; i < 765; i++)
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(*ramdacPtr->WriteData) (pScrn, 0xff);
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#endif
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}
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void
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TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
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RamDacRegRecPtr ramdacReg)
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{
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int i;
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(*ramdacPtr->ReadAddress) (pScrn, 0);
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for (i = 0; i < 768; i++)
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ramdacReg->DAC[i] = (*ramdacPtr->ReadData) (pScrn);
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/* Read back N,M and P values for pixel clock */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
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ramdacReg->DacRegs[TIDAC_PIXEL_N] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
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ramdacReg->DacRegs[TIDAC_PIXEL_M] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
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ramdacReg->DacRegs[TIDAC_PIXEL_P] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
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/* Read back N,M and P values for loop clock */
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
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ramdacReg->DacRegs[TIDAC_LOOP_N] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
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ramdacReg->DacRegs[TIDAC_LOOP_M] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
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(*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
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ramdacReg->DacRegs[TIDAC_LOOP_P] =
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(*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
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/* Order is important */
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TISAVE(TIDAC_latch_ctrl);
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TISAVE(TIDAC_true_color_ctrl);
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TISAVE(TIDAC_multiplex_ctrl);
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TISAVE(TIDAC_clock_select);
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TISAVE(TIDAC_palette_page);
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TISAVE(TIDAC_general_ctrl);
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TISAVE(TIDAC_misc_ctrl);
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/* 0x2A & 0x2B are reserved */
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TISAVE(TIDAC_key_over_low);
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TISAVE(TIDAC_key_over_high);
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TISAVE(TIDAC_key_red_low);
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TISAVE(TIDAC_key_red_high);
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TISAVE(TIDAC_key_green_low);
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TISAVE(TIDAC_key_green_high);
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TISAVE(TIDAC_key_blue_low);
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TISAVE(TIDAC_key_blue_high);
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TISAVE(TIDAC_key_ctrl);
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TISAVE(TIDAC_clock_ctrl);
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TISAVE(TIDAC_sense_test);
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TISAVE(TIDAC_ind_curs_ctrl);
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}
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RamDacHelperRecPtr
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TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
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{
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RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
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RamDacHelperRecPtr ramdacHelperPtr = NULL;
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Bool RamDacIsSupported = FALSE;
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int TIramdac_ID = -1;
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int i;
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unsigned char id, rev, rev2, id2;
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/* read ID and revision */
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rev = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
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id = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);
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/* check if ID and revision are read only */
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(*ramdacPtr->WriteDAC) (pScrn, ~rev, 0, TIDAC_rev);
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(*ramdacPtr->WriteDAC) (pScrn, ~id, 0, TIDAC_id);
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rev2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
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id2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);
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switch (id) {
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case TIDAC_TVP_3030_ID:
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if (id == id2 && rev == rev2) /* check for READ ONLY */
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TIramdac_ID = TI3030_RAMDAC;
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break;
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case TIDAC_TVP_3026_ID:
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if (id == id2 && rev == rev2) /* check for READ ONLY */
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TIramdac_ID = TI3026_RAMDAC;
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break;
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}
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(*ramdacPtr->WriteDAC) (pScrn, rev, 0, TIDAC_rev);
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(*ramdacPtr->WriteDAC) (pScrn, id, 0, TIDAC_id);
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if (TIramdac_ID == -1) {
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xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
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"Cannot determine TI RAMDAC type, aborting\n");
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return NULL;
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}
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else {
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xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
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"Attached RAMDAC is %s\n",
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TIramdacDeviceInfo[TIramdac_ID & 0xFFFF].DeviceName);
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}
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for (i = 0; ramdacs[i].token != -1; i++) {
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if (ramdacs[i].token == TIramdac_ID)
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RamDacIsSupported = TRUE;
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}
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if (!RamDacIsSupported) {
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xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
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"This TI RAMDAC is NOT supported by this driver, aborting\n");
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return NULL;
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}
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ramdacHelperPtr = RamDacHelperCreateInfoRec();
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switch (TIramdac_ID) {
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case TI3030_RAMDAC:
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ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
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ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
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break;
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case TI3026_RAMDAC:
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ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
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ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
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break;
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}
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ramdacPtr->RamDacType = TIramdac_ID;
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ramdacHelperPtr->RamDacType = TIramdac_ID;
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ramdacHelperPtr->Save = TIramdacSave;
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ramdacHelperPtr->Restore = TIramdacRestore;
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return ramdacHelperPtr;
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}
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void
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TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
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{
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switch (pScrn->bitsPerPixel) {
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case 32:
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/* order is important */
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ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
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ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
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ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
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ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
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ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
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ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
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ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
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/* 0x2A & 0x2B are reserved */
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ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
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ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
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ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
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if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
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ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
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ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
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ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
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}
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ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
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break;
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case 24:
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/* order is important */
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ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
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ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
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ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
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ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
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ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
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ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
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ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
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/* 0x2A & 0x2B are reserved */
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ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
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ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
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ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
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ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
case 16:
|
|
/* order is important */
|
|
#if 0
|
|
/* Matrox driver uses this */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
|
|
#else
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
#endif
|
|
if (pScrn->depth == 16) {
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
|
|
}
|
|
else {
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
|
|
}
|
|
#if 0
|
|
/* Matrox driver uses this */
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
|
|
#else
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
|
|
#endif
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
case 8:
|
|
/* order is important */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
|
|
{
|
|
switch (pScrn->bitsPerPixel) {
|
|
case 32:
|
|
/* order is important */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
|
|
}
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
case 24:
|
|
/* order is important */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
case 16:
|
|
/* order is important */
|
|
#if 0
|
|
/* Matrox driver uses this */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
|
|
#else
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
#endif
|
|
if (pScrn->depth == 16) {
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
|
|
}
|
|
else {
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
|
|
}
|
|
#if 0
|
|
/* Matrox driver uses this */
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
|
|
#else
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
|
|
#endif
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
case 8:
|
|
/* order is important */
|
|
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
|
|
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
|
|
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
|
|
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
|
|
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
|
|
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
|
|
/* 0x2A & 0x2B are reserved */
|
|
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
|
|
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
TIramdacShowCursor(ScrnInfoPtr pScrn)
|
|
{
|
|
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
|
|
|
|
/* Enable cursor - X11 mode */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
|
|
}
|
|
|
|
static void
|
|
TIramdacHideCursor(ScrnInfoPtr pScrn)
|
|
{
|
|
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
|
|
|
|
/* Disable cursor - X11 mode */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
|
|
}
|
|
|
|
static void
|
|
TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
|
|
{
|
|
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
|
|
|
|
x += 64;
|
|
y += 64;
|
|
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
|
|
}
|
|
|
|
static void
|
|
TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
|
|
{
|
|
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
|
|
|
|
/* Background color */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
|
|
((bg & 0x00ff0000) >> 16));
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
|
|
((bg & 0x0000ff00) >> 8));
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (bg & 0x000000ff));
|
|
|
|
/* Foreground color */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
|
|
((fg & 0x00ff0000) >> 16));
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
|
|
((fg & 0x0000ff00) >> 8));
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (fg & 0x000000ff));
|
|
}
|
|
|
|
static Bool
|
|
TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
|
|
{
|
|
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
|
|
int i = 1024;
|
|
|
|
/* reset A9,A8 */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
|
|
/* reset cursor RAM load address A7..A0 */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_INDEX, 0x00, 0x00);
|
|
|
|
while (i--) {
|
|
/* NOT_DONE: might need a delay here */
|
|
(*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
static Bool
|
|
TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
|
|
{
|
|
return TRUE;
|
|
}
|
|
|
|
void
|
|
TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
|
|
{
|
|
infoPtr->MaxWidth = 64;
|
|
infoPtr->MaxHeight = 64;
|
|
infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
|
|
HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
|
|
HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
|
|
infoPtr->SetCursorColors = TIramdacSetCursorColors;
|
|
infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
|
|
infoPtr->LoadCursorImageCheck = TIramdacLoadCursorImage;
|
|
infoPtr->HideCursor = TIramdacHideCursor;
|
|
infoPtr->ShowCursor = TIramdacShowCursor;
|
|
infoPtr->UseHWCursor = TIramdacUseHWCursor;
|
|
}
|
|
|
|
void
|
|
TIramdacLoadPalette(ScrnInfoPtr pScrn,
|
|
int numColors,
|
|
int *indices, LOCO * colors, VisualPtr pVisual)
|
|
{
|
|
RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
|
|
int i, index, shift;
|
|
|
|
if (pScrn->depth == 16) {
|
|
for (i = 0; i < numColors; i++) {
|
|
index = indices[i];
|
|
(*hwp->WriteAddress) (pScrn, index << 2);
|
|
(*hwp->WriteData) (pScrn, colors[index >> 1].red);
|
|
(*hwp->WriteData) (pScrn, colors[index].green);
|
|
(*hwp->WriteData) (pScrn, colors[index >> 1].blue);
|
|
|
|
if (index <= 31) {
|
|
(*hwp->WriteAddress) (pScrn, index << 3);
|
|
(*hwp->WriteData) (pScrn, colors[index].red);
|
|
(*hwp->WriteData) (pScrn, colors[(index << 1) + 1].green);
|
|
(*hwp->WriteData) (pScrn, colors[index].blue);
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
shift = (pScrn->depth == 15) ? 3 : 0;
|
|
|
|
for (i = 0; i < numColors; i++) {
|
|
index = indices[i];
|
|
(*hwp->WriteAddress) (pScrn, index << shift);
|
|
(*hwp->WriteData) (pScrn, colors[index].red);
|
|
(*hwp->WriteData) (pScrn, colors[index].green);
|
|
(*hwp->WriteData) (pScrn, colors[index].blue);
|
|
}
|
|
}
|
|
}
|
|
|
|
TIramdacLoadPaletteProc *
|
|
TIramdacLoadPaletteWeak(void)
|
|
{
|
|
return TIramdacLoadPalette;
|
|
}
|