7b7b372578
This is the last known working version in 'zaphod' mode (one X screen per head in multi-head configs). This makes it possible to update the "real" radeon driver in xf86-video-ati, without breaking existing zaphod setups.
150 lines
7.9 KiB
C
150 lines
7.9 KiB
C
/*
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* RadeonHD R6xx, R7xx Register documentation
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*
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* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2009 Matthias Hopf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _R600_REG_R7xx_H_
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#define _R600_REG_R7xx_H_
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/*
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* Register update for R7xx chips
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*/
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enum {
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R7XX_MC_VM_FB_LOCATION = 0x00002024,
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// GRBM_STATUS = 0x00008010,
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R7XX_TA_BUSY_bit = 1 << 14,
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R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
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RING0_OFFSET_mask = 0xff << 0,
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RING0_OFFSET_shift = 0,
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ISOLATE_ES_ENABLE_bit = 1 << 12,
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ISOLATE_GS_ENABLE_bit = 1 << 13,
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VS_PC_LIMIT_ENABLE_bit = 1 << 14,
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// SQ_ALU_WORD0 = 0x00008dfc,
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// SRC0_SEL_mask = 0x1ff << 0,
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// SRC1_SEL_mask = 0x1ff << 13,
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R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
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R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
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R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
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R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
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// INDEX_MODE_mask = 0x07 << 26,
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R7xx_SQ_INDEX_GLOBAL = 0x05,
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R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
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R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
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R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
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R6xx_FOG_MERGE_bit = 1 << 5,
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R6xx_OMOD_mask = 0x03 << 6,
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R7xx_OMOD_mask = 0x03 << 5,
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R6xx_OMOD_shift = 6,
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R7xx_OMOD_shift = 5,
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R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
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R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
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R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
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R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
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R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
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R7xx_SQ_OP2_INST_ADD_64 = 0x17,
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R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
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R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
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R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
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R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
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R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
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R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
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R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
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R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
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// SQ_ALU_WORD1_OP3 = 0x00008dfc,
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// SRC2_SEL_mask = 0x1ff << 0,
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// R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
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// R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
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// R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
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// R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
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// SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
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R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
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R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
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R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
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R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
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// SQ_CF_ALU_WORD1 = 0x00008dfc,
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R6xx_USES_WATERFALL_bit = 1 << 25,
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R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
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// SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
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// ARRAY_BASE_mask = 0x1fff << 0,
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// TYPE_mask = 0x03 << 13,
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// SQ_EXPORT_PARAM = 0x02,
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// X_UNUSED_FOR_SX_EXPORTS = 0x03,
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// ELEM_SIZE_mask = 0x03 << 30,
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// SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
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// SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
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R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
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// SQ_CF_WORD1 = 0x00008dfc,
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// SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
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R7xx_COUNT_3_bit = 1 << 19,
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// SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
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R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
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R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
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R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
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R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
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R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
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// SQ_VTX_WORD0 = 0x00008dfc,
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// VTX_INST_mask = 0x1f << 0,
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R7xx_SQ_VTX_INST_MEM = 0x02,
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// SQ_VTX_WORD2 = 0x00008dfc,
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R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
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// SQ_TEX_WORD0 = 0x00008dfc,
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// TEX_INST_mask = 0x1f << 0,
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R7xx_X_MEMORY_READ = 0x02,
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R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
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R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
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R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
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R7xx_PA_SC_EDGERULE = 0x00028230,
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R7xx_SPI_THREAD_GROUPING = 0x000286c8,
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PS_GROUPING_mask = 0x1f << 0,
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PS_GROUPING_shift = 0,
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VS_GROUPING_mask = 0x1f << 8,
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VS_GROUPING_shift = 8,
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GS_GROUPING_mask = 0x1f << 16,
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GS_GROUPING_shift = 16,
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ES_GROUPING_mask = 0x1f << 24,
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ES_GROUPING_shift = 24,
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R7xx_CB_SHADER_CONTROL = 0x000287a0,
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RT0_ENABLE_bit = 1 << 0,
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RT1_ENABLE_bit = 1 << 1,
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RT2_ENABLE_bit = 1 << 2,
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RT3_ENABLE_bit = 1 << 3,
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RT4_ENABLE_bit = 1 << 4,
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RT5_ENABLE_bit = 1 << 5,
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RT6_ENABLE_bit = 1 << 6,
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RT7_ENABLE_bit = 1 << 7,
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// DB_ALPHA_TO_MASK = 0x00028d44,
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R7xx_OFFSET_ROUND_bit = 1 << 16,
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// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
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R7xx_TRUNCATE_COORD_bit = 1 << 9,
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R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
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} ;
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#endif /* _R600_REG_R7xx_H_ */
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