149 lines
5.7 KiB
C
149 lines
5.7 KiB
C
/*
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* Copyright © 2011 Red Hat All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/*
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* Authors:
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* Jérôme Glisse <jglisse@redhat.com>
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*/
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#ifndef RADEON_SURFACE_H
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#define RADEON_SURFACE_H
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/* Note :
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*
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* For texture array, the n layer are stored one after the other within each
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* mipmap level. 0 value for field than can be hint is always valid.
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*/
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#define RADEON_SURF_MAX_LEVEL 32
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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#define RADEON_SURF_TYPE_2D 1
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#define RADEON_SURF_TYPE_3D 2
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#define RADEON_SURF_TYPE_CUBEMAP 3
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#define RADEON_SURF_TYPE_1D_ARRAY 4
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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#define RADEON_SURF_MODE_LINEAR 0
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#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
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#define RADEON_SURF_MODE_1D 2
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#define RADEON_SURF_MODE_2D 3
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
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#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
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#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
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#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
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/* first field up to mode need to match r6 struct so that we can reuse
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* same function for linear & linear aligned
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*/
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struct radeon_surface_level {
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uint64_t offset;
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uint64_t slice_size;
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uint32_t npix_x;
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uint32_t npix_y;
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uint32_t npix_z;
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uint32_t nblk_x;
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uint32_t nblk_y;
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uint32_t nblk_z;
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uint32_t pitch_bytes;
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uint32_t mode;
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};
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enum si_tiling_mode {
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SI_TILING_AUTO = 0,
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SI_TILING_COLOR_1D,
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SI_TILING_COLOR_1D_SCANOUT,
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SI_TILING_COLOR_2D_8BPP,
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SI_TILING_COLOR_2D_16BPP,
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SI_TILING_COLOR_2D_32BPP,
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SI_TILING_COLOR_2D_64BPP,
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SI_TILING_COLOR_2D_SCANOUT_16BPP,
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SI_TILING_COLOR_2D_SCANOUT_32BPP,
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SI_TILING_COLOR_LINEAR,
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SI_TILING_STENCIL_1D,
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SI_TILING_STENCIL_2D,
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SI_TILING_STENCIL_2D_2AA,
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SI_TILING_STENCIL_2D_4AA,
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SI_TILING_STENCIL_2D_8AA,
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SI_TILING_DEPTH_1D,
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SI_TILING_DEPTH_2D,
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SI_TILING_DEPTH_2D_2AA,
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SI_TILING_DEPTH_2D_4AA,
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SI_TILING_DEPTH_2D_8AA,
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SI_TILING_LAST_MODE,
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};
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struct radeon_surface {
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uint32_t npix_x;
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uint32_t npix_y;
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uint32_t npix_z;
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uint32_t blk_w;
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uint32_t blk_h;
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uint32_t blk_d;
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uint32_t array_size;
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uint32_t last_level;
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uint32_t bpe;
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uint32_t nsamples;
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uint32_t flags;
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/* Following is updated/fill by the allocator. It's allowed to
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* set some of the value but they are use as hint and can be
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* overridden (things lile bankw/bankh on evergreen for
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* instance).
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*/
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uint64_t bo_size;
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uint64_t bo_alignment;
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/* apply to eg */
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uint32_t bankw;
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uint32_t bankh;
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uint32_t mtilea;
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uint32_t tile_split;
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uint32_t stencil_tile_split;
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uint64_t stencil_offset;
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struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
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struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
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uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
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uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
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};
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struct radeon_surface_manager *radeon_surface_manager_new(int fd);
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void radeon_surface_manager_free(struct radeon_surface_manager *surf_man);
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int radeon_surface_init(struct radeon_surface_manager *surf_man,
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struct radeon_surface *surf);
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int radeon_surface_best(struct radeon_surface_manager *surf_man,
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struct radeon_surface *surf);
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#endif
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