822 lines
21 KiB
C
822 lines
21 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include <pthread.h>
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#include <sched.h>
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#include <sys/ioctl.h>
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#ifdef HAVE_ALLOCA_H
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# include <alloca.h>
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#endif
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#include "xf86drm.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem);
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static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
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/**
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* Create command submission context
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*
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* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
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* \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*
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* \param context - \c [out] GPU Context handle
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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drm_public int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
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uint32_t priority,
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amdgpu_context_handle *context)
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{
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struct amdgpu_context *gpu_context;
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union drm_amdgpu_ctx args;
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int i, j, k;
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int r;
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if (!dev || !context)
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return -EINVAL;
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gpu_context = calloc(1, sizeof(struct amdgpu_context));
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if (!gpu_context)
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return -ENOMEM;
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gpu_context->dev = dev;
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r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
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if (r)
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goto error;
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/* Create the context */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
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args.in.priority = priority;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
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if (r)
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goto error;
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gpu_context->id = args.out.alloc.ctx_id;
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for (i = 0; i < AMDGPU_HW_IP_NUM; i++)
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for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++)
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for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++)
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list_inithead(&gpu_context->sem_list[i][j][k]);
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*context = (amdgpu_context_handle)gpu_context;
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return 0;
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error:
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pthread_mutex_destroy(&gpu_context->sequence_mutex);
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free(gpu_context);
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return r;
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}
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drm_public int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
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amdgpu_context_handle *context)
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{
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return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context);
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}
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/**
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* Release command submission context
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*
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* \param dev - \c [in] amdgpu device handle
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* \param context - \c [in] amdgpu context handle
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*
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* \return 0 on success otherwise POSIX Error code
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*/
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drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle context)
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{
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union drm_amdgpu_ctx args;
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int i, j, k;
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int r;
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if (!context)
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return -EINVAL;
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pthread_mutex_destroy(&context->sequence_mutex);
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/* now deal with kernel side */
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_FREE_CTX;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
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for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) {
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for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) {
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amdgpu_semaphore_handle sem;
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LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) {
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list_del(&sem->list);
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amdgpu_cs_reset_sem(sem);
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amdgpu_cs_unreference_sem(sem);
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}
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}
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}
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}
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free(context);
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return r;
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}
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drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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int master_fd,
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unsigned priority)
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{
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int r;
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if (!dev || !context || master_fd < 0)
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return -EINVAL;
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union drm_amdgpu_sched args;
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
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args.in.fd = dev->fd;
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args.in.priority = priority;
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args.in.ctx_id = context->id;
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r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
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if (r)
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return r;
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return 0;
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}
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drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
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uint32_t *state, uint32_t *hangs)
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{
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union drm_amdgpu_ctx args;
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int r;
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if (!context)
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return -EINVAL;
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memset(&args, 0, sizeof(args));
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args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
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args.in.ctx_id = context->id;
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
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&args, sizeof(args));
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if (!r) {
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*state = args.out.state.reset_status;
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*hangs = args.out.state.hangs;
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}
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return r;
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}
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/**
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* Submit command to kernel DRM
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* \param dev - \c [in] Device handle
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* \param context - \c [in] GPU Context
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* \param ibs_request - \c [in] Pointer to submission requests
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* \param fence - \c [out] return fence for this submission
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*
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* \return 0 on success otherwise POSIX Error code
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* \sa amdgpu_cs_submit()
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*/
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static int amdgpu_cs_submit_one(amdgpu_context_handle context,
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struct amdgpu_cs_request *ibs_request)
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{
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union drm_amdgpu_cs cs;
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uint64_t *chunk_array;
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struct drm_amdgpu_cs_chunk *chunks;
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struct drm_amdgpu_cs_chunk_data *chunk_data;
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struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
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struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
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struct list_head *sem_list;
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amdgpu_semaphore_handle sem, tmp;
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uint32_t i, size, sem_count = 0;
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bool user_fence;
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int r = 0;
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if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
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return -EINVAL;
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if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
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return -EINVAL;
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if (ibs_request->number_of_ibs == 0) {
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ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ;
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return 0;
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}
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user_fence = (ibs_request->fence_info.handle != NULL);
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size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
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chunk_array = alloca(sizeof(uint64_t) * size);
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chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
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size = ibs_request->number_of_ibs + (user_fence ? 1 : 0);
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chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
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memset(&cs, 0, sizeof(cs));
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cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
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cs.in.ctx_id = context->id;
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if (ibs_request->resources)
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cs.in.bo_list_handle = ibs_request->resources->handle;
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cs.in.num_chunks = ibs_request->number_of_ibs;
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/* IB chunks */
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for (i = 0; i < ibs_request->number_of_ibs; i++) {
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struct amdgpu_cs_ib_info *ib;
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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ib = &ibs_request->ibs[i];
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chunk_data[i].ib_data._pad = 0;
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chunk_data[i].ib_data.va_start = ib->ib_mc_address;
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chunk_data[i].ib_data.ib_bytes = ib->size * 4;
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chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
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chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
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chunk_data[i].ib_data.ring = ibs_request->ring;
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chunk_data[i].ib_data.flags = ib->flags;
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}
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pthread_mutex_lock(&context->sequence_mutex);
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if (user_fence) {
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i = cs.in.num_chunks++;
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/* fence chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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/* fence bo handle */
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chunk_data[i].fence_data.handle = ibs_request->fence_info.handle->handle;
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/* offset */
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chunk_data[i].fence_data.offset =
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ibs_request->fence_info.offset * sizeof(uint64_t);
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}
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if (ibs_request->number_of_dependencies) {
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dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) *
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ibs_request->number_of_dependencies);
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if (!dependencies) {
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r = -ENOMEM;
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goto error_unlock;
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}
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for (i = 0; i < ibs_request->number_of_dependencies; ++i) {
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struct amdgpu_cs_fence *info = &ibs_request->dependencies[i];
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struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i];
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dep->ip_type = info->ip_type;
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dep->ip_instance = info->ip_instance;
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dep->ring = info->ring;
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dep->ctx_id = info->context->id;
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dep->handle = info->fence;
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}
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i = cs.in.num_chunks++;
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/* dependencies chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
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* ibs_request->number_of_dependencies;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies;
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}
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sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring];
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LIST_FOR_EACH_ENTRY(sem, sem_list, list)
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sem_count++;
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if (sem_count) {
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sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count);
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if (!sem_dependencies) {
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r = -ENOMEM;
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goto error_unlock;
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}
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sem_count = 0;
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LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, sem_list, list) {
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struct amdgpu_cs_fence *info = &sem->signal_fence;
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struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
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dep->ip_type = info->ip_type;
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dep->ip_instance = info->ip_instance;
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dep->ring = info->ring;
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dep->ctx_id = info->context->id;
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dep->handle = info->fence;
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list_del(&sem->list);
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amdgpu_cs_reset_sem(sem);
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amdgpu_cs_unreference_sem(sem);
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}
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i = cs.in.num_chunks++;
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/* dependencies chunk */
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
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}
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r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
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&cs, sizeof(cs));
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if (r)
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goto error_unlock;
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ibs_request->seq_no = cs.out.handle;
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context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no;
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error_unlock:
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pthread_mutex_unlock(&context->sequence_mutex);
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free(dependencies);
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free(sem_dependencies);
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return r;
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}
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drm_public int amdgpu_cs_submit(amdgpu_context_handle context,
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uint64_t flags,
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struct amdgpu_cs_request *ibs_request,
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uint32_t number_of_requests)
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{
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uint32_t i;
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int r;
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if (!context || !ibs_request)
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return -EINVAL;
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r = 0;
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for (i = 0; i < number_of_requests; i++) {
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r = amdgpu_cs_submit_one(context, ibs_request);
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if (r)
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break;
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ibs_request++;
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}
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return r;
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}
|
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|
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/**
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* Calculate absolute timeout.
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*
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* \param timeout - \c [in] timeout in nanoseconds.
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*
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* \return absolute timeout in nanoseconds
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*/
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drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
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{
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int r;
|
|
|
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if (timeout != AMDGPU_TIMEOUT_INFINITE) {
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struct timespec current;
|
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uint64_t current_ns;
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r = clock_gettime(CLOCK_MONOTONIC, ¤t);
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if (r) {
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fprintf(stderr, "clock_gettime() returned error (%d)!", errno);
|
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return AMDGPU_TIMEOUT_INFINITE;
|
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}
|
|
|
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current_ns = ((uint64_t)current.tv_sec) * 1000000000ull;
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current_ns += current.tv_nsec;
|
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timeout += current_ns;
|
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if (timeout < current_ns)
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timeout = AMDGPU_TIMEOUT_INFINITE;
|
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}
|
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return timeout;
|
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}
|
|
|
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static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
|
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unsigned ip,
|
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unsigned ip_instance,
|
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uint32_t ring,
|
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uint64_t handle,
|
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uint64_t timeout_ns,
|
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uint64_t flags,
|
|
bool *busy)
|
|
{
|
|
amdgpu_device_handle dev = context->dev;
|
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union drm_amdgpu_wait_cs args;
|
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int r;
|
|
|
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memset(&args, 0, sizeof(args));
|
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args.in.handle = handle;
|
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args.in.ip_type = ip;
|
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args.in.ip_instance = ip_instance;
|
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args.in.ring = ring;
|
|
args.in.ctx_id = context->id;
|
|
|
|
if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE)
|
|
args.in.timeout = timeout_ns;
|
|
else
|
|
args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
|
|
|
|
r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
|
|
if (r)
|
|
return -errno;
|
|
|
|
*busy = args.out.status;
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
|
|
uint64_t timeout_ns,
|
|
uint64_t flags,
|
|
uint32_t *expired)
|
|
{
|
|
bool busy = true;
|
|
int r;
|
|
|
|
if (!fence || !expired || !fence->context)
|
|
return -EINVAL;
|
|
if (fence->ip_type >= AMDGPU_HW_IP_NUM)
|
|
return -EINVAL;
|
|
if (fence->ring >= AMDGPU_CS_MAX_RINGS)
|
|
return -EINVAL;
|
|
if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) {
|
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*expired = true;
|
|
return 0;
|
|
}
|
|
|
|
*expired = false;
|
|
|
|
r = amdgpu_ioctl_wait_cs(fence->context, fence->ip_type,
|
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fence->ip_instance, fence->ring,
|
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fence->fence, timeout_ns, flags, &busy);
|
|
|
|
if (!r && !busy)
|
|
*expired = true;
|
|
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
|
|
uint32_t fence_count,
|
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bool wait_all,
|
|
uint64_t timeout_ns,
|
|
uint32_t *status,
|
|
uint32_t *first)
|
|
{
|
|
struct drm_amdgpu_fence *drm_fences;
|
|
amdgpu_device_handle dev = fences[0].context->dev;
|
|
union drm_amdgpu_wait_fences args;
|
|
int r;
|
|
uint32_t i;
|
|
|
|
drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count);
|
|
for (i = 0; i < fence_count; i++) {
|
|
drm_fences[i].ctx_id = fences[i].context->id;
|
|
drm_fences[i].ip_type = fences[i].ip_type;
|
|
drm_fences[i].ip_instance = fences[i].ip_instance;
|
|
drm_fences[i].ring = fences[i].ring;
|
|
drm_fences[i].seq_no = fences[i].fence;
|
|
}
|
|
|
|
memset(&args, 0, sizeof(args));
|
|
args.in.fences = (uint64_t)(uintptr_t)drm_fences;
|
|
args.in.fence_count = fence_count;
|
|
args.in.wait_all = wait_all;
|
|
args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns);
|
|
|
|
r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args);
|
|
if (r)
|
|
return -errno;
|
|
|
|
*status = args.out.status;
|
|
|
|
if (first)
|
|
*first = args.out.first_signaled;
|
|
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
|
|
uint32_t fence_count,
|
|
bool wait_all,
|
|
uint64_t timeout_ns,
|
|
uint32_t *status,
|
|
uint32_t *first)
|
|
{
|
|
uint32_t i;
|
|
|
|
/* Sanity check */
|
|
if (!fences || !status || !fence_count)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < fence_count; i++) {
|
|
if (NULL == fences[i].context)
|
|
return -EINVAL;
|
|
if (fences[i].ip_type >= AMDGPU_HW_IP_NUM)
|
|
return -EINVAL;
|
|
if (fences[i].ring >= AMDGPU_CS_MAX_RINGS)
|
|
return -EINVAL;
|
|
}
|
|
|
|
*status = 0;
|
|
|
|
return amdgpu_ioctl_wait_fences(fences, fence_count, wait_all,
|
|
timeout_ns, status, first);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
|
|
{
|
|
struct amdgpu_semaphore *gpu_semaphore;
|
|
|
|
if (!sem)
|
|
return -EINVAL;
|
|
|
|
gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
|
|
if (!gpu_semaphore)
|
|
return -ENOMEM;
|
|
|
|
atomic_set(&gpu_semaphore->refcount, 1);
|
|
*sem = gpu_semaphore;
|
|
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
|
|
uint32_t ip_type,
|
|
uint32_t ip_instance,
|
|
uint32_t ring,
|
|
amdgpu_semaphore_handle sem)
|
|
{
|
|
if (!ctx || !sem)
|
|
return -EINVAL;
|
|
if (ip_type >= AMDGPU_HW_IP_NUM)
|
|
return -EINVAL;
|
|
if (ring >= AMDGPU_CS_MAX_RINGS)
|
|
return -EINVAL;
|
|
/* sem has been signaled */
|
|
if (sem->signal_fence.context)
|
|
return -EINVAL;
|
|
pthread_mutex_lock(&ctx->sequence_mutex);
|
|
sem->signal_fence.context = ctx;
|
|
sem->signal_fence.ip_type = ip_type;
|
|
sem->signal_fence.ip_instance = ip_instance;
|
|
sem->signal_fence.ring = ring;
|
|
sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
|
|
update_references(NULL, &sem->refcount);
|
|
pthread_mutex_unlock(&ctx->sequence_mutex);
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
|
|
uint32_t ip_type,
|
|
uint32_t ip_instance,
|
|
uint32_t ring,
|
|
amdgpu_semaphore_handle sem)
|
|
{
|
|
if (!ctx || !sem)
|
|
return -EINVAL;
|
|
if (ip_type >= AMDGPU_HW_IP_NUM)
|
|
return -EINVAL;
|
|
if (ring >= AMDGPU_CS_MAX_RINGS)
|
|
return -EINVAL;
|
|
/* must signal first */
|
|
if (!sem->signal_fence.context)
|
|
return -EINVAL;
|
|
|
|
pthread_mutex_lock(&ctx->sequence_mutex);
|
|
list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]);
|
|
pthread_mutex_unlock(&ctx->sequence_mutex);
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
|
|
{
|
|
if (!sem || !sem->signal_fence.context)
|
|
return -EINVAL;
|
|
|
|
sem->signal_fence.context = NULL;
|
|
sem->signal_fence.ip_type = 0;
|
|
sem->signal_fence.ip_instance = 0;
|
|
sem->signal_fence.ring = 0;
|
|
sem->signal_fence.fence = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
|
|
{
|
|
if (!sem)
|
|
return -EINVAL;
|
|
|
|
if (update_references(&sem->refcount, NULL))
|
|
free(sem);
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
|
|
{
|
|
return amdgpu_cs_unreference_sem(sem);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
|
|
uint32_t flags,
|
|
uint32_t *handle)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjCreate(dev->fd, flags, handle);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
|
|
uint32_t *handle)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjCreate(dev->fd, 0, handle);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
|
|
uint32_t handle)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjDestroy(dev->fd, handle);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
|
|
const uint32_t *syncobjs,
|
|
uint32_t syncobj_count)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjReset(dev->fd, syncobjs, syncobj_count);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
|
|
const uint32_t *syncobjs,
|
|
uint32_t syncobj_count)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
|
|
uint32_t *handles, unsigned num_handles,
|
|
int64_t timeout_nsec, unsigned flags,
|
|
uint32_t *first_signaled)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec,
|
|
flags, first_signaled);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
|
|
uint32_t handle,
|
|
int *shared_fd)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
|
|
int shared_fd,
|
|
uint32_t *handle)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
|
|
uint32_t syncobj,
|
|
int *sync_file_fd)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
|
|
uint32_t syncobj,
|
|
int sync_file_fd)
|
|
{
|
|
if (NULL == dev)
|
|
return -EINVAL;
|
|
|
|
return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
|
|
}
|
|
|
|
drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
|
|
amdgpu_context_handle context,
|
|
amdgpu_bo_list_handle bo_list_handle,
|
|
int num_chunks,
|
|
struct drm_amdgpu_cs_chunk *chunks,
|
|
uint64_t *seq_no)
|
|
{
|
|
union drm_amdgpu_cs cs = {0};
|
|
uint64_t *chunk_array;
|
|
int i, r;
|
|
if (num_chunks == 0)
|
|
return -EINVAL;
|
|
|
|
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
|
|
for (i = 0; i < num_chunks; i++)
|
|
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
|
|
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
|
|
cs.in.ctx_id = context->id;
|
|
cs.in.bo_list_handle = bo_list_handle ? bo_list_handle->handle : 0;
|
|
cs.in.num_chunks = num_chunks;
|
|
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
|
|
&cs, sizeof(cs));
|
|
if (r)
|
|
return r;
|
|
|
|
if (seq_no)
|
|
*seq_no = cs.out.handle;
|
|
return 0;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
|
|
amdgpu_context_handle context,
|
|
uint32_t bo_list_handle,
|
|
int num_chunks,
|
|
struct drm_amdgpu_cs_chunk *chunks,
|
|
uint64_t *seq_no)
|
|
{
|
|
union drm_amdgpu_cs cs = {0};
|
|
uint64_t *chunk_array;
|
|
int i, r;
|
|
|
|
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
|
|
for (i = 0; i < num_chunks; i++)
|
|
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
|
|
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
|
|
cs.in.ctx_id = context->id;
|
|
cs.in.bo_list_handle = bo_list_handle;
|
|
cs.in.num_chunks = num_chunks;
|
|
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
|
|
&cs, sizeof(cs));
|
|
if (!r && seq_no)
|
|
*seq_no = cs.out.handle;
|
|
return r;
|
|
}
|
|
|
|
drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
|
|
struct drm_amdgpu_cs_chunk_data *data)
|
|
{
|
|
data->fence_data.handle = fence_info->handle->handle;
|
|
data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
|
|
}
|
|
|
|
drm_public void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
|
|
struct drm_amdgpu_cs_chunk_dep *dep)
|
|
{
|
|
dep->ip_type = fence->ip_type;
|
|
dep->ip_instance = fence->ip_instance;
|
|
dep->ring = fence->ring;
|
|
dep->ctx_id = fence->context->id;
|
|
dep->handle = fence->fence;
|
|
}
|
|
|
|
drm_public int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
|
|
struct amdgpu_cs_fence *fence,
|
|
uint32_t what,
|
|
uint32_t *out_handle)
|
|
{
|
|
union drm_amdgpu_fence_to_handle fth = {0};
|
|
int r;
|
|
|
|
fth.in.fence.ctx_id = fence->context->id;
|
|
fth.in.fence.ip_type = fence->ip_type;
|
|
fth.in.fence.ip_instance = fence->ip_instance;
|
|
fth.in.fence.ring = fence->ring;
|
|
fth.in.fence.seq_no = fence->fence;
|
|
fth.in.what = what;
|
|
|
|
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
|
|
&fth, sizeof(fth));
|
|
if (r == 0)
|
|
*out_handle = fth.out.handle;
|
|
return r;
|
|
}
|