231 lines
8.6 KiB
C
231 lines
8.6 KiB
C
/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_CHIPSET_H
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#define _INTEL_CHIPSET_H
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#define PCI_CHIP_ILD_G 0x0042
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#define PCI_CHIP_ILM_G 0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
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#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
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#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2 0x0412
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#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
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#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
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#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
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#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
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#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
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#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
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#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
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#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */
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#define PCI_CHIP_VALLEYVIEW_1 0x0f31
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#define PCI_CHIP_VALLEYVIEW_2 0x0f32
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#define PCI_CHIP_VALLEYVIEW_3 0x0f33
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#define IS_830(dev) (dev == 0x3577)
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#define IS_845(dev) (dev == 0x2562)
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#define IS_85X(dev) (dev == 0x3582)
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#define IS_865(dev) (dev == 0x2572)
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#define IS_GEN2(dev) (IS_830(dev) || \
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IS_845(dev) || \
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IS_85X(dev) || \
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IS_865(dev))
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#define IS_915G(dev) (dev == 0x2582 || \
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dev == 0x258a)
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#define IS_915GM(dev) (dev == 0x2592)
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#define IS_945G(dev) (dev == 0x2772)
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#define IS_945GM(dev) (dev == 0x27A2 || \
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dev == 0x27AE)
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#define IS_915(dev) (IS_915G(dev) || \
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IS_915GM(dev))
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#define IS_945(dev) (IS_945G(dev) || \
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IS_945GM(dev) || \
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IS_G33(dev) || \
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IS_PINEVIEW(dev))
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#define IS_G33(dev) (dev == 0x29C2 || \
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dev == 0x29B2 || \
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dev == 0x29D2)
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#define IS_PINEVIEW(dev) (dev == 0xa001 || \
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dev == 0xa011)
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#define IS_GEN3(dev) (IS_915(dev) || \
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IS_945(dev) || \
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IS_G33(dev) || \
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IS_PINEVIEW(dev))
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#define IS_I965GM(dev) (dev == 0x2A02)
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#define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \
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((dev) == PCI_CHIP_VALLEYVIEW_1) || \
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((dev) == PCI_CHIP_VALLEYVIEW_2) || \
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((dev) == PCI_CHIP_VALLEYVIEW_3))
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#define IS_GEN4(dev) (dev == 0x2972 || \
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dev == 0x2982 || \
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dev == 0x2992 || \
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dev == 0x29A2 || \
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dev == 0x2A02 || \
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dev == 0x2A12 || \
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dev == 0x2A42 || \
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dev == 0x2E02 || \
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dev == 0x2E12 || \
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dev == 0x2E22 || \
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dev == 0x2E32 || \
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dev == 0x2E42 || \
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dev == 0x0042 || \
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dev == 0x0046 || \
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IS_I965GM(dev) || \
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IS_G4X(dev))
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#define IS_GM45(dev) (dev == 0x2A42)
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#define IS_GEN5(dev) (dev == PCI_CHIP_ILD_G || \
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dev == PCI_CHIP_ILM_G)
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#define IS_GEN6(dev) (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
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dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
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dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
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dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
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dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
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dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
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dev == PCI_CHIP_SANDYBRIDGE_S)
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#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
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IS_HASWELL(devid) || \
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IS_VALLEYVIEW(devid))
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#define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
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dev == PCI_CHIP_IVYBRIDGE_GT2 || \
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dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
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dev == PCI_CHIP_IVYBRIDGE_S || \
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dev == PCI_CHIP_IVYBRIDGE_S_GT2)
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#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
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devid == PCI_CHIP_HASWELL_M_GT1 || \
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devid == PCI_CHIP_HASWELL_S_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_S_GT1)
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#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
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devid == PCI_CHIP_HASWELL_M_GT2 || \
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devid == PCI_CHIP_HASWELL_S_GT2 || \
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devid == PCI_CHIP_HASWELL_SDV_GT2 || \
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devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
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devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
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devid == PCI_CHIP_HASWELL_ULT_GT2 || \
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devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
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devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
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devid == PCI_CHIP_HASWELL_CRW_GT2 || \
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devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
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devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
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devid == PCI_CHIP_HASWELL_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
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#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
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IS_HSW_GT2(devid))
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#define IS_G4X(dev) (dev == 0x2E02 || \
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dev == 0x2E12 || \
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dev == 0x2E22 || \
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dev == 0x2E32 || \
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dev == 0x2E42 || \
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IS_GM45(dev))
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#define IS_9XX(dev) (IS_GEN3(dev) || \
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IS_GEN4(dev) || \
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IS_GEN5(dev) || \
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IS_GEN6(dev) || \
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IS_GEN7(dev))
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#endif /* _INTEL_CHIPSET_H */
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