f6224eae74
Tested by jsg@, kettenis@ and myself on a wide range of intel cards.
141 lines
6.1 KiB
Plaintext
141 lines
6.1 KiB
Plaintext
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Author:
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* Zou Nan hai <nanhai.zou@intel.com>
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*
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*/
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and.nz (1) null g2.0<1,1,1>UD 0x1UD{align1};
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(f0) jmpi direct_idct;
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add (1) g2.8<1>UD g76.8<1,1,1>UD 0UD{align1};
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send (16) 0 g3.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g4.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g5.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g6.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g7.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g8.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g9.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g10.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g11.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g12.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g13.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g14.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g15.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g16.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g17.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g18.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g19.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g20.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g21.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g22.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g23<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g24.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g25.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1};
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send (16) 0 g26.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 };
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direct_idct:
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and.nz (1) null g76.12<1,1,1>UW 0x20UW {align1};
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(f0) jmpi next_block;
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mov (8) g3.0<1>UW 0UW {align1};
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mov (8) g4.0<1>UW 0UW {align1};
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mov (8) g5.0<1>UW 0UW {align1};
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mov (8) g6.0<1>UW 0UW {align1};
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mov (8) g7.0<1>UW 0UW {align1};
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mov (8) g8.0<1>UW 0UW {align1};
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mov (8) g9.0<1>UW 0UW {align1};
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mov (8) g10.0<1>UW 0UW {align1};
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next_block:
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and.nz (1) null g1.12<1,1,1>UW 0x10UW {align1};
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(f0) jmpi next_field;
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mov (8) g3.16<1>UW 0UW {align1};
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mov (8) g4.16<1>UW 0UW {align1};
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mov (8) g5.16<1>UW 0UW {align1};
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mov (8) g6.16<1>UW 0UW {align1};
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mov (8) g7.16<1>UW 0UW {align1};
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mov (8) g8.16<1>UW 0UW {align1};
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mov (8) g9.16<1>UW 0UW {align1};
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mov (8) g10.16<1>UW 0UW {align1};
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next_field:
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and.nz (1) null g1.12<1,1,1>UW 0x8UW {align1};
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(f0) jmpi next_field;
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mov (8) g11.0<1>UW 0UW {align1};
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mov (8) g12.0<1>UW 0UW {align1};
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mov (8) g13.0<1>UW 0UW {align1};
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mov (8) g14.0<1>UW 0UW {align1};
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mov (8) g15.0<1>UW 0UW {align1};
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mov (8) g16.0<1>UW 0UW {align1};
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mov (8) g17.0<1>UW 0UW {align1};
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mov (8) g18.0<1>UW 0UW {align1};
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next_field:
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and.nz (1) null g1.12<1,1,1>UW 0x4UW {align1};
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(f0) jmpi next_field;
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mov (8) g11.16<1>UW 0UW {align1};
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mov (8) g12.16<1>UW 0UW {align1};
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mov (8) g13.16<1>UW 0UW {align1};
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mov (8) g14.16<1>UW 0UW {align1};
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mov (8) g15.16<1>UW 0UW {align1};
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mov (8) g16.16<1>UW 0UW {align1};
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mov (8) g17.16<1>UW 0UW {align1};
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mov (8) g18.16<1>UW 0UW {align1};
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next_field:
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and.nz (1) null g1.12<1,1,1>UW 0x2UW {align1};
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(f0) jmpi next_field;
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mov (16) g19.0<1>UW 0UW {align1};
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mov (16) g20.0<1>UW 0UW {align1};
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mov (16) g21.0<1>UW 0UW {align1};
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mov (16) g22.0<1>UW 0UW {align1};
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next_field:
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and.nz (1) null g1.12<1,1,1>UW 0x1UW {align1};
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(f0) jmpi next_field;
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mov (16) g23.0<1>UW 0UW {align1};
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mov (16) g24.0<1>UW 0UW {align1};
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mov (16) g25.0<1>UW 0UW {align1};
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mov (16) g26.0<1>UW 0UW {align1};
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next_field:
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