f6224eae74
Tested by jsg@, kettenis@ and myself on a wide range of intel cards.
118 lines
5.5 KiB
Plaintext
118 lines
5.5 KiB
Plaintext
/* GRF allocation:
|
|
g1~g30: constant buffer
|
|
g1~g2:intra IQ matrix
|
|
g3~g4:non intra IQ matrix
|
|
g5~g20:IDCT table
|
|
g31: thread payload
|
|
g32: message descriptor for reading reference data
|
|
g58~g81:reference data
|
|
g82: thread payload backup
|
|
g84~g107:IDCT data */
|
|
//mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; //restore x and y
|
|
mov (2) g31.0<1>UD g82.0<2,2,1>UD {align1}; //restore x and y
|
|
|
|
and.nz (1) null g82.30<1,1,1>UB 0x1UW {align1}; //dct_type
|
|
(f0) jmpi field_dct;
|
|
|
|
add.sat (32) g58.0<2>UB g84.0<16,16,1>W g58.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g60.0<2>UB g86.0<16,16,1>W g60.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g62.0<2>UB g88.0<16,16,1>W g62.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g64.0<2>UB g90.0<16,16,1>W g64.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g66.0<2>UB g92.0<16,16,1>W g66.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g68.0<2>UB g94.0<16,16,1>W g68.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g70.0<2>UB g96.0<16,16,1>W g70.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g72.0<2>UB g98.0<16,16,1>W g72.0<16,16,2>UB {align1 compr};
|
|
|
|
add.sat (32) g74.0<2>UB g100.0<16,16,1>W g74.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g76.0<2>UB g102.0<16,16,1>W g76.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g78.0<2>UB g104.0<16,16,1>W g78.0<16,16,2>UB {align1 compr};
|
|
add.sat (32) g80.0<2>UB g106.0<16,16,1>W g80.0<16,16,2>UB {align1 compr};
|
|
jmpi write_back;
|
|
|
|
field_dct:
|
|
add.sat (16) g58.0<2>UB g84.0<16,16,1>W g58.0<16,16,2>UB {align1};
|
|
add.sat (16) g59.0<2>UB g92.0<16,16,1>W g59.0<16,16,2>UB {align1};
|
|
add.sat (16) g60.0<2>UB g85.0<16,16,1>W g60.0<16,16,2>UB {align1};
|
|
add.sat (16) g61.0<2>UB g93.0<16,16,1>W g61.0<16,16,2>UB {align1};
|
|
add.sat (16) g62.0<2>UB g86.0<16,16,1>W g62.0<16,16,2>UB {align1};
|
|
add.sat (16) g63.0<2>UB g94.0<16,16,1>W g63.0<16,16,2>UB {align1};
|
|
add.sat (16) g64.0<2>UB g87.0<16,16,1>W g64.0<16,16,2>UB {align1};
|
|
add.sat (16) g65.0<2>UB g95.0<16,16,1>W g65.0<16,16,2>UB {align1};
|
|
add.sat (16) g66.0<2>UB g88.0<16,16,1>W g66.0<16,16,2>UB {align1};
|
|
add.sat (16) g67.0<2>UB g96.0<16,16,1>W g67.0<16,16,2>UB {align1};
|
|
add.sat (16) g68.0<2>UB g89.0<16,16,1>W g68.0<16,16,2>UB {align1};
|
|
add.sat (16) g69.0<2>UB g97.0<16,16,1>W g69.0<16,16,2>UB {align1};
|
|
add.sat (16) g70.0<2>UB g90.0<16,16,1>W g70.0<16,16,2>UB {align1};
|
|
add.sat (16) g71.0<2>UB g98.0<16,16,1>W g71.0<16,16,2>UB {align1};
|
|
add.sat (16) g72.0<2>UB g91.0<16,16,1>W g72.0<16,16,2>UB {align1};
|
|
add.sat (16) g73.0<2>UB g99.0<16,16,1>W g73.0<16,16,2>UB {align1};
|
|
/*
|
|
add.sat (16) g74.0<2>UB g100.0<16,16,1>W g74.0<16,16,2>UB {align1};
|
|
add.sat (16) g75.0<2>UB g101.0<16,16,1>W g75.0<16,16,2>UB {align1};
|
|
add.sat (16) g76.0<2>UB g102.0<16,16,1>W g76.0<16,16,2>UB {align1};
|
|
add.sat (16) g77.0<2>UB g103.0<16,16,1>W g77.0<16,16,2>UB {align1};
|
|
add.sat (16) g78.0<2>UB g104.0<16,16,1>W g78.0<16,16,2>UB {align1};
|
|
add.sat (16) g79.0<2>UB g105.0<16,16,1>W g79.0<16,16,2>UB {align1};
|
|
add.sat (16) g80.0<2>UB g106.0<16,16,1>W g80.0<16,16,2>UB {align1};
|
|
add.sat (16) g81.0<2>UB g107.0<16,16,1>W g81.0<16,16,2>UB {align1};
|
|
*/
|
|
add (16) g100.0<1>W g100.0<16,16,1>W g74.0<16,16,2>UB {align1};
|
|
add (16) g101.0<1>W g101.0<16,16,1>W g75.0<16,16,2>UB {align1};
|
|
add (16) g102.0<1>W g102.0<16,16,1>W g76.0<16,16,2>UB {align1};
|
|
add (16) g103.0<1>W g103.0<16,16,1>W g77.0<16,16,2>UB {align1};
|
|
add (16) g104.0<1>W g104.0<16,16,1>W g78.0<16,16,2>UB {align1};
|
|
add (16) g105.0<1>W g105.0<16,16,1>W g79.0<16,16,2>UB {align1};
|
|
add (16) g106.0<1>W g106.0<16,16,1>W g80.0<16,16,2>UB {align1};
|
|
add (16) g107.0<1>W g107.0<16,16,1>W g81.0<16,16,2>UB {align1};
|
|
|
|
mov.sat (16) g74.0<2>UB g100.0<16,16,1>W {align1};
|
|
mov.sat (16) g75.0<2>UB g101.0<16,16,1>W {align1};
|
|
mov.sat (16) g76.0<2>UB g102.0<16,16,1>W {align1};
|
|
mov.sat (16) g77.0<2>UB g103.0<16,16,1>W {align1};
|
|
mov.sat (16) g78.0<2>UB g104.0<16,16,1>W {align1};
|
|
mov.sat (16) g79.0<2>UB g105.0<16,16,1>W {align1};
|
|
mov.sat (16) g80.0<2>UB g106.0<16,16,1>W {align1};
|
|
mov.sat (16) g81.0<2>UB g107.0<16,16,1>W {align1};
|
|
|
|
|
|
write_back:
|
|
mov (1) g31.8<1>UD 0x00F000FUD {align1};
|
|
|
|
mov (16) m1.0<1>UB g58.0<16,16,2>UB {align1};
|
|
mov (16) m1.16<1>UB g59.0<16,16,2>UB {align1};
|
|
mov (16) m2.0<1>UB g60.0<16,16,2>UB {align1};
|
|
mov (16) m2.16<1>UB g61.0<16,16,2>UB {align1};
|
|
mov (16) m3.0<1>UB g62.0<16,16,2>UB {align1};
|
|
mov (16) m3.16<1>UB g63.0<16,16,2>UB {align1};
|
|
mov (16) m4.0<1>UB g64.0<16,16,2>UB {align1};
|
|
mov (16) m4.16<1>UB g65.0<16,16,2>UB {align1};
|
|
mov (16) m5.0<1>UB g66.0<16,16,2>UB {align1};
|
|
mov (16) m5.16<1>UB g67.0<16,16,2>UB {align1};
|
|
mov (16) m6.0<1>UB g68.0<16,16,2>UB {align1};
|
|
mov (16) m6.16<1>UB g69.0<16,16,2>UB {align1};
|
|
mov (16) m7.0<1>UB g70.0<16,16,2>UB {align1};
|
|
mov (16) m7.16<1>UB g71.0<16,16,2>UB {align1};
|
|
mov (16) m8.0<1>UB g72.0<16,16,2>UB {align1};
|
|
mov (16) m8.16<1>UB g73.0<16,16,2>UB {align1};
|
|
send (16) 0 acc0<1>UW g31<8,8,1>UW write(0,0,2,0) mlen 9 rlen 0 {align1};
|
|
|
|
//U
|
|
mov (1) g31.8<1>UD 0x0070007UD { align1 };
|
|
shr (2) g31.0<1>UD g31.0<2,2,1>UD 1D {align1};
|
|
|
|
mov (16) m1.0<1>UB g74.0<16,16,2>UB {align1};
|
|
mov (16) m1.16<1>UB g75.0<16,16,2>UB {align1};
|
|
mov (16) m2.0<1>UB g76.0<16,16,2>UB {align1};
|
|
mov (16) m2.16<1>UB g77.0<16,16,2>UB {align1};
|
|
send (16) 0 acc0<1>UW g31<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 };
|
|
|
|
//V
|
|
mov (16) m1.0<1>UB g78.0<16,16,2>UB {align1};
|
|
mov (16) m1.16<1>UB g79.0<16,16,2>UB {align1};
|
|
mov (16) m2.0<1>UB g80.0<16,16,2>UB {align1};
|
|
mov (16) m2.16<1>UB g81.0<16,16,2>UB {align1};
|
|
send (16) 0 acc0<1>UW g31<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 };
|
|
|
|
send (16) 0 acc0<1>UW g0<8,8,1>UW
|
|
thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT};
|