568 lines
18 KiB
C
568 lines
18 KiB
C
/*
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* Modified 1996 by Egbert Eich <eich@xfree86.org>
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* Modified 1996 by David Bateman <dbateman@club-internet.fr>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of the authors not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. The authors makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as is" without express or implied warranty.
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*
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* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _CT_DRIVER_H_
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#define _CT_DRIVER_H_
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#include "ct_pcirename.h"
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#ifdef HAVE_XAA_H
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#include "xaa.h"
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#include "xaalocal.h" /* XAA internals as we replace some of XAA */
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#endif
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#include "vbe.h"
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#include "xf86Cursor.h"
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#include "xf86i2c.h"
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#include "xf86DDC.h"
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#include "xf86xv.h"
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#include "vgaHW.h"
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#include <string.h>
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#include <unistd.h>
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#include "compat-api.h"
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/* Supported chipsets */
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typedef enum {
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CHIPS_CT65520,
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CHIPS_CT65525,
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CHIPS_CT65530,
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CHIPS_CT65535,
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CHIPS_CT65540,
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CHIPS_CT65545,
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CHIPS_CT65546,
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CHIPS_CT65548,
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CHIPS_CT65550,
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CHIPS_CT65554,
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CHIPS_CT65555,
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CHIPS_CT68554,
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CHIPS_CT69000,
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CHIPS_CT69030,
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CHIPS_CT64200,
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CHIPS_CT64300
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} CHIPSType;
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/* Clock related */
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typedef struct {
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unsigned char msr; /* Dot Clock Related */
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unsigned char fcr;
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unsigned char xr02;
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unsigned char xr03;
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unsigned char xr33;
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unsigned char xr54;
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unsigned char fr03;
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int Clock;
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int FPClock;
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} CHIPSClockReg, *CHIPSClockPtr;
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typedef struct {
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unsigned int ProbedClk;
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unsigned int Max; /* Memory Clock Related */
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unsigned int Clk;
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unsigned char M;
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unsigned char N;
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unsigned char P;
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unsigned char PSN;
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unsigned char xrCC;
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unsigned char xrCD;
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unsigned char xrCE;
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} CHIPSMemClockReg, *CHIPSMemClockPtr;
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#define TYPE_HW 0x01
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#define TYPE_PROGRAMMABLE 0x02
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#define GET_TYPE 0x0F
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#define OLD_STYLE 0x10
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#define NEW_STYLE 0x20
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#define HiQV_STYLE 0x30
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#define WINGINE_1_STYLE 0x40 /* 64300: external clock; 4 clocks */
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#define WINGINE_2_STYLE 0x50 /* 64300: internal clock; 2 hw-clocks */
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#define GET_STYLE 0xF0
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#define LCD_TEXT_CLK_FREQ 25000 /* lcd textclock if TYPE_PROGRAMMABLE */
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#define CRT_TEXT_CLK_FREQ 28322 /* crt textclock if TYPE_PROGRAMMABLE */
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#define Fref 14318180 /* The reference clock in Hertz */
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/* The capability flags for the C&T chipsets */
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#define ChipsLinearSupport 0x00000001
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#define ChipsAccelSupport 0x00000002
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#define ChipsFullMMIOSupport 0x00000004
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#define ChipsMMIOSupport 0x00000008
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#define ChipsHDepthSupport 0x00000010
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#define ChipsDPMSSupport 0x00000020
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#define ChipsTMEDSupport 0x00000040
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#define ChipsGammaSupport 0x00000080
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#define ChipsVideoSupport 0x00000100
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#define ChipsDualChannelSupport 0x00000200
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#define ChipsDualRefresh 0x00000400
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#define Chips64BitMemory 0x00000800
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/* Options flags for the C&T chipsets */
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#define ChipsHWCursor 0x00001000
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#define ChipsShadowFB 0x00002000
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#define ChipsUseNewFB 0x00008000
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/* Architecture type flags */
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#define ChipsHiQV 0x00010000
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#define ChipsWingine 0x00020000
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#define IS_Wingine(x) ((x->Flags) & ChipsWingine)
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#define IS_HiQV(x) ((x->Flags) & ChipsHiQV)
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/* Acceleration flags for the C&T chipsets */
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#define ChipsColorTransparency 0x0100000
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#define ChipsImageReadSupport 0x0200000
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/* Overlay Transparency Key */
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#define TRANSPARENCY_KEY 255
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/* Flag Bus Types */
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#define ChipsUnknown 0
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#define ChipsISA 1
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#define ChipsVLB 2
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#define ChipsPCI 3
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#define ChipsCPUDirect 4
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#define ChipsPIB 5
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#define ChipsMCB 6
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/* Macro's to select the 32 bit acceleration registers */
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#define DR(x) cPtr->Regs32[x] /* For CT655xx naming scheme */
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#define MR(x) cPtr->Regs32[x] /* CT655xx MMIO naming scheme */
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#define BR(x) cPtr->Regs32[x] /* For HiQV naming scheme */
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#define MMIOmeml(x) *(CARD32 *)(cPtr->MMIOBase + (x))
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#if 0
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#define MMIOmemw(x) *(CARD16 *)(cPtr->MMIOBase + (x))
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#endif
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/* Monitor or flat panel type flags */
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#define ChipsCRT 0x0010
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#define ChipsLCD 0x1000
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#define ChipsLCDProbed 0x2000
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#define ChipsTFT 0x0100
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#define ChipsDS 0x0200
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#define ChipsDD 0x0400
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#define ChipsSS 0x0800
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#define IS_STN(x) ((x) & 0xE00)
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/* Dual channel register enable masks */
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#define IOSS_MASK 0xE0
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#define IOSS_BOTH 0x13
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#define IOSS_PIPE_A 0x11
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#define IOSS_PIPE_B 0x1E
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#define MSS_MASK 0xF0
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#define MSS_BOTH 0x0B
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#define MSS_PIPE_A 0x02
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#define MSS_PIPE_B 0x05
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/* Aggregate value of MSS shadow bits -GHB */
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#define MSS_SHADOW 0x07
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/* Storage for the registers of the C&T chipsets */
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typedef struct {
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unsigned char XR[0xFF];
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unsigned char CR[0x80];
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unsigned char FR[0x80];
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unsigned char MR[0x80];
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CHIPSClockReg Clock;
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} CHIPSRegRec, *CHIPSRegPtr;
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/* Storage for the flat panel size */
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typedef struct {
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int HDisplay;
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int HRetraceStart;
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int HRetraceEnd;
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int HTotal;
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int VDisplay;
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int VRetraceStart;
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int VTotal;
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} CHIPSPanelSizeRec, *CHIPSPanelSizePtr;
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/* Some variables needed in the XAA acceleration */
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typedef struct {
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/* General variable */
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unsigned int CommandFlags;
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unsigned int BytesPerPixel;
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unsigned int BitsPerPixel;
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unsigned int FbOffset;
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unsigned int PitchInBytes;
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unsigned int ScratchAddress;
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/* 64k for color expansion and imagewrites */
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unsigned char * BltDataWindow;
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/* Hardware cursor address */
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unsigned int CursorAddress;
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Bool UseHWCursor;
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/* Boundaries of the pixmap cache */
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unsigned int CacheStart;
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unsigned int CacheEnd;
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/* Storage for pattern mask */
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int planemask;
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/* Storage for foreground and background color */
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int fgColor;
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int bgColor;
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/* For the 8x8 pattern fills */
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int patternyrot;
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/* For cached stipple fills */
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int SlotWidth;
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/* Variables for the 24bpp fill */
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unsigned char fgpixel;
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unsigned char bgpixel;
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unsigned char xorpixel;
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Bool fastfill;
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Bool rgb24equal;
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int fillindex;
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unsigned int width24bpp;
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unsigned int color24bpp;
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unsigned int rop24bpp;
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} CHIPSACLRec, *CHIPSACLPtr;
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#define CHIPSACLPTR(p) &((CHIPSPtr)((p)->driverPrivate))->Accel
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/* Storage for some register values that are messed up by suspend/resumes */
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typedef struct {
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unsigned char xr02;
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unsigned char xr03;
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unsigned char xr14;
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unsigned char xr15;
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unsigned char vgaIOBaseFlag;
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} CHIPSSuspendHackRec, *CHIPSSuspendHackPtr;
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/* The functions to access the C&T extended registers */
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typedef struct _CHIPSRec *CHIPSPtr;
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typedef CARD8 (*chipsReadXRPtr)(CHIPSPtr cPtr, CARD8 index);
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typedef void (*chipsWriteXRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
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typedef CARD8 (*chipsReadFRPtr)(CHIPSPtr cPtr, CARD8 index);
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typedef void (*chipsWriteFRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
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typedef CARD8 (*chipsReadMRPtr)(CHIPSPtr cPtr, CARD8 index);
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typedef void (*chipsWriteMRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
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typedef CARD8 (*chipsReadMSSPtr)(CHIPSPtr cPtr);
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typedef void (*chipsWriteMSSPtr)(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value);
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typedef CARD8 (*chipsReadIOSSPtr)(CHIPSPtr cPtr);
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typedef void (*chipsWriteIOSSPtr)(CHIPSPtr cPtr, CARD8 value);
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/* The privates of the C&T driver */
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#define CHIPSPTR(p) ((CHIPSPtr)((p)->driverPrivate))
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typedef struct {
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int lastInstance;
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int refCount;
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CARD32 masterFbAddress;
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long masterFbMapSize;
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CARD32 slaveFbAddress;
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long slaveFbMapSize;
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int mastervideoRam;
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int slavevideoRam;
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Bool masterOpen;
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Bool slaveOpen;
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Bool masterActive;
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Bool slaveActive;
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} CHIPSEntRec, *CHIPSEntPtr;
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typedef struct _CHIPSRec {
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pciVideoPtr PciInfo;
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#ifndef XSERVER_LIBPCIACCESS
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PCITAG PciTag;
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#endif
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int Chipset;
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EntityInfoPtr pEnt;
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unsigned long PIOBase;
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unsigned long IOAddress;
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unsigned long FbAddress;
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unsigned int IOBase;
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unsigned char * FbBase;
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unsigned char * MMIOBase;
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unsigned char * MMIOBaseVGA;
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unsigned char * MMIOBasePipeA;
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unsigned char * MMIOBasePipeB;
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long FbMapSize;
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unsigned char * ShadowPtr;
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int ShadowPitch;
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int Rotate;
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void (*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
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int FbOffset16;
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int FbSize16;
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OptionInfoPtr Options;
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CHIPSPanelSizeRec PanelSize;
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int FrameBufferSize;
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Bool SyncResetIgn;
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Bool UseMMIO;
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Bool UseFullMMIO;
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Bool UseDualChannel;
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int Monitor;
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int MinClock;
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int MaxClock;
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CHIPSClockReg SaveClock; /* Storage for ClockSelect */
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CHIPSMemClockReg MemClock;
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unsigned char ClockType;
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unsigned char CRTClk[4];
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unsigned char FPClk[4];
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int FPclock;
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int FPclkInx;
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int CRTclkInx;
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Bool FPClkModified;
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int ClockMulFactor;
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int Rounding;
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CHIPSSuspendHackRec SuspendHack;
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CARD32 PanelType;
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CHIPSRegRec ModeReg;
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CHIPSRegRec SavedReg;
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CHIPSRegRec SavedReg2;
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vgaRegRec VgaSavedReg2;
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unsigned int * Regs32;
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unsigned int Flags;
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CARD32 Bus;
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#ifdef HAVE_XAA_H
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XAAInfoRecPtr AccelInfoRec;
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#endif
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xf86CursorInfoPtr CursorInfoRec;
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CHIPSACLRec Accel;
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unsigned int HWCursorContents;
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Bool HWCursorShown;
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DGAModePtr DGAModes;
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int numDGAModes;
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Bool DGAactive;
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int DGAViewportStatus;
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CloseScreenProcPtr CloseScreen;
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ScreenBlockHandlerProcPtr BlockHandler;
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void (*VideoTimerCallback)(ScrnInfoPtr, Time);
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int videoKey;
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XF86VideoAdaptorPtr adaptor;
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int OverlaySkewX;
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int OverlaySkewY;
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int VideoZoomMax;
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Bool SecondCrtc;
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CHIPSEntPtr entityPrivate;
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unsigned char storeMSS;
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unsigned char storeIOSS;
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#ifdef __arm32__
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#ifdef __NetBSD__
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int TVMode;
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#endif
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int Bank;
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#endif
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unsigned char ddc_mask;
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I2CBusPtr I2C;
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vbeInfoPtr pVbe;
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chipsReadXRPtr readXR;
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chipsWriteXRPtr writeXR;
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chipsReadFRPtr readFR;
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chipsWriteFRPtr writeFR;
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chipsReadMRPtr readMR;
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chipsWriteMRPtr writeMR;
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chipsReadMSSPtr readMSS;
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chipsWriteMSSPtr writeMSS;
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chipsReadIOSSPtr readIOSS;
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chipsWriteIOSSPtr writeIOSS;
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Bool cursorDelay;
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unsigned int viewportMask;
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Bool dualEndianAp;
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} CHIPSRec;
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typedef struct _CHIPSi2c {
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unsigned char i2cClockBit;
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unsigned char i2cDataBit;
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CHIPSPtr cPtr;
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} CHIPSI2CRec, *CHIPSI2CPtr;
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/* External variables */
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extern int ChipsAluConv[];
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extern int ChipsAluConv2[];
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extern int ChipsAluConv3[];
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extern unsigned int ChipsReg32[];
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extern unsigned int ChipsReg32HiQV[];
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/* Prototypes */
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void CHIPSAdjustFrame(ADJUST_FRAME_ARGS_DECL);
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Bool CHIPSSwitchMode(SWITCH_MODE_ARGS_DECL);
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/* video */
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void CHIPSInitVideo(ScreenPtr pScreen);
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void CHIPSResetVideo(ScrnInfoPtr pScrn);
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/* banking */
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int CHIPSSetRead(ScreenPtr pScreen, int bank);
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int CHIPSSetWrite(ScreenPtr pScreen, int bank);
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int CHIPSSetReadWrite(ScreenPtr pScreen, int bank);
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int CHIPSSetReadPlanar(ScreenPtr pScreen, int bank);
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int CHIPSSetWritePlanar(ScreenPtr pScreen, int bank);
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int CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank);
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int CHIPSWINSetRead(ScreenPtr pScreen, int bank);
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int CHIPSWINSetWrite(ScreenPtr pScreen, int bank);
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int CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank);
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int CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank);
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int CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank);
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int CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank);
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int CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank);
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int CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank);
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/* acceleration */
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Bool CHIPSAccelInit(ScreenPtr pScreen);
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void CHIPSSync(ScrnInfoPtr pScrn);
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Bool CHIPSMMIOAccelInit(ScreenPtr pScreen);
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void CHIPSMMIOSync(ScrnInfoPtr pScrn);
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Bool CHIPSHiQVAccelInit(ScreenPtr pScreen);
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void CHIPSHiQVSync(ScrnInfoPtr pScrn);
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Bool CHIPSCursorInit(ScreenPtr pScreen);
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/* register access functions */
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void CHIPSSetStdExtFuncs(CHIPSPtr cPtr);
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void CHIPSSetMmioExtFuncs(CHIPSPtr cPtr);
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void CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset);
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/* ddc */
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extern void chips_ddc1(ScrnInfoPtr pScrn);
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extern Bool chips_i2cInit(ScrnInfoPtr pScrn);
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/* dga */
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Bool CHIPSDGAInit(ScreenPtr pScreen);
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/* shadow fb */
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void chipsRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
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void chipsRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
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void chipsRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
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void chipsRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
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void chipsRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
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void chipsPointerMoved(SCRN_ARG_TYPE arg, int x, int y);
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#if X_BYTE_ORDER == X_BIG_ENDIAN
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# define BE_SWAP_APRETURE(pScrn,cPtr) \
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((pScrn->bitsPerPixel == 16) && cPtr->dualEndianAp)
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#endif
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/*
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* Some macros for switching display channels. NOTE... It appears that we
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* can't write to both display channels at the same time, and so the options
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* MSS_BOTH and IOSS_BOTH should not be used. Need to get around this by set
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* dual channel mode to pipe A by default and handling multiple channel writes
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* in ModeInit..
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*/
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#define DUALOPEN \
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{ \
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/* Set the IOSS/MSS registers to point to the right register set */ \
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if (xf86IsEntityShared(pScrn->entityList[0])) { \
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if (cPtr->SecondCrtc == TRUE) { \
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cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
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IOSS_PIPE_B)); \
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cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
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MSS_MASK) | MSS_PIPE_B)); \
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cPtrEnt->slaveOpen = TRUE; \
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cPtrEnt->slaveActive = TRUE; \
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cPtrEnt->masterActive = FALSE; \
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} else { \
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cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
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IOSS_PIPE_A)); \
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cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
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MSS_MASK) | MSS_PIPE_A)); \
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cPtrEnt->masterOpen = TRUE; \
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cPtrEnt->masterActive = TRUE; \
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cPtrEnt->slaveActive = FALSE; \
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} \
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} else { \
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cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
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IOSS_PIPE_A)); \
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cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
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MSS_MASK) | MSS_PIPE_A)); \
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} \
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}
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#define DUALREOPEN \
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|
{ \
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|
if (xf86IsEntityShared(pScrn->entityList[0])) { \
|
|
if (cPtr->SecondCrtc == TRUE) { \
|
|
if (! cPtrEnt->slaveActive) { \
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|
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
|
|
IOSS_PIPE_B)); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
|
|
MSS_MASK) | MSS_PIPE_B)); \
|
|
cPtrEnt->slaveOpen = TRUE; \
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|
cPtrEnt->slaveActive = TRUE; \
|
|
cPtrEnt->masterActive = FALSE; \
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|
} \
|
|
} else { \
|
|
if (! cPtrEnt->masterActive) { \
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|
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
|
|
IOSS_PIPE_A)); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
|
|
MSS_MASK) | MSS_PIPE_A)); \
|
|
cPtrEnt->masterOpen = TRUE; \
|
|
cPtrEnt->masterActive = TRUE; \
|
|
cPtrEnt->slaveActive = FALSE; \
|
|
} \
|
|
} \
|
|
} \
|
|
}
|
|
|
|
#define DUALCLOSE \
|
|
{ \
|
|
if (! xf86IsEntityShared(pScrn->entityList[0])) { \
|
|
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
|
|
IOSS_PIPE_A)); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
|
|
MSS_MASK) | MSS_PIPE_A)); \
|
|
chipsHWCursorOff(cPtr, pScrn); \
|
|
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, \
|
|
&cPtr->SavedReg, TRUE); \
|
|
chipsLock(pScrn); \
|
|
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | \
|
|
IOSS_PIPE_B)); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS & \
|
|
MSS_MASK) | MSS_PIPE_B)); \
|
|
chipsHWCursorOff(cPtr, pScrn); \
|
|
chipsRestore(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2, TRUE); \
|
|
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
|
|
chipsLock(pScrn); \
|
|
} else { \
|
|
chipsHWCursorOff(cPtr, pScrn); \
|
|
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,\
|
|
TRUE); \
|
|
if (cPtr->SecondCrtc == TRUE) { \
|
|
cPtrEnt->slaveActive = FALSE; \
|
|
cPtrEnt->slaveOpen = FALSE; \
|
|
if (! cPtrEnt->masterActive) { \
|
|
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
|
|
chipsLock(pScrn); \
|
|
} \
|
|
} else { \
|
|
cPtrEnt->masterActive = FALSE; \
|
|
cPtrEnt->masterOpen = FALSE; \
|
|
if (! cPtrEnt->slaveActive) { \
|
|
cPtr->writeIOSS(cPtr, cPtr->storeIOSS); \
|
|
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS); \
|
|
chipsLock(pScrn); \
|
|
} \
|
|
} \
|
|
} \
|
|
}
|
|
|
|
|
|
/* To aid debugging of 32 bit register access we make the following defines */
|
|
/*
|
|
#define DEBUG
|
|
#define CT_HW_DEBUG
|
|
*/
|
|
#if defined(DEBUG) & defined(CT_HW_DEBUG)
|
|
#define HW_DEBUG(x) {usleep(500000); ErrorF("Register/Address: 0x%X\n",x);}
|
|
#else
|
|
#define HW_DEBUG(x)
|
|
#endif
|
|
#endif
|