186 lines
5.9 KiB
C
186 lines
5.9 KiB
C
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/* Definitions for the Chips and Technology BitBLT engine communication. */
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/* These are done using Memory Mapped IO, of the registers */
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/* BitBLT modes for register 93D0. */
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#define ctPATCOPY 0xF0
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#define ctLEFT2RIGHT 0x000
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#define ctRIGHT2LEFT 0x100
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#define ctTOP2BOTTOM 0x000
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#define ctBOTTOM2TOP 0x200
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#define ctSRCSYSTEM 0x400
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#define ctDSTSYSTEM 0x800
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#define ctSRCMONO 0x1000
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#define ctBGTRANSPARENT 0x22000
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#define ctCOLORTRANSENABLE 0x4000
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#define ctCOLORTRANSDISABLE 0x0
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#define ctCOLORTRANSDST 0x8000
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#define ctCOLORTRANSROP 0x0
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#define ctCOLORTRANSEQUAL 0x10000L
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#define ctCOLORTRANSNEQUAL 0x0
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#define ctPATMONO 0x40000L
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#define ctPATSOLID 0x80000L
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#define ctPATSTART0 0x000000L
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#define ctPATSTART1 0x100000L
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#define ctPATSTART2 0x200000L
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#define ctPATSTART3 0x300000L
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#define ctPATSTART4 0x400000L
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#define ctPATSTART5 0x500000L
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#define ctPATSTART6 0x600000L
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#define ctPATSTART7 0x700000L
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#define ctSRCFG 0x000000L /* Where is this for the 65550?? */
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/* The Monochrome expansion register setup */
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#define ctCLIPLEFT(clip) ((clip)&0x3F)
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#define ctCLIPRIGHT(clip) (((clip)&0x3F) << 8)
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#define ctSRCDISCARD(clip) (((clip)&0x3F) << 16)
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#define ctBITALIGN 0x1000000L
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#define ctBYTEALIGN 0x2000000L
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#define ctWORDALIGN 0x3000000L
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#define ctDWORDALIGN 0x4000000L
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#define ctQWORDALIGN 0x5000000L
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/* This shouldn't be used because not all chip rev's
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* have BR09 and BR0A, and I haven't even defined
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* macros to write to these registers
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*/
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#define ctEXPCOLSEL 0x8000000L
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/* Macros to do useful things with the C&T BitBLT engine */
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/* For some odd reason the blitter busy bit occasionly "locks up" when
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* it gets polled to fast. However I have observed this behavior only
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* when doing ScreenToScreenColorExpandFill on a 65550. This operation
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* was broken anyway (the source offest register is not observed) therefore
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* no action was taken.
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*
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* This function uses indirect access to XR20 to test whether the blitter
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* is busy. If the cost of doing this is too high then other options will
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* need to be considered.
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*
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* Note that BR04[31] can't be used as some C&T chipsets lockup when reading
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* the BRxx registers.
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*/
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#define ctBLTWAIT \
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{int timeout; \
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timeout = 0; \
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for (;;) { \
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if (cPtr->Chipset >= CHIPS_CT69000 ) { \
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if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
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break; \
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} else { \
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if (!(cPtr->readXR(cPtr,0x20) & 0x1)) break; \
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} \
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timeout++; \
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if ((cPtr->Chipset < CHIPS_CT69000 && \
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(timeout > 100000)) || timeout > 300000) { \
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unsigned char tmp; \
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ErrorF("timeout\n"); \
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tmp = cPtr->readXR(cPtr, 0x20); \
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cPtr->writeXR(cPtr, 0x20, ((tmp & 0xFD) | 0x2)); \
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usleep(10000); \
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cPtr->writeXR(cPtr, 0x20, (tmp & 0xFD)); \
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break; \
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} \
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} \
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}
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#if X_BYTE_ORDER == X_BIG_ENDIAN
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# define TWEAK_24_BE(c) \
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c = ((c & 0xFF0000) >> 16) | (c & 0xFF00) | (( c & 0xFF) << 16)
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#else
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# define TWEAK_24_BE(c)
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#endif
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#define ctSETROP(op) \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x4), op)
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#define ctSETMONOCTL(op) \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x3), op)
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#define ctSETSRCADDR(srcAddr) \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x6), (srcAddr)&0x7FFFFFL)
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#define ctSETDSTADDR(dstAddr) \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x7), (dstAddr)&0x7FFFFFL)
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#define ctSETPITCH(srcPitch,dstPitch) \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x0), (((dstPitch)&0xFFFF)<<16)| \
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((srcPitch)&0xFFFF))
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#define ctSETHEIGHTWIDTHGO(Height,Width)\
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MMIO_OUT32(cPtr->MMIOBase, BR(0x8), (((Height)&0xFFFF)<<16)| \
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((Width)&0xFFFF))
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#define ctSETPATSRCADDR(srcAddr)\
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MMIO_OUT32(cPtr->MMIOBase, BR(0x5), (srcAddr)&0x7FFFFFL)
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#define ctSETBGCOLOR8(c) {\
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if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
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cAcl->bgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFF)); \
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} \
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}
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#define ctSETBGCOLOR16(c) {\
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if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
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cAcl->bgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFF)); \
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} \
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}
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#define ctSETBGCOLOR24(c) {\
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TWEAK_24_BE(c); \
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if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
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cAcl->bgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFFFF)); \
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} \
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}
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#define ctSETFGCOLOR8(c) {\
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if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
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cAcl->fgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFF)); \
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} \
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}
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#define ctSETFGCOLOR16(c) {\
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if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
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cAcl->fgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFF)); \
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} \
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}
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#define ctSETFGCOLOR24(c) {\
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TWEAK_24_BE(c); \
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if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
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cAcl->fgColor = (c); \
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MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFFFF)); \
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} \
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}
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/* Define a Macro to replicate a planemask 64 times and write to address
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* allocated for planemask pattern */
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#define ctWRITEPLANEMASK8(mask,addr) { \
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if (cAcl->planemask != (mask&0xFF)) { \
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cAcl->planemask = (mask&0xFF); \
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memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \
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} \
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}
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#define ctWRITEPLANEMASK16(mask,addr) { \
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if (cAcl->planemask != (mask&0xFFFF)) { \
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cAcl->planemask = (mask&0xFFFF); \
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{ int i; \
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for (i = 0; i < 64; i++) { \
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memcpy((unsigned char *)cPtr->FbBase + addr \
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+ i * 2, &mask, 2); \
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} \
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} \
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} \
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}
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