243 lines
6.6 KiB
C
243 lines
6.6 KiB
C
/*
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* Copyright 2001 Ani Joshi <ajoshi@unixbox.com>
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*
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* XFree86 4.x driver for S3 chipsets
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*
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation and
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* that the name of Ani Joshi not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. Ani Joshi makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as-is" without express or implied warranty.
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*
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* ANI JOSHI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ANI JOSHI BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*
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*
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*/
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#ifndef _S3_H
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#define _S3_H
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#include "s3_pcirename.h"
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#include <string.h>
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#include "xf86.h"
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#include "xf86Pci.h"
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#include "xf86PciInfo.h"
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#include "xf86RamDac.h"
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#include "xaa.h"
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#include "vbe.h"
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#include "vgaHW.h"
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#include "xf86xv.h"
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#include <X11/extensions/Xv.h>
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#include "fourcc.h"
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typedef struct _S3RegRec {
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unsigned char cr31, cr32, cr33, cr34, cr3a, cr3b, cr3c;
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unsigned char cr3b2, cr3c2;
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unsigned char cr40, cr42, cr43, cr44, cr45;
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unsigned char cr50, cr51, cr53, cr54, cr55, cr58, cr59, cr5a,
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cr5d, cr5e;
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unsigned char cr60, cr61, cr62, cr65, cr66, cr67, cr6d;
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unsigned char s3save[10];
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unsigned char s3syssave[46];
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unsigned char dacregs[0x101];
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unsigned char color_stack[8];
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unsigned char clock;
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} S3RegRec, *S3RegPtr;
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typedef struct {
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unsigned char brightness;
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unsigned char contrast;
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FBAreaPtr area;
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RegionRec clip;
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CARD32 colorKey;
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CARD32 videoStatus;
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Time offTime;
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Time freeTime;
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int lastPort;
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} S3PortPrivRec, *S3PortPrivPtr;
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typedef struct {
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int bitsPerPixel;
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int depth;
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int displayWidth;
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int pixel_code;
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int pixel_bytes;
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DisplayModePtr mode;
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} S3FBLayout;
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typedef struct _S3Rec {
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pciVideoPtr PciInfo;
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#ifndef XSERVER_LIBPCIACCESS
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PCITAG PciTag;
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#endif
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EntityInfoPtr pEnt;
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unsigned long IOAddress;
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unsigned long FBAddress;
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unsigned char * FBBase;
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unsigned char * MMIOBase;
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unsigned long videoRam;
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OptionInfoPtr Options;
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unsigned int Flags;
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Bool NoAccel;
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Bool SWCursor;
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Bool SlowDRAMRefresh;
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Bool SlowDRAM;
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Bool SlowEDODRAM;
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Bool SlowVRAM;
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Bool S3NewMMIO;
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Bool PCIRetry;
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Bool ColorExpandBug;
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XAAInfoRecPtr pXAA;
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xf86CursorInfoPtr pCurs;
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xf86Int10InfoPtr pInt10;
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vbeInfoPtr pVBE;
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XF86VideoAdaptorPtr adaptor;
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S3PortPrivPtr portPrivate;
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DGAModePtr DGAModes;
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int numDGAModes;
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Bool DGAactive;
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int DGAViewportStatus;
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S3FBLayout CurrentLayout;
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RamDacHelperRecPtr RamDac;
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RamDacRecPtr RamDacRec;
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int vgaCRIndex, vgaCRReg;
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int s3Bpp, s3BppDisplayWidth, HDisplay;
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int mclk, MaxClock;
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int pixMuxShift;
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int Chipset, ChipRev;
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int RefClock;
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int s3ScissB, s3ScissR;
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unsigned short BltDir;
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int trans_color;
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int FBCursorOffset;
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S3RegRec SavedRegs;
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S3RegRec ModeRegs;
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unsigned char SAM256;
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void (*DacPreInit)(ScrnInfoPtr pScrn);
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void (*DacInit)(ScrnInfoPtr pScrn,
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DisplayModePtr mode);
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void (*DacSave)(ScrnInfoPtr pScrn);
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void (*DacRestore)(ScrnInfoPtr pScrn);
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Bool (*CursorInit)(ScreenPtr pScreen);
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void (*LoadPalette)(ScrnInfoPtr pScrn, int numColors,
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int *indicies, LOCO *colors,
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VisualPtr pVisual);
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Bool (*CloseScreen)(int, ScreenPtr);
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unsigned char *imageBuffer;
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int imageWidth;
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int imageHeight;
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Bool hwCursor;
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} S3Rec, *S3Ptr;
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#define S3PTR(p) ((S3Ptr)((p)->driverPrivate))
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#define DRIVER_NAME "s3"
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#define DRIVER_VERSION PACKAGE_VERSION
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#define VERSION_MAJOR PACKAGE_VERSION_MAJOR
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#define VERSION_MINOR PACKAGE_VERSION_MINOR
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#define PATCHLEVEL PACKAGE_VERSION_PATCHLEVEL
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#define S3_VERSION ((VERSION_MAJOR << 24) | \
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(VERSION_MINOR << 16) | PATCHLEVEL)
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/*
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* Prototypes
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*/
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Bool S3AccelInit(ScreenPtr pScreen);
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Bool S3AccelInitNewMMIO(ScreenPtr pScreen);
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Bool S3AccelInitPIO(ScreenPtr pScreen);
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Bool S3DGAInit(ScreenPtr pScreen);
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Bool S3SwitchMode(int scrnIndex, DisplayModePtr mode, int flags);
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int S3GetRefClock(ScrnInfoPtr pScrn);
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void S3InitVideo(ScreenPtr pScreen);
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void S3InitStreams(ScrnInfoPtr pScrn, DisplayModePtr mode);
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/* IBMRGB */
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extern RamDacSupportedInfoRec S3IBMRamdacs[];
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Bool S3ProbeIBMramdac(ScrnInfoPtr pScrn);
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void S3IBMRGB_PreInit(ScrnInfoPtr pScrn);
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void S3IBMRGB_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
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void S3IBMRGB_Save(ScrnInfoPtr pScrn);
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void S3IBMRGB_Restore(ScrnInfoPtr pScrn);
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Bool S3IBMRGB_CursorInit(ScreenPtr pScreen);
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/* TRIO64 */
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Bool S3Trio64DACProbe(ScrnInfoPtr pScrn);
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void S3Trio64DAC_PreInit(ScrnInfoPtr pScrn);
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void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
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void S3Trio64DAC_Save(ScrnInfoPtr pScrn);
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void S3Trio64DAC_Restore(ScrnInfoPtr pScrn);
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/* Ti */
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Bool S3TiDACProbe(ScrnInfoPtr pScrn);
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void S3TiDAC_PreInit(ScrnInfoPtr pScrn);
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void S3TiDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
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void S3TiDAC_Save(ScrnInfoPtr pScrn);
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void S3TiDAC_Restore(ScrnInfoPtr pScrn);
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void S3TiLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indicies, LOCO *colors,
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VisualPtr pVisual);
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Bool S3Ti_CursorInit(ScreenPtr pScreen);
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void S3OutTiIndReg(ScrnInfoPtr pScrn, CARD32 reg, unsigned char mask,
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unsigned char data);
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/* s3 gen cursor */
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Bool S3_CursorInit(ScreenPtr pScreen);
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#define TRIO64_RAMDAC 0x8811
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#define TI3025_RAMDAC 0x3025
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#define TI3020_RAMDAC 0x3020
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#define BIOS_BSIZE 1024
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#define BIOS_BASE 0xc0000
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/*
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* Chip...Sets...
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*/
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#define S3_964_SERIES() ((pS3->Chipset == PCI_CHIP_964_0) || \
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(pS3->Chipset == PCI_CHIP_964_1))
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#define S3_TRIO_SERIES() ((pS3->Chipset == PCI_CHIP_TRIO) || \
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(pS3->Chipset == PCI_CHIP_AURORA64VP) || \
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(pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
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(pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
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#endif /* _S3_H */
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