93897d45ea
drmCommandWrite() must be used to issue it. Already merged upstream. ok jsg@
404 lines
10 KiB
C
404 lines
10 KiB
C
/*
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* Copyright © 2008 Dave Airlie
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* Copyright © 2008 Jérôme Glisse
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/*
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* Authors:
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* Dave Airlie
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* Jérôme Glisse <glisse@freedesktop.org>
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*/
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <errno.h>
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#include "xf86drm.h"
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#include "xf86atomic.h"
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#include "drm.h"
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#include "radeon_drm.h"
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#include "radeon_bo.h"
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#include "radeon_bo_int.h"
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#include "radeon_bo_gem.h"
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#include <fcntl.h>
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struct radeon_bo_gem {
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struct radeon_bo_int base;
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uint32_t name;
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int map_count;
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atomic_t reloc_in_cs;
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void *priv_ptr;
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};
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struct bo_manager_gem {
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struct radeon_bo_manager base;
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};
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static int bo_wait(struct radeon_bo_int *boi);
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static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
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uint32_t handle,
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uint32_t size,
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uint32_t alignment,
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uint32_t domains,
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uint32_t flags)
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{
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struct radeon_bo_gem *bo;
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int r;
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bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
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if (bo == NULL) {
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return NULL;
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}
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bo->base.bom = bom;
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bo->base.handle = 0;
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bo->base.size = size;
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bo->base.alignment = alignment;
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bo->base.domains = domains;
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bo->base.flags = flags;
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bo->base.ptr = NULL;
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atomic_set(&bo->reloc_in_cs, 0);
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bo->map_count = 0;
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if (handle) {
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struct drm_gem_open open_arg;
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memset(&open_arg, 0, sizeof(open_arg));
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open_arg.name = handle;
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r = drmIoctl(bom->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
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if (r != 0) {
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free(bo);
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return NULL;
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}
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bo->base.handle = open_arg.handle;
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bo->base.size = open_arg.size;
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bo->name = handle;
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} else {
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struct drm_radeon_gem_create args;
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args.size = size;
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args.alignment = alignment;
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args.initial_domain = bo->base.domains;
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args.flags = 0;
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args.handle = 0;
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r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
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&args, sizeof(args));
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bo->base.handle = args.handle;
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if (r) {
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fprintf(stderr, "Failed to allocate :\n");
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fprintf(stderr, " size : %d bytes\n", size);
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fprintf(stderr, " alignment : %d bytes\n", alignment);
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fprintf(stderr, " domains : %d\n", bo->base.domains);
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free(bo);
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return NULL;
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}
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}
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radeon_bo_ref((struct radeon_bo*)bo);
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return (struct radeon_bo*)bo;
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}
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static void bo_ref(struct radeon_bo_int *boi)
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{
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}
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static struct radeon_bo *bo_unref(struct radeon_bo_int *boi)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi;
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struct drm_gem_close args;
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if (boi->cref) {
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return (struct radeon_bo *)boi;
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}
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if (bo_gem->priv_ptr) {
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munmap(bo_gem->priv_ptr, boi->size);
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}
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/* Zero out args to make valgrind happy */
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memset(&args, 0, sizeof(args));
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/* close object */
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args.handle = boi->handle;
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drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_CLOSE, &args);
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memset(bo_gem, 0, sizeof(struct radeon_bo_gem));
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free(bo_gem);
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return NULL;
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}
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static int bo_map(struct radeon_bo_int *boi, int write)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi;
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struct drm_radeon_gem_mmap args;
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int r;
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void *ptr;
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if (bo_gem->map_count++ != 0) {
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return 0;
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}
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if (bo_gem->priv_ptr) {
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goto wait;
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}
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boi->ptr = NULL;
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/* Zero out args to make valgrind happy */
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memset(&args, 0, sizeof(args));
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args.handle = boi->handle;
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args.offset = 0;
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args.size = (uint64_t)boi->size;
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r = drmCommandWriteRead(boi->bom->fd,
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DRM_RADEON_GEM_MMAP,
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&args,
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sizeof(args));
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if (r) {
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fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
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boi, boi->handle, r);
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return r;
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}
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ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, boi->bom->fd, args.addr_ptr);
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if (ptr == MAP_FAILED)
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return -errno;
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bo_gem->priv_ptr = ptr;
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wait:
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boi->ptr = bo_gem->priv_ptr;
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r = bo_wait(boi);
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if (r)
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return r;
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return 0;
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}
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static int bo_unmap(struct radeon_bo_int *boi)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi;
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if (--bo_gem->map_count > 0) {
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return 0;
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}
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//munmap(bo->ptr, bo->size);
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boi->ptr = NULL;
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return 0;
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}
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static int bo_wait(struct radeon_bo_int *boi)
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{
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struct drm_radeon_gem_wait_idle args;
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int ret;
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/* Zero out args to make valgrind happy */
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memset(&args, 0, sizeof(args));
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args.handle = boi->handle;
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do {
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ret = drmCommandWrite(boi->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
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&args, sizeof(args));
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} while (ret == -EBUSY);
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return ret;
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}
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static int bo_is_busy(struct radeon_bo_int *boi, uint32_t *domain)
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{
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struct drm_radeon_gem_busy args;
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int ret;
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args.handle = boi->handle;
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args.domain = 0;
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ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY,
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&args, sizeof(args));
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*domain = args.domain;
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return ret;
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}
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static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
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uint32_t pitch)
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{
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struct drm_radeon_gem_set_tiling args;
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int r;
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args.handle = boi->handle;
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args.tiling_flags = tiling_flags;
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args.pitch = pitch;
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r = drmCommandWriteRead(boi->bom->fd,
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DRM_RADEON_GEM_SET_TILING,
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&args,
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sizeof(args));
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return r;
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}
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static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
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uint32_t *pitch)
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{
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struct drm_radeon_gem_set_tiling args = {};
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int r;
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args.handle = boi->handle;
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r = drmCommandWriteRead(boi->bom->fd,
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DRM_RADEON_GEM_GET_TILING,
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&args,
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sizeof(args));
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if (r)
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return r;
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*tiling_flags = args.tiling_flags;
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*pitch = args.pitch;
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return r;
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}
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static struct radeon_bo_funcs bo_gem_funcs = {
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bo_open,
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bo_ref,
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bo_unref,
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bo_map,
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bo_unmap,
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bo_wait,
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NULL,
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bo_set_tiling,
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bo_get_tiling,
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bo_is_busy,
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};
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struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
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{
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struct bo_manager_gem *bomg;
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bomg = (struct bo_manager_gem*)calloc(1, sizeof(struct bo_manager_gem));
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if (bomg == NULL) {
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return NULL;
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}
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bomg->base.funcs = &bo_gem_funcs;
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bomg->base.fd = fd;
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return (struct radeon_bo_manager*)bomg;
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}
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void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom)
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{
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struct bo_manager_gem *bomg = (struct bo_manager_gem*)bom;
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if (bom == NULL) {
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return;
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}
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free(bomg);
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}
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uint32_t radeon_gem_name_bo(struct radeon_bo *bo)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
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return bo_gem->name;
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}
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void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
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return &bo_gem->reloc_in_cs;
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}
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int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
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struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
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struct drm_gem_flink flink;
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int r;
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if (bo_gem->name) {
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*name = bo_gem->name;
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return 0;
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}
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flink.handle = bo->handle;
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r = drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_FLINK, &flink);
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if (r) {
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return r;
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}
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bo_gem->name = flink.name;
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*name = flink.name;
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return 0;
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}
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int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
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{
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struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
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struct drm_radeon_gem_set_domain args;
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int r;
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args.handle = bo->handle;
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args.read_domains = read_domains;
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args.write_domain = write_domain;
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r = drmCommandWriteRead(boi->bom->fd,
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DRM_RADEON_GEM_SET_DOMAIN,
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&args,
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sizeof(args));
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return r;
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}
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int radeon_gem_prime_share_bo(struct radeon_bo *bo, int *handle)
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{
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struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
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int ret;
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ret = drmPrimeHandleToFD(bo_gem->base.bom->fd, bo->handle, DRM_CLOEXEC, handle);
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return ret;
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}
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struct radeon_bo *radeon_gem_bo_open_prime(struct radeon_bo_manager *bom,
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int fd_handle,
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uint32_t size)
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{
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struct radeon_bo_gem *bo;
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int r;
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uint32_t handle;
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bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
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if (bo == NULL) {
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return NULL;
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}
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bo->base.bom = bom;
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bo->base.handle = 0;
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bo->base.size = size;
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bo->base.alignment = 0;
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bo->base.domains = RADEON_GEM_DOMAIN_GTT;
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bo->base.flags = 0;
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bo->base.ptr = NULL;
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atomic_set(&bo->reloc_in_cs, 0);
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bo->map_count = 0;
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r = drmPrimeFDToHandle(bom->fd, fd_handle, &handle);
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if (r != 0) {
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free(bo);
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return NULL;
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}
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bo->base.handle = handle;
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bo->name = handle;
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radeon_bo_ref((struct radeon_bo *)bo);
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return (struct radeon_bo *)bo;
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}
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