438 lines
11 KiB
C
438 lines
11 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdio.h>
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#include "CUnit/Basic.h"
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#include "util_math.h"
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#include "amdgpu_test.h"
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#include "uvd_messages.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#define IB_SIZE 4096
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#define MAX_RESOURCES 16
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static amdgpu_device_handle device_handle;
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static uint32_t major_version;
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static uint32_t minor_version;
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static uint32_t family_id;
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static uint32_t chip_rev;
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static uint32_t chip_id;
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static amdgpu_context_handle context_handle;
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static amdgpu_bo_handle ib_handle;
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static uint64_t ib_mc_address;
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static uint32_t *ib_cpu;
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static amdgpu_va_handle ib_va_handle;
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static amdgpu_bo_handle resources[MAX_RESOURCES];
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static unsigned num_resources;
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static void amdgpu_cs_uvd_create(void);
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static void amdgpu_cs_uvd_decode(void);
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static void amdgpu_cs_uvd_destroy(void);
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CU_TestInfo cs_tests[] = {
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{ "UVD create", amdgpu_cs_uvd_create },
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{ "UVD decode", amdgpu_cs_uvd_decode },
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{ "UVD destroy", amdgpu_cs_uvd_destroy },
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CU_TEST_INFO_NULL,
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};
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int suite_cs_tests_init(void)
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{
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amdgpu_bo_handle ib_result_handle;
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void *ib_result_cpu;
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uint64_t ib_result_mc_address;
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amdgpu_va_handle ib_result_va_handle;
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int r;
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r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
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&minor_version, &device_handle);
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if (r) {
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if ((r == -EACCES) && (errno == EACCES))
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printf("\n\nError:%s. "
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"Hint:Try to run this test program as root.",
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strerror(errno));
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return CUE_SINIT_FAILED;
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}
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family_id = device_handle->info.family_id;
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/* VI asic POLARIS10/11 have specific external_rev_id */
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chip_rev = device_handle->info.chip_rev;
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chip_id = device_handle->info.chip_external_rev;
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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if (r)
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return CUE_SINIT_FAILED;
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r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address,
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&ib_result_va_handle);
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if (r)
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return CUE_SINIT_FAILED;
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ib_handle = ib_result_handle;
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ib_mc_address = ib_result_mc_address;
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ib_cpu = ib_result_cpu;
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ib_va_handle = ib_result_va_handle;
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return CUE_SUCCESS;
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}
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int suite_cs_tests_clean(void)
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{
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int r;
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r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
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ib_mc_address, IB_SIZE);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_cs_ctx_free(context_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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r = amdgpu_device_deinitialize(device_handle);
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if (r)
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return CUE_SCLEAN_FAILED;
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return CUE_SUCCESS;
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}
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static int submit(unsigned ndw, unsigned ip)
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{
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info = {0};
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struct amdgpu_cs_fence fence_status = {0};
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uint32_t expired;
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int r;
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ib_info.ib_mc_address = ib_mc_address;
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ib_info.size = ndw;
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ibs_request.ip_type = ip;
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r = amdgpu_bo_list_create(device_handle, num_resources, resources,
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NULL, &ibs_request.resources);
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if (r)
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return r;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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if (r)
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return r;
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r = amdgpu_bo_list_destroy(ibs_request.resources);
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if (r)
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return r;
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fence_status.context = context_handle;
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fence_status.ip_type = ip;
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fence_status.fence = ibs_request.seq_no;
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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if (r)
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return r;
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return 0;
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}
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static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
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{
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ib_cpu[(*idx)++] = 0x3BC4;
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ib_cpu[(*idx)++] = addr;
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ib_cpu[(*idx)++] = 0x3BC5;
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ib_cpu[(*idx)++] = addr >> 32;
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ib_cpu[(*idx)++] = 0x3BC3;
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ib_cpu[(*idx)++] = cmd << 1;
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}
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static void amdgpu_cs_uvd_create(void)
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{
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struct amdgpu_bo_alloc_request req = {0};
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amdgpu_bo_handle buf_handle;
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uint64_t va = 0;
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amdgpu_va_handle va_handle;
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void *msg;
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int i, r;
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req.alloc_size = 4*1024;
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req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_alloc(device_handle,
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amdgpu_gpu_va_range_general,
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4096, 1, 0, &va,
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&va_handle, 0);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(buf_handle, &msg);
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CU_ASSERT_EQUAL(r, 0);
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memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
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if (family_id >= AMDGPU_FAMILY_VI) {
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((uint8_t*)msg)[0x10] = 7;
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/* chip polaris 10/11 */
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if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
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/* dpb size */
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((uint8_t*)msg)[0x28] = 0x00;
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((uint8_t*)msg)[0x29] = 0x94;
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((uint8_t*)msg)[0x2A] = 0x6B;
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((uint8_t*)msg)[0x2B] = 0x00;
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}
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}
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r = amdgpu_bo_cpu_unmap(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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num_resources = 0;
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resources[num_resources++] = buf_handle;
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resources[num_resources++] = ib_handle;
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i = 0;
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uvd_cmd(va, 0x0, &i);
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for (; i % 16; ++i)
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ib_cpu[i] = 0x80000000;
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r = submit(i, AMDGPU_HW_IP_UVD);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_free(va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_free(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_cs_uvd_decode(void)
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{
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const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
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uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
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struct amdgpu_bo_alloc_request req = {0};
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle va_handle;
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uint64_t va = 0;
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uint64_t sum;
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uint8_t *ptr;
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int i, r;
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req.alloc_size = 4*1024; /* msg */
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req.alloc_size += 4*1024; /* fb */
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if (family_id >= AMDGPU_FAMILY_VI)
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req.alloc_size += 4096; /*it_scaling_table*/
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req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
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req.alloc_size += ALIGN(dpb_size, 4*1024);
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req.alloc_size += ALIGN(dt_size, 4*1024);
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req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_alloc(device_handle,
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amdgpu_gpu_va_range_general,
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req.alloc_size, 1, 0, &va,
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&va_handle, 0);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
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AMDGPU_VA_OP_MAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
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CU_ASSERT_EQUAL(r, 0);
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memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
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if (family_id >= AMDGPU_FAMILY_VI) {
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ptr[0x10] = 7;
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ptr[0x98] = 0x00;
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ptr[0x99] = 0x02;
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/* chip polaris10/11 */
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if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
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/*dpb size */
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ptr[0x24] = 0x00;
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ptr[0x25] = 0x94;
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ptr[0x26] = 0x6B;
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ptr[0x27] = 0x00;
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/*ctx size */
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ptr[0x2C] = 0x00;
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ptr[0x2D] = 0xAF;
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ptr[0x2E] = 0x50;
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ptr[0x2F] = 0x00;
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}
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}
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ptr += 4*1024;
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memset(ptr, 0, 4*1024);
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if (family_id >= AMDGPU_FAMILY_VI) {
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ptr += 4*1024;
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memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
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}
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ptr += 4*1024;
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memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
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ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
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memset(ptr, 0, dpb_size);
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ptr += ALIGN(dpb_size, 4*1024);
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memset(ptr, 0, dt_size);
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num_resources = 0;
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resources[num_resources++] = buf_handle;
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resources[num_resources++] = ib_handle;
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msg_addr = va;
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fb_addr = msg_addr + 4*1024;
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if (family_id >= AMDGPU_FAMILY_VI) {
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it_addr = fb_addr + 4*1024;
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bs_addr = it_addr + 4*1024;
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} else
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bs_addr = fb_addr + 4*1024;
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dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
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if ((family_id >= AMDGPU_FAMILY_VI) &&
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(chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
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ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
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}
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dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
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i = 0;
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uvd_cmd(msg_addr, 0x0, &i);
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uvd_cmd(dpb_addr, 0x1, &i);
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uvd_cmd(dt_addr, 0x2, &i);
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uvd_cmd(fb_addr, 0x3, &i);
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uvd_cmd(bs_addr, 0x100, &i);
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if (family_id >= AMDGPU_FAMILY_VI) {
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uvd_cmd(it_addr, 0x204, &i);
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if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
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uvd_cmd(ctx_addr, 0x206, &i);
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}
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ib_cpu[i++] = 0x3BC6;
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ib_cpu[i++] = 0x1;
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for (; i % 16; ++i)
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ib_cpu[i] = 0x80000000;
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r = submit(i, AMDGPU_HW_IP_UVD);
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CU_ASSERT_EQUAL(r, 0);
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/* TODO: use a real CRC32 */
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for (i = 0, sum = 0; i < dt_size; ++i)
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sum += ptr[i];
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CU_ASSERT_EQUAL(sum, 0x20345d8);
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r = amdgpu_bo_cpu_unmap(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_free(va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_free(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_cs_uvd_destroy(void)
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{
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struct amdgpu_bo_alloc_request req = {0};
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle va_handle;
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uint64_t va = 0;
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void *msg;
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int i, r;
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req.alloc_size = 4*1024;
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req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_alloc(device_handle,
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amdgpu_gpu_va_range_general,
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req.alloc_size, 1, 0, &va,
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&va_handle, 0);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
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AMDGPU_VA_OP_MAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(buf_handle, &msg);
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CU_ASSERT_EQUAL(r, 0);
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memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
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if (family_id >= AMDGPU_FAMILY_VI)
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((uint8_t*)msg)[0x10] = 7;
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r = amdgpu_bo_cpu_unmap(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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num_resources = 0;
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resources[num_resources++] = buf_handle;
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resources[num_resources++] = ib_handle;
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i = 0;
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uvd_cmd(va, 0x0, &i);
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for (; i % 16; ++i)
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ib_cpu[i] = 0x80000000;
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r = submit(i, AMDGPU_HW_IP_UVD);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_free(va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_free(buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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