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Merge Mesa 19.0.8

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This commit is contained in:
jsg 2019-07-01 08:36:47 +00:00
parent b1b22c2ae6
commit ff40cb71bf
57 changed files with 280 additions and 315 deletions
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2
lib/mesa/VERSION
View File

@ -1 +1 @@
19.0.5
19.0.8

20
lib/mesa/configure vendored
View File

@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.69 for Mesa 19.0.5.
# Generated by GNU Autoconf 2.69 for Mesa 19.0.8.
#
# Report bugs to <https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa>.
#
@ -591,8 +591,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='Mesa'
PACKAGE_TARNAME='mesa'
PACKAGE_VERSION='19.0.5'
PACKAGE_STRING='Mesa 19.0.5'
PACKAGE_VERSION='19.0.8'
PACKAGE_STRING='Mesa 19.0.8'
PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa'
PACKAGE_URL=''
@ -1895,7 +1895,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
\`configure' configures Mesa 19.0.5 to adapt to many kinds of systems.
\`configure' configures Mesa 19.0.8 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@ -1966,7 +1966,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
short | recursive ) echo "Configuration of Mesa 19.0.5:";;
short | recursive ) echo "Configuration of Mesa 19.0.8:";;
esac
cat <<\_ACEOF
@ -2352,7 +2352,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
Mesa configure 19.0.5
Mesa configure 19.0.8
generated by GNU Autoconf 2.69
Copyright (C) 2012 Free Software Foundation, Inc.
@ -3071,7 +3071,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
It was created by Mesa $as_me 19.0.5, which was
It was created by Mesa $as_me 19.0.8, which was
generated by GNU Autoconf 2.69. Invocation command line was
$ $0 $@
@ -4007,7 +4007,7 @@ fi
# Define the identity of the package.
PACKAGE='mesa'
VERSION='19.0.5'
VERSION='19.0.8'
cat >>confdefs.h <<_ACEOF
@ -30969,7 +30969,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
This file was extended by Mesa $as_me 19.0.5, which was
This file was extended by Mesa $as_me 19.0.8, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@ -31026,7 +31026,7 @@ _ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
Mesa config.status 19.0.5
Mesa config.status 19.0.8
configured by $0, generated by GNU Autoconf 2.69,
with options \\"\$ac_cs_config\\"

2
lib/mesa/include/CL/cl_d3d10.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
#ifndef __OPENCL_CL_D3D10_H
#define __OPENCL_CL_D3D10_H

2
lib/mesa/include/CL/cl_d3d11.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
#ifndef __OPENCL_CL_D3D11_H
#define __OPENCL_CL_D3D11_H

2
lib/mesa/include/CL/cl_dx9_media_sharing.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_H
#define __OPENCL_CL_DX9_MEDIA_SHARING_H

2
lib/mesa/include/CL/cl_ext.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
******************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
/* cl_ext.h contains OpenCL extensions which don't have external */
/* (OpenGL, D3D) dependencies. */

2
lib/mesa/include/CL/cl_gl_ext.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
/* cl_gl_ext.h contains vendor (non-KHR) OpenCL extensions which have */
/* OpenGL dependencies. */

2
lib/mesa/include/CL/cl_platform.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
#ifndef __CL_PLATFORM_H
#define __CL_PLATFORM_H

2
lib/mesa/include/CL/opencl.h
View File

@ -21,7 +21,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
******************************************************************************/
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
#ifndef __OPENCL_H
#define __OPENCL_H

2
lib/mesa/include/EGL/eglplatform.h
View File

@ -25,7 +25,7 @@
*/
/* Platform-specific types and definitions for egl.h
* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $
* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $
*
* Adopters may modify khrplatform.h and this file to suit their platform.
* You are encouraged to submit all modifications to the Khronos group so that

2
lib/mesa/include/GLES3/gl31.h
View File

@ -33,7 +33,7 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
** Khronos $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $
** Khronos $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $
*/
#include <GLES3/gl3platform.h>

2
lib/mesa/include/GLES3/gl3ext.h
View File

@ -1,7 +1,7 @@
#ifndef __gl3ext_h_
#define __gl3ext_h_
/* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $ */
/* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $ */
/*
* This document is licensed under the SGI Free Software B License Version

2
lib/mesa/include/KHR/khrplatform.h
View File

@ -26,7 +26,7 @@
/* Khronos platform-specific types and definitions.
*
* $Revision: 1.15 $ on $Date: 2019/05/23 05:33:19 $
* $Revision: 1.16 $ on $Date: 2019/07/01 08:36:47 $
*
* Adopters may modify this file to suit their platform. Adopters are
* encouraged to submit platform specific modifications to the Khronos

2
lib/mesa/src/amd/common/ac_llvm_build.c
View File

@ -3455,7 +3455,7 @@ ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
/* ws->result_reduce is already the correct value */
if (ws->enable_inclusive)
ws->result_inclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->src, ws->op);
ws->result_inclusive = ac_build_alu_op(ctx, ws->result_inclusive, ws->src, ws->op);
if (ws->enable_exclusive)
ws->result_exclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->extra, ws->op);
}

6
lib/mesa/src/amd/vulkan/radv_cmd_buffer.c
View File

@ -566,8 +566,8 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
for_each_bit(i, descriptors_state->valid) {
struct radv_descriptor_set *set = descriptors_state->sets[i];
data[i * 2] = (uintptr_t)set;
data[i * 2 + 1] = (uintptr_t)set >> 32;
data[i * 2] = (uint64_t)(uintptr_t)set;
data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
}
radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
@ -4736,7 +4736,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
/* Flags that only require a top-of-pipe event. */
VkPipelineStageFlags top_of_pipe_flags =

60
lib/mesa/src/amd/vulkan/radv_device.c
View File

@ -1393,40 +1393,46 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
* Note that the application heap usages are not really accurate (eg.
* in presence of shared buffers).
*/
if (vram_size) {
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM);
for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
heap_budget = vram_size -
device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
heap_usage;
switch (device->mem_type_indices[i]) {
case RADV_MEM_TYPE_VRAM:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM);
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
}
heap_budget = vram_size -
device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
heap_usage;
if (visible_vram_size) {
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM_VIS);
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM_VIS);
heap_budget = visible_vram_size -
device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
heap_usage;
heap_budget = visible_vram_size -
device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
heap_usage;
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
}
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_GTT);
if (gtt_size) {
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_GTT);
heap_budget = gtt_size -
device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
heap_usage;
heap_budget = gtt_size -
device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
heap_usage;
memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
default:
break;
}
}
/* The heapBudget and heapUsage values must be zero for array elements

5
lib/mesa/src/amd/vulkan/radv_formats.c
View File

@ -524,7 +524,7 @@ static bool radv_is_storage_image_format_supported(struct radv_physical_device *
}
}
static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
{
const struct vk_format_description *desc = vk_format_description(format);
unsigned data_format, num_format;
@ -536,7 +536,8 @@ static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
num_format = radv_translate_buffer_numformat(desc,
vk_format_get_first_non_void_channel(format));
*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
if (scaled)
*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID &&
num_format != ~0;
}

1
lib/mesa/src/amd/vulkan/radv_meta_clear.c
View File

@ -650,6 +650,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
if (radv_image_has_htile(iview->image) &&
iview->base_mip == 0 &&
iview->base_layer == 0 &&
iview->layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
radv_image_extent_compare(iview->image, &iview->extent))
return true;

36
lib/mesa/src/amd/vulkan/radv_meta_copy.c
View File

@ -189,6 +189,24 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
layout,
&pRegions[r].imageSubresource);
if (!radv_is_buffer_format_supported(img_bsurf.format, NULL)) {
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
.levelCount = 1,
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
.layerCount = pRegions[r].imageSubresource.layerCount,
});
}
img_bsurf.format = vk_format_for_size(vk_format_get_blocksize(img_bsurf.format));
img_bsurf.current_layout = VK_IMAGE_LAYOUT_GENERAL;
}
struct radv_meta_blit2d_buffer buf_bsurf = {
.bs = img_bsurf.bs,
.format = img_bsurf.format,
@ -314,6 +332,24 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
layout,
&pRegions[r].imageSubresource);
if (!radv_is_buffer_format_supported(img_info.format, NULL)) {
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
.levelCount = 1,
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
.layerCount = pRegions[r].imageSubresource.layerCount,
});
}
img_info.format = vk_format_for_size(vk_format_get_blocksize(img_info.format));
img_info.current_layout = VK_IMAGE_LAYOUT_GENERAL;
}
struct radv_meta_blit2d_buffer buf_info = {
.bs = img_info.bs,
.format = img_info.format,

9
lib/mesa/src/amd/vulkan/radv_pipeline.c
View File

@ -524,7 +524,7 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
col_format |= cf << (4 * i);
}
if (!col_format && blend->need_src_alpha & (1 << 0)) {
if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
/* When a subpass doesn't have any color attachments, write the
* alpha channel of MRT0 when alpha coverage is enabled because
* the depth attachment needs it.
@ -542,10 +542,13 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
}
}
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
/* The output for dual source blending should have the same format as
* the first output.
*/
if (blend->mrt0_is_dual_src)
col_format |= (col_format & 0xf) << 4;
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
blend->spi_shader_col_format = col_format;
}

1
lib/mesa/src/amd/vulkan/radv_private.h
View File

@ -1448,6 +1448,7 @@ uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *de
int first_non_void);
uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
int first_non_void);
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
uint32_t radv_translate_colorformat(VkFormat format);
uint32_t radv_translate_color_numformat(VkFormat format,
const struct vk_format_description *desc,

48
lib/mesa/src/amd/vulkan/radv_query.c
View File

@ -40,18 +40,6 @@
static const int pipelinestat_block_size = 11 * 8;
static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
static unsigned get_max_db(struct radv_device *device)
{
unsigned num_db = device->physical_device->rad_info.num_render_backends;
MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
/* Otherwise we need to change the query reset procedure */
assert(rb_mask == ((1ull << num_db) - 1));
return num_db;
}
static nir_ssa_def *nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)
{
return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));
@ -108,12 +96,14 @@ build_occlusion_query_shader(struct radv_device *device) {
* uint64_t dst_offset = dst_stride * global_id.x;
* bool available = true;
* for (int i = 0; i < db_count; ++i) {
* uint64_t start = src_buf[src_offset + 16 * i];
* uint64_t end = src_buf[src_offset + 16 * i + 8];
* if ((start & (1ull << 63)) && (end & (1ull << 63)))
* result += end - start;
* else
* available = false;
* if (enabled_rb_mask & (1 << i)) {
* uint64_t start = src_buf[src_offset + 16 * i];
* uint64_t end = src_buf[src_offset + 16 * i + 8];
* if ((start & (1ull << 63)) && (end & (1ull << 63)))
* result += end - start;
* else
* available = false;
* }
* }
* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
@ -139,7 +129,8 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");
unsigned db_count = get_max_db(device);
unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
unsigned db_count = device->physical_device->rad_info.num_render_backends;
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
@ -185,6 +176,16 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
nir_ssa_def *enabled_cond =
nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),
nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));
nir_if *enabled_if = nir_if_create(b.shader);
enabled_if->condition = nir_src_for_ssa(nir_i2b(&b, enabled_cond));
nir_cf_node_insert(b.cursor, &enabled_if->cf_node);
b.cursor = nir_after_cf_list(&enabled_if->then_list);
nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
load_offset = nir_iadd(&b, input_base, load_offset);
@ -1038,7 +1039,7 @@ VkResult radv_CreateQueryPool(
switch(pCreateInfo->queryType) {
case VK_QUERY_TYPE_OCCLUSION:
pool->stride = 16 * get_max_db(device);
pool->stride = 16 * device->physical_device->rad_info.num_render_backends;
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
pool->stride = pipelinestat_block_size * 2;
@ -1152,12 +1153,17 @@ VkResult radv_GetQueryPoolResults(
}
case VK_QUERY_TYPE_OCCLUSION: {
volatile uint64_t const *src64 = (volatile uint64_t const *)src;
uint32_t db_count = device->physical_device->rad_info.num_render_backends;
uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
uint64_t sample_count = 0;
int db_count = get_max_db(device);
available = 1;
for (int i = 0; i < db_count; ++i) {
uint64_t start, end;
if (!(enabled_rb_mask & (1 << i)))
continue;
do {
start = src64[2 * i];
end = src64[2 * i + 1];

5
lib/mesa/src/compiler/glsl/shader_cache.cpp
View File

@ -165,9 +165,8 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
prog->FragDataIndexBindings->iterate(create_binding_str, &buf);
ralloc_asprintf_append(&buf, "tf: %d ", prog->TransformFeedback.BufferMode);
for (unsigned int i = 0; i < prog->TransformFeedback.NumVarying; i++) {
ralloc_asprintf_append(&buf, "%s:%d ",
prog->TransformFeedback.VaryingNames[i],
prog->TransformFeedback.BufferStride[i]);
ralloc_asprintf_append(&buf, "%s ",
prog->TransformFeedback.VaryingNames[i]);
}
/* SSO has an effect on the linked program so include this when generating

31
lib/mesa/src/egl/drivers/dri2/egl_dri2.c
View File

@ -1433,6 +1433,37 @@ dri2_surf_update_fence_fd(_EGLContext *ctx,
dri2_surface_set_out_fence_fd(surf, fence_fd);
}
EGLBoolean
dri2_create_drawable(struct dri2_egl_display *dri2_dpy,
const __DRIconfig *config,
struct dri2_egl_surface *dri2_surf)
{
__DRIcreateNewDrawableFunc createNewDrawable;
void *loaderPrivate = dri2_surf;
if (dri2_dpy->image_driver)
createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
else if (dri2_dpy->dri2)
createNewDrawable = dri2_dpy->dri2->createNewDrawable;
else if (dri2_dpy->swrast)
createNewDrawable = dri2_dpy->swrast->createNewDrawable;
else
return _eglError(EGL_BAD_ALLOC, "no createNewDrawable");
/* As always gbm is a bit special.. */
#ifdef HAVE_DRM_PLATFORM
if (dri2_surf->gbm_surf)
loaderPrivate = dri2_surf->gbm_surf;
#endif
dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen,
config, loaderPrivate);
if (dri2_surf->dri_drawable == NULL)
return _eglError(EGL_BAD_ALLOC, "createNewDrawable");
return EGL_TRUE;
}
/**
* Called via eglMakeCurrent(), drv->API.MakeCurrent().
*/

5
lib/mesa/src/egl/drivers/dri2/egl_dri2.h
View File

@ -540,6 +540,11 @@ dri2_init_surface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
void
dri2_fini_surface(_EGLSurface *surf);
EGLBoolean
dri2_create_drawable(struct dri2_egl_display *dri2_dpy,
const __DRIconfig *config,
struct dri2_egl_surface *dri2_surf);
static inline uint64_t
combine_u32_into_u64(uint32_t hi, uint32_t lo)
{

12
lib/mesa/src/egl/drivers/dri2/platform_android.c
View File

@ -335,7 +335,6 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
_EGLConfig *conf, void *native_window,
const EGLint *attrib_list)
{
__DRIcreateNewDrawableFunc createNewDrawable;
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_config *dri2_conf = dri2_egl_config(conf);
struct dri2_egl_surface *dri2_surf;
@ -379,17 +378,8 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
goto cleanup_surface;
}
if (dri2_dpy->image_driver)
createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
else
createNewDrawable = dri2_dpy->dri2->createNewDrawable;
dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen, config,
dri2_surf);
if (dri2_surf->dri_drawable == NULL) {
_eglError(EGL_BAD_ALLOC, "createNewDrawable");
if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
goto cleanup_surface;
}
if (window) {
window->common.incRef(&window->common);

17
lib/mesa/src/egl/drivers/dri2/platform_drm.c
View File

@ -171,23 +171,8 @@ dri2_drm_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
dri2_surf->base.Height = surf->base.height;
surf->dri_private = dri2_surf;
if (dri2_dpy->dri2) {
dri2_surf->dri_drawable =
dri2_dpy->dri2->createNewDrawable(dri2_dpy->dri_screen, config,
dri2_surf->gbm_surf);
} else {
assert(dri2_dpy->swrast != NULL);
dri2_surf->dri_drawable =
dri2_dpy->swrast->createNewDrawable(dri2_dpy->dri_screen, config,
dri2_surf->gbm_surf);
}
if (dri2_surf->dri_drawable == NULL) {
_eglError(EGL_BAD_ALLOC, "createNewDrawable()");
if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
goto cleanup_surf;
}
return &dri2_surf->base;

7
lib/mesa/src/egl/drivers/dri2/platform_surfaceless.c
View File

@ -135,13 +135,8 @@ dri2_surfaceless_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
goto cleanup_surface;
}
dri2_surf->dri_drawable =
dri2_dpy->image_driver->createNewDrawable(dri2_dpy->dri_screen, config,
dri2_surf);
if (dri2_surf->dri_drawable == NULL) {
_eglError(EGL_BAD_ALLOC, "image->createNewDrawable");
if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
goto cleanup_surface;
}
if (conf->RedSize == 5)
dri2_surf->visual = __DRI_IMAGE_FORMAT_RGB565;

14
lib/mesa/src/egl/drivers/dri2/platform_wayland.c
View File

@ -272,7 +272,6 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf, void *native_window,
const EGLint *attrib_list)
{
__DRIcreateNewDrawableFunc createNewDrawable;
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_config *dri2_conf = dri2_egl_config(conf);
struct wl_egl_window *window = native_window;
@ -349,19 +348,8 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
if (dri2_dpy->flush)
dri2_surf->wl_win->resize_callback = resize_callback;
if (dri2_dpy->image_driver)
createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
else if (dri2_dpy->dri2)
createNewDrawable = dri2_dpy->dri2->createNewDrawable;
else
createNewDrawable = dri2_dpy->swrast->createNewDrawable;
dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen, config,
dri2_surf);
if (dri2_surf->dri_drawable == NULL) {
_eglError(EGL_BAD_ALLOC, "createNewDrawable");
if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
goto cleanup_surf_wrapper;
}
dri2_surf->base.SwapInterval = dri2_dpy->default_swap_interval;

17
lib/mesa/src/egl/drivers/dri2/platform_x11.c
View File

@ -261,7 +261,7 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
(void) drv;
dri2_surf = malloc(sizeof *dri2_surf);
dri2_surf = calloc(1, sizeof *dri2_surf);
if (!dri2_surf) {
_eglError(EGL_BAD_ALLOC, "dri2_create_surface");
return NULL;
@ -289,21 +289,8 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
goto cleanup_pixmap;
}
if (dri2_dpy->dri2) {
dri2_surf->dri_drawable =
dri2_dpy->dri2->createNewDrawable(dri2_dpy->dri_screen, config,
dri2_surf);
} else {
assert(dri2_dpy->swrast);
dri2_surf->dri_drawable =
dri2_dpy->swrast->createNewDrawable(dri2_dpy->dri_screen, config,
dri2_surf);
}
if (dri2_surf->dri_drawable == NULL) {
_eglError(EGL_BAD_ALLOC, "dri2->createNewDrawable");
if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
goto cleanup_pixmap;
}
if (type != EGL_PBUFFER_BIT) {
cookie = xcb_get_geometry (dri2_dpy->conn, dri2_surf->drawable);

3
lib/mesa/src/gallium/auxiliary/util/u_blitter.c
View File

@ -2059,7 +2059,8 @@ void util_blitter_generate_mipmap(struct blitter_context *blitter,
target = PIPE_TEXTURE_2D_ARRAY;
assert(tex->nr_samples <= 1);
assert(!util_format_has_stencil(desc));
/* Disallow stencil formats without depth. */
assert(!util_format_has_stencil(desc) || util_format_has_depth(desc));
is_depth = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS;

4
lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.c
View File

@ -592,12 +592,12 @@ etna_emit_state(struct etna_context *ctx)
static const uint32_t uniform_dirty_bits =
ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;
if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
etna_uniforms_write(
ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX],
ctx->shader_state.VS_UNIFORMS, &ctx->shader_state.vs_uniforms_size);
if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
etna_uniforms_write(
ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT],
ctx->shader_state.PS_UNIFORMS, &ctx->shader_state.ps_uniforms_size);

1
lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c
View File

@ -610,6 +610,7 @@ etna_resource_get_handle(struct pipe_screen *pscreen,
rsc = etna_resource(rsc->external);
handle->stride = rsc->levels[0].stride;
handle->offset = rsc->levels[0].offset;
handle->modifier = layout_to_modifier(rsc->layout);
if (handle->type == WINSYS_HANDLE_TYPE_SHARED) {

8
lib/mesa/src/gallium/drivers/svga/svga_draw.c
View File

@ -619,11 +619,11 @@ draw_vgpu10(struct svga_hwtnl *hwtnl,
vbuffer_attrs[i].sid = 0;
}
/* If we haven't yet emitted a drawing command or if any
* vertex buffer state is changing, issue that state now.
/* If any of the vertex buffer state has changed, issue
* the SetVertexBuffers command. Otherwise, we will just
* need to rebind the resources.
*/
if (((hwtnl->cmd.swc->hints & SVGA_HINT_FLAG_CAN_PRE_FLUSH) == 0) ||
vbuf_count != svga->state.hw_draw.num_vbuffers ||
if (vbuf_count != svga->state.hw_draw.num_vbuffers ||
!vertex_buffers_equal(vbuf_count,
vbuffer_attrs,
vbuffers,

65
lib/mesa/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
View File

@ -565,68 +565,3 @@ using Vec4 = typename SIMD_T::Vec4;
template <typename SIMD_T>
using Mask = typename SIMD_T::Mask;
template <typename SIMD_T>
struct SIMDVecEqual
{
INLINE bool operator()(Integer<SIMD_T> a, Integer<SIMD_T> b) const
{
Integer<SIMD_T> c = SIMD_T::xor_si(a, b);
return SIMD_T::testz_si(c, c);
}
INLINE bool operator()(Float<SIMD_T> a, Float<SIMD_T> b) const
{
return this->operator()(SIMD_T::castps_si(a), SIMD_T::castps_si(b));
}
INLINE bool operator()(Double<SIMD_T> a, Double<SIMD_T> b) const
{
return this->operator()(SIMD_T::castpd_si(a), SIMD_T::castpd_si(b));
}
};
template <typename SIMD_T>
struct SIMDVecHash
{
INLINE uint32_t operator()(Integer<SIMD_T> val) const
{
#if defined(_WIN64) || !defined(_WIN32) // assume non-Windows is always 64-bit
static_assert(sizeof(void*) == 8, "This path only meant for 64-bit code");
uint64_t crc32 = 0;
const uint64_t* pData = reinterpret_cast<const uint64_t*>(&val);
static const uint32_t loopIterations = sizeof(val) / sizeof(void*);
static_assert(loopIterations * sizeof(void*) == sizeof(val), "bad vector size");
for (uint32_t i = 0; i < loopIterations; ++i)
{
crc32 = _mm_crc32_u64(crc32, pData[i]);
}
return static_cast<uint32_t>(crc32);
#else
static_assert(sizeof(void*) == 4, "This path only meant for 32-bit code");
uint32_t crc32 = 0;
const uint32_t* pData = reinterpret_cast<const uint32_t*>(&val);
static const uint32_t loopIterations = sizeof(val) / sizeof(void*);
static_assert(loopIterations * sizeof(void*) == sizeof(val), "bad vector size");
for (uint32_t i = 0; i < loopIterations; ++i)
{
crc32 = _mm_crc32_u32(crc32, pData[i]);
}
return crc32;
#endif
};
INLINE uint32_t operator()(Float<SIMD_T> val) const
{
return operator()(SIMD_T::castps_si(val));
};
INLINE uint32_t operator()(Double<SIMD_T> val) const
{
return operator()(SIMD_T::castpd_si(val));
}
};

7
lib/mesa/src/gallium/drivers/swr/swr_screen.cpp
View File

@ -36,6 +36,7 @@
#include "util/u_cpu_detect.h"
#include "util/u_format_s3tc.h"
#include "util/u_string.h"
#include "util/u_screen.h"
#include "state_tracker/sw_winsys.h"
@ -387,11 +388,9 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
return (int)(system_memory >> 20);
}
default:
return u_pipe_screen_get_param_defaults(screen, param);
}
/* should only get here on unhandled cases */
debug_printf("Unexpected PIPE_CAP %d query\n", param);
return 0;
}
static int

3
lib/mesa/src/gallium/drivers/virgl/virgl_screen.c
View File

@ -347,7 +347,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
return vscreen->vws->supports_fences;
case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL;
return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
(vscreen->caps.caps.v2.host_feature_check_version < 1);
default:
return u_pipe_screen_get_param_defaults(screen, param);
}

25
lib/mesa/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
View File

@ -210,6 +210,10 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
SVGA3dMSQualityLevel qualityLevel,
struct vmw_region **p_region)
{
union {
union drm_vmw_gb_surface_create_ext_arg ext_arg;
union drm_vmw_gb_surface_create_arg arg;
} s_arg;
struct drm_vmw_gb_surface_create_rep *rep;
struct vmw_region *region = NULL;
int ret;
@ -222,12 +226,11 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
return SVGA3D_INVALID_ID;
}
if (vws->ioctl.have_drm_2_15) {
union drm_vmw_gb_surface_create_ext_arg s_arg;
struct drm_vmw_gb_surface_create_ext_req *req = &s_arg.req;
rep = &s_arg.rep;
memset(&s_arg, 0, sizeof(s_arg));
memset(&s_arg, 0, sizeof(s_arg));
if (vws->ioctl.have_drm_2_15) {
struct drm_vmw_gb_surface_create_ext_req *req = &s_arg.ext_arg.req;
rep = &s_arg.ext_arg.rep;
req->version = drm_vmw_gb_surface_v1;
req->multisample_pattern = multisamplePattern;
@ -264,17 +267,15 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
buffer_handle : SVGA3D_INVALID_ID;
ret = drmCommandWriteRead(vws->ioctl.drm_fd,
DRM_VMW_GB_SURFACE_CREATE_EXT, &s_arg,
sizeof(s_arg));
DRM_VMW_GB_SURFACE_CREATE_EXT, &s_arg.ext_arg,
sizeof(s_arg.ext_arg));
if (ret)
goto out_fail_create;
} else {
union drm_vmw_gb_surface_create_arg s_arg;
struct drm_vmw_gb_surface_create_req *req = &s_arg.req;
rep = &s_arg.rep;
struct drm_vmw_gb_surface_create_req *req = &s_arg.arg.req;
rep = &s_arg.arg.rep;
memset(&s_arg, 0, sizeof(s_arg));
req->svga3d_flags = (uint32_t) flags;
req->format = (uint32_t) format;
@ -305,7 +306,7 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
buffer_handle : SVGA3D_INVALID_ID;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE,
&s_arg, sizeof(s_arg));
&s_arg.arg, sizeof(s_arg.arg));
if (ret)
goto out_fail_create;

2
lib/mesa/src/getopt/getopt.h
View File

@ -1,4 +1,4 @@
/* $OpenBSD: getopt.h,v 1.15 2019/05/23 05:33:28 jsg Exp $ */
/* $OpenBSD: getopt.h,v 1.16 2019/07/01 08:36:48 jsg Exp $ */
/* $NetBSD: getopt.h,v 1.4 2000/07/07 10:43:54 ad Exp $ */
/*-

2
lib/mesa/src/getopt/getopt_long.c
View File

@ -1,4 +1,4 @@
/* $OpenBSD: getopt_long.c,v 1.15 2019/05/23 05:33:28 jsg Exp $ */
/* $OpenBSD: getopt_long.c,v 1.16 2019/07/01 08:36:48 jsg Exp $ */
/* $NetBSD: getopt_long.c,v 1.15 2002/01/31 22:43:40 tv Exp $ */
/*

6
lib/mesa/src/intel/compiler/brw_eu_emit.c
View File

@ -696,9 +696,9 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
gen7_convert_mrf_to_grf(p, &dest);
assert(dest.nr < 128);
assert(src0.file != BRW_IMMEDIATE_VALUE || src0.nr < 128);
assert(src1.file != BRW_IMMEDIATE_VALUE || src1.nr < 128);
assert(src2.file != BRW_IMMEDIATE_VALUE || src2.nr < 128);
assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < 128);
assert(src1.file != BRW_IMMEDIATE_VALUE && src1.nr < 128);
assert(src2.file == BRW_IMMEDIATE_VALUE || src2.nr < 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);

2
lib/mesa/src/intel/vulkan/anv_image.c
View File

@ -751,7 +751,7 @@ resolve_ahw_image(struct anv_device *device,
vk_format,
VK_IMAGE_ASPECT_COLOR_BIT,
vk_tiling);
assert(format != ISL_FORMAT_UNSUPPORTED);
assert(isl_fmt != ISL_FORMAT_UNSUPPORTED);
/* Handle RGB(X)->RGBA fallback. */
switch (desc.format) {

37
lib/mesa/src/intel/vulkan/genX_cmd_buffer.c
View File

@ -122,6 +122,23 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
sba.IndirectObjectBufferSizeModifyEnable = true;
sba.InstructionBufferSize = 0xfffff;
sba.InstructionBuffersizeModifyEnable = true;
# else
/* On gen7, we have upper bounds instead. According to the docs,
* setting an upper bound of zero means that no bounds checking is
* performed so, in theory, we should be able to leave them zero.
* However, border color is broken and the GPU bounds-checks anyway.
* To avoid this and other potential problems, we may as well set it
* for everything.
*/
sba.GeneralStateAccessUpperBound =
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
sba.GeneralStateAccessUpperBoundModifyEnable = true;
sba.DynamicStateAccessUpperBound =
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
sba.DynamicStateAccessUpperBoundModifyEnable = true;
sba.InstructionAccessUpperBound =
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
sba.InstructionAccessUpperBoundModifyEnable = true;
# endif
# if (GEN_GEN >= 9)
sba.BindlessSurfaceStateBaseAddress = (struct anv_address) { NULL, 0 };
@ -828,27 +845,21 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
set_image_fast_clear_state(cmd_buffer, image, aspect,
ANV_FAST_CLEAR_NONE);
/* The fast clear value dword(s) will be copied into a surface state object.
* Ensure that the restrictions of the fields in the dword(s) are followed.
*
* CCS buffers on SKL+ can have any value set for the clear colors.
*/
if (image->samples == 1 && GEN_GEN >= 9)
return;
/* Other combinations of auxiliary buffers and platforms require specific
* values in the clear value dword(s).
/* Initialize the struct fields that are accessed for fast-clears so that
* the HW restrictions on the field values are satisfied.
*/
struct anv_address addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
if (GEN_GEN >= 9) {
for (unsigned i = 0; i < 4; i++) {
const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
const unsigned num_dwords = GEN_GEN >= 10 ?
isl_dev->ss.clear_color_state_size / 4 :
isl_dev->ss.clear_value_size / 4;
for (unsigned i = 0; i < num_dwords; i++) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = addr;
sdi.Address.offset += i * 4;
/* MCS buffers on SKL+ can only have 1/0 clear colors. */
assert(image->samples > 1);
sdi.ImmediateData = 0;
}
}

8
lib/mesa/src/mapi/glapi/gen/gl_XML.py
View File

@ -49,7 +49,7 @@ def parse_GL_API( file_name, factory = None ):
# that are not part of the ABI.
for func in api.functionIterateByCategory():
if func.assign_offset:
if func.assign_offset and func.offset < 0:
func.offset = api.next_offset;
api.next_offset += 1
@ -683,8 +683,12 @@ class gl_function( gl_item ):
if name in static_data.offsets and static_data.offsets[name] <= static_data.MAX_OFFSETS:
self.offset = static_data.offsets[name]
elif name in static_data.offsets and static_data.offsets[name] > static_data.MAX_OFFSETS:
self.offset = static_data.offsets[name]
self.assign_offset = True
else:
self.offset = -1
if self.exec_flavor != "skip":
raise RuntimeError("Entry-point %s is missing offset in static_data.py. Add one at the bottom of the list." % (name))
self.assign_offset = self.exec_flavor != "skip" or name in static_data.unused_functions
if not self.name:

2
lib/mesa/src/mapi/glapi/gen/static_data.py
View File

@ -29,7 +29,7 @@ MAX_OFFSETS = 407
"""Table of functions that have ABI-mandated offsets in the dispatch table.
The first MAX_OFFSETS entries are required by indirect GLX. The rest are
required to preserve the glapi <> drivers ABI. This is to be addressed shortly.
required to preserve the glapi <> GL/GLES ABI. This is to be addressed shortly.
This list will never change."""
offsets = {

22
lib/mesa/src/mesa/drivers/dri/i965/brw_performance_query.c
View File

@ -1848,23 +1848,10 @@ static bool
kernel_has_dynamic_config_support(struct brw_context *brw)
{
__DRIscreen *screen = brw->screen->driScrnPriv;
uint64_t invalid_config_id = UINT64_MAX;
hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
struct brw_perf_query_info *query = entry->data;
char config_path[280];
uint64_t config_id;
snprintf(config_path, sizeof(config_path), "%s/metrics/%s/id",
brw->perfquery.sysfs_dev_dir, query->guid);
/* Look for the test config, which we know we can't replace. */
if (read_file_uint64(config_path, &config_id) && config_id == 1) {
return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
&config_id) < 0 && errno == ENOENT;
}
}
return false;
return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
&invalid_config_id) < 0 && errno == ENOENT;
}
static void
@ -1990,8 +1977,7 @@ compute_topology_builtins(struct brw_context *brw)
for (int i = 0; i < sizeof(devinfo->eu_masks); i++)
brw->perfquery.sys_vars.n_eus += util_bitcount(devinfo->eu_masks[i]);
brw->perfquery.sys_vars.eu_threads_count =
brw->perfquery.sys_vars.n_eus * devinfo->num_thread_per_eu;
brw->perfquery.sys_vars.eu_threads_count = devinfo->num_thread_per_eu;
/* At the moment the subslice mask builtin has groups of 3bits for each
* slice.

3
lib/mesa/src/mesa/drivers/dri/i965/intel_screen.c
View File

@ -1363,7 +1363,8 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
for (i = 0; i < num_mods && i < max; i++) {
if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
external_only[i] = GL_TRUE;
}
else {

4
lib/mesa/src/mesa/main/context.c
View File

@ -1760,10 +1760,6 @@ _mesa_make_current( struct gl_context *newCtx,
check_init_viewport(newCtx, drawBuffer->Width, drawBuffer->Height);
}
else {
_mesa_reference_framebuffer(&newCtx->WinSysDrawBuffer, NULL);
_mesa_reference_framebuffer(&newCtx->WinSysReadBuffer, NULL);
}
if (newCtx->FirstTimeCurrent) {
handle_first_current(newCtx);

39
lib/mesa/src/mesa/program/ir_to_mesa.cpp
View File

@ -2511,8 +2511,7 @@ _mesa_generate_parameters_list_for_uniforms(struct gl_context *ctx,
void
_mesa_associate_uniform_storage(struct gl_context *ctx,
struct gl_shader_program *shader_program,
struct gl_program *prog,
bool propagate_to_storage)
struct gl_program *prog)
{
struct gl_program_parameter_list *params = prog->Parameters;
gl_shader_stage shader_type = prog->info.stage;
@ -2638,26 +2637,24 @@ _mesa_associate_uniform_storage(struct gl_context *ctx,
* data from the linker's backing store. This will cause values from
* initializers in the source code to be copied over.
*/
if (propagate_to_storage) {
unsigned array_elements = MAX2(1, storage->array_elements);
if (ctx->Const.PackedDriverUniformStorage && !prog->is_arb_asm &&
(storage->is_bindless || !storage->type->contains_opaque())) {
const int dmul = storage->type->is_64bit() ? 2 : 1;
const unsigned components =
storage->type->vector_elements *
storage->type->matrix_columns;
unsigned array_elements = MAX2(1, storage->array_elements);
if (ctx->Const.PackedDriverUniformStorage && !prog->is_arb_asm &&
(storage->is_bindless || !storage->type->contains_opaque())) {
const int dmul = storage->type->is_64bit() ? 2 : 1;
const unsigned components =
storage->type->vector_elements *
storage->type->matrix_columns;
for (unsigned s = 0; s < storage->num_driver_storage; s++) {
gl_constant_value *uni_storage = (gl_constant_value *)
storage->driver_storage[s].data;
memcpy(uni_storage, storage->storage,
sizeof(storage->storage[0]) * components *
array_elements * dmul);
}
} else {
_mesa_propagate_uniforms_to_driver_storage(storage, 0,
array_elements);
for (unsigned s = 0; s < storage->num_driver_storage; s++) {
gl_constant_value *uni_storage = (gl_constant_value *)
storage->driver_storage[s].data;
memcpy(uni_storage, storage->storage,
sizeof(storage->storage[0]) * components *
array_elements * dmul);
}
} else {
_mesa_propagate_uniforms_to_driver_storage(storage, 0,
array_elements);
}
last_location = location;
@ -3016,7 +3013,7 @@ get_mesa_program(struct gl_context *ctx,
* prog->ParameterValues to get reallocated (e.g., anything that adds a
* program constant) has to happen before creating this linkage.
*/
_mesa_associate_uniform_storage(ctx, shader_program, prog, true);
_mesa_associate_uniform_storage(ctx, shader_program, prog);
if (!shader_program->data->LinkStatus) {
goto fail_exit;
}

3
lib/mesa/src/mesa/program/ir_to_mesa.h
View File

@ -50,8 +50,7 @@ _mesa_generate_parameters_list_for_uniforms(struct gl_context *ctx,
void
_mesa_associate_uniform_storage(struct gl_context *ctx,
struct gl_shader_program *shader_program,
struct gl_program *prog,
bool propagate_to_storage);
struct gl_program *prog);
#ifdef __cplusplus
}

6
lib/mesa/src/mesa/state_tracker/st_cb_fbo.c
View File

@ -414,9 +414,15 @@ st_new_renderbuffer_fb(enum pipe_format format, unsigned samples, boolean sw)
case PIPE_FORMAT_R32G32B32A32_FLOAT:
strb->Base.InternalFormat = GL_RGBA32F;
break;
case PIPE_FORMAT_R32G32B32X32_FLOAT:
strb->Base.InternalFormat = GL_RGB32F;
break;
case PIPE_FORMAT_R16G16B16A16_FLOAT:
strb->Base.InternalFormat = GL_RGBA16F;
break;
case PIPE_FORMAT_R16G16B16X16_FLOAT:
strb->Base.InternalFormat = GL_RGB16F;
break;
default:
_mesa_problem(NULL,
"Unexpected format %s in st_new_renderbuffer_fb",

2
lib/mesa/src/mesa/state_tracker/st_context.c
View File

@ -479,7 +479,7 @@ st_create_context_priv(struct gl_context *ctx, struct pipe_context *pipe,
PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET));
/* GL limits and extensions */
st_init_limits(pipe->screen, &ctx->Const, &ctx->Extensions, ctx->API);
st_init_limits(pipe->screen, &ctx->Const, &ctx->Extensions);
st_init_extensions(pipe->screen, &ctx->Const,
&ctx->Extensions, &st->options, ctx->API);

13
lib/mesa/src/mesa/state_tracker/st_extensions.c
View File

@ -76,8 +76,7 @@ static int _clamp(int a, int min, int max)
* Note that we have to limit/clamp against Mesa's internal limits too.
*/
void st_init_limits(struct pipe_screen *screen,
struct gl_constants *c, struct gl_extensions *extensions,
gl_api api)
struct gl_constants *c, struct gl_extensions *extensions)
{
int supported_irs;
unsigned sh;
@ -440,14 +439,8 @@ void st_init_limits(struct pipe_screen *screen,
c->GLSLFrontFacingIsSysVal =
screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
/* GL_ARB_get_program_binary
*
* The QT framework has a bug in their shader program cache, which is built
* on GL_ARB_get_program_binary. In an effort to allow them to fix the bug
* we don't enable more than 1 binary format for compatibility profiles.
*/
if (api != API_OPENGL_COMPAT &&
screen->get_disk_shader_cache && screen->get_disk_shader_cache(screen))
/* GL_ARB_get_program_binary */
if (screen->get_disk_shader_cache && screen->get_disk_shader_cache(screen))
c->NumProgramBinaryFormats = 1;
c->MaxAtomicBufferBindings =

2
lib/mesa/src/mesa/state_tracker/st_glsl_to_nir.cpp
View File

@ -456,7 +456,7 @@ st_glsl_to_nir_post_opts(struct st_context *st, struct gl_program *prog,
* prog->ParameterValues to get reallocated (e.g., anything that adds a
* program constant) has to happen before creating this linkage.
*/
_mesa_associate_uniform_storage(st->ctx, shader_program, prog, true);
_mesa_associate_uniform_storage(st->ctx, shader_program, prog);
st_set_prog_affected_state_flags(prog);

2
lib/mesa/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
View File

@ -7201,7 +7201,7 @@ get_mesa_program_tgsi(struct gl_context *ctx,
* prog->ParameterValues to get reallocated (e.g., anything that adds a
* program constant) has to happen before creating this linkage.
*/
_mesa_associate_uniform_storage(ctx, shader_program, prog, true);
_mesa_associate_uniform_storage(ctx, shader_program, prog);
if (!shader_program->data->LinkStatus) {
free_glsl_to_tgsi_visitor(v);
_mesa_reference_program(ctx, &shader->Program, NULL);

2
lib/mesa/src/mesa/state_tracker/st_manager.c
View File

@ -1259,7 +1259,7 @@ get_version(struct pipe_screen *screen,
_mesa_init_constants(&consts, api);
_mesa_init_extensions(&extensions);
st_init_limits(screen, &consts, &extensions, api);
st_init_limits(screen, &consts, &extensions);
st_init_extensions(screen, &consts, &extensions, options, api);
return _mesa_get_version(&extensions, &consts, api);

2
lib/mesa/src/mesa/state_tracker/st_shader_cache.c
View File

@ -365,7 +365,7 @@ st_deserialise_ir_program(struct gl_context *ctx,
}
st_set_prog_affected_state_flags(prog);
_mesa_associate_uniform_storage(ctx, shProg, prog, false);
_mesa_associate_uniform_storage(ctx, shProg, prog);
/* Create Gallium shaders now instead of on demand. */
if (ST_DEBUG & DEBUG_PRECOMPILE ||