Pull in a patch from X.Org-current to let X11 run on AMD Geode LX
CPUs in basic VESA mode: X86EMU: handle CPUID instruction Starting X on an AMD Geode LX system such as an Alix board with VGA connector, the Xorg driver attempts to issue INT 10/0 to go to mode 3 (VGA). The emulator, running the BIOS code, would then spit out: c000:0282: A2 ILLEGAL EXTENDED X86 OPCODE! The opcode was 0F A2, or CPUID; it was not implemented in the emulator. With this patch it handles the CPUID instruction in one of two ways: 1) if ran on __i386__ or __x86_64__ then it calls the CPUID instruction directly. 2) if ran elsewhere it returns a canned 486dx4 set of values for function 1. Tested with & ok matthieu
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@ -327,6 +327,20 @@ static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
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END_OF_INSTR();
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}
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/****************************************************************************
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REMARKS: CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output
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Handles opcode 0x0f,0xa2
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****************************************************************************/
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static void x86emuOp2_cpuid(u8 X86EMU_UNUSED(op2))
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{
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START_OF_INSTR();
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DECODE_PRINTF("CPUID\n");
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TRACE_AND_STEP();
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cpuid();
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DECODE_CLEAR_SEGOVR();
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END_OF_INSTR();
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}
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/****************************************************************************
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REMARKS:
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Handles opcode 0x0f,0xa3
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@ -2734,7 +2748,7 @@ void (*x86emu_optab2[256])(u8) =
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/* 0xa0 */ x86emuOp2_push_FS,
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/* 0xa1 */ x86emuOp2_pop_FS,
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/* 0xa2 */ x86emuOp2_illegal_op,
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/* 0xa2 */ x86emuOp2_cpuid,
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/* 0xa3 */ x86emuOp2_bt_R,
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/* 0xa4 */ x86emuOp2_shld_IMM,
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/* 0xa5 */ x86emuOp2_shld_CL,
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@ -102,6 +102,12 @@
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#define PRIM_OPS_NO_REDEFINE_ASM
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#include "x86emu/x86emui.h"
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#if defined(__GNUC__)
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# if defined (__i386__) || defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__)
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# include "x86emu/prim_x86_gcc.h"
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# endif
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#endif
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/*------------------------- Global Variables ------------------------------*/
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static u32 x86emu_parity_tab[8] =
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@ -2654,3 +2660,63 @@ DB( if (CHECK_SP_ACCESS())
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return res;
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}
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/****************************************************************************
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REMARKS:
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CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output
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****************************************************************************/
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void cpuid (void)
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{
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u32 feature = M.x86.R_EAX;
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#ifdef X86EMU_HAS_HW_CPUID
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/* If the platform allows it, we will base our values on the real
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* results from the CPUID instruction. We limit support to the
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* first two features, and the results of those are sanitized.
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*/
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if (feature <= 1)
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hw_cpuid(&M.x86.R_EAX, &M.x86.R_EBX, &M.x86.R_ECX, &M.x86.R_EDX);
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#endif
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switch (feature) {
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case 0:
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/* Regardless if we have real data from the hardware, the emulator
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* will only support upto feature 1, which we set in register EAX.
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* Registers EBX:EDX:ECX contain a string identifying the CPU.
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*/
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M.x86.R_EAX = 1;
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#ifndef X86EMU_HAS_HW_CPUID
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/* EBX:EDX:ECX = "GenuineIntel" */
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M.x86.R_EBX = 0x756e6547;
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M.x86.R_EDX = 0x49656e69;
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M.x86.R_ECX = 0x6c65746e;
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#endif
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break;
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case 1:
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#ifndef X86EMU_HAS_HW_CPUID
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/* If we don't have x86 compatible hardware, we return values from an
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* Intel 486dx4; which was one of the first processors to have CPUID.
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*/
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M.x86.R_EAX = 0x00000480;
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M.x86.R_EBX = 0x00000000;
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M.x86.R_ECX = 0x00000000;
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M.x86.R_EDX = 0x00000002; /* VME */
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#else
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/* In the case that we have hardware CPUID instruction, we make sure
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* that the features reported are limited to TSC and VME.
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*/
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M.x86.R_EDX &= 0x00000012;
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#endif
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break;
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default:
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/* Finally, we don't support any additional features. Most CPUs
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* return all zeros when queried for invalid or unsupported feature
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* numbers.
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*/
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M.x86.R_EAX = 0;
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M.x86.R_EBX = 0;
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M.x86.R_ECX = 0;
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M.x86.R_EDX = 0;
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break;
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}
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}
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@ -133,6 +133,7 @@ void push_word (u16 w);
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void push_long (u32 w);
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u16 pop_word (void);
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u32 pop_long (void);
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void cpuid (void);
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#ifdef __cplusplus
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} /* End of "C" linkage for C++ */
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79
xserver/hw/xfree86/x86emu/x86emu/prim_x86_gcc.h
Normal file
79
xserver/hw/xfree86/x86emu/x86emu/prim_x86_gcc.h
Normal file
@ -0,0 +1,79 @@
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/****************************************************************************
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*
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* Inline helpers for x86emu
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*
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* Copyright (C) 2008 Bart Trojanowski, Symbio Technologies, LLC
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*
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* ========================================================================
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*
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* Permission to use, copy, modify, distribute, and sell this software and
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* its documentation for any purpose is hereby granted without fee,
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* provided that the above copyright notice appear in all copies and that
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* both that copyright notice and this permission notice appear in
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* supporting documentation, and that the name of the authors not be used
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* in advertising or publicity pertaining to distribution of the software
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* without specific, written prior permission. The authors makes no
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* representations about the suitability of this software for any purpose.
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* It is provided "as is" without express or implied warranty.
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*
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* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
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* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*
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* ========================================================================
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*
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* Language: GNU C
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* Environment: GCC on i386 or x86-64
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* Developer: Bart Trojanowski
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*
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* Description: This file defines a few x86 macros that can be used by the
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* emulator to execute native instructions.
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*
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* For PIC vs non-PIC code refer to:
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* http://sam.zoy.org/blog/2007-04-13-shlib-with-non-pic-code-have-inline-assembly-and-pic-mix-well
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*
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****************************************************************************/
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#ifndef __X86EMU_PRIM_X86_GCC_H
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#define __X86EMU_PRIM_X86_GCC_H
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#include "x86emu/types.h"
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#if !defined(__GNUC__) || !(defined (__i386__) || defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__))
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#error This file is intended to be used by gcc on i386 or x86-64 system
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#endif
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#if defined(__PIC__) && defined(__i386__)
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#define X86EMU_HAS_HW_CPUID 1
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static inline void hw_cpuid (u32 *a, u32 *b, u32 *c, u32 *d)
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{
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__asm__ __volatile__ ("pushl %%ebx \n\t"
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"cpuid \n\t"
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"movl %%ebx, %1 \n\t"
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"popl %%ebx \n\t"
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: "=a" (*a), "=r" (*b),
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"=c" (*c), "=d" (*d)
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: "a" (*a), "c" (*c)
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: "cc");
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}
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#else // ! (__PIC__ && __i386__)
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#define x86EMU_HAS_HW_CPUID 1
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static inline void hw_cpuid (u32 *a, u32 *b, u32 *c, u32 *d)
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{
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__asm__ __volatile__ ("cpuid"
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: "=a" (*a), "=b" (*b),
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"=c" (*c), "=d" (*d)
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: "a" (*a), "c" (*c)
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: "cc");
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}
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#endif // __PIC__ && __i386__
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#endif // __X86EMU_PRIM_X86_GCC_H
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