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fix some files cvs got wrong when checking out 13.0.6

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This commit is contained in:
jsg 2018-01-08 06:41:59 +00:00
parent 646d14d2d3
commit bc2a4df05f
4 changed files with 50 additions and 110 deletions
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37
lib/mesa/src/mesa/drivers/dri/i965/gen7_gs_state.c
View File

@ -29,13 +29,18 @@
static void
upload_gs_state(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct brw_stage_state *stage_state = &brw->gs.base;
const int max_threads_shift = brw->is_haswell ?
HSW_GS_MAX_THREADS_SHIFT : GEN6_GS_MAX_THREADS_SHIFT;
/* BRW_NEW_GEOMETRY_PROGRAM */
bool active = brw->geometry_program;
/* BRW_NEW_GS_PROG_DATA */
const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
const struct brw_vue_prog_data *vue_prog_data =
brw_vue_prog_data(stage_state->prog_data);
const struct brw_gs_prog_data *gs_prog_data =
brw_gs_prog_data(stage_state->prog_data);
/**
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
@ -58,26 +63,25 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_GS_SAMPLER_COUNT_SHIFT) |
((brw->gs.prog_data->base.base.binding_table.size_bytes / 4) <<
((prog_data->binding_table.size_bytes / 4) <<
GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (brw->gs.prog_data->base.base.total_scratch) {
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(brw->gs.prog_data->base.base.total_scratch) - 11);
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
}
uint32_t dw4 =
((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
((gs_prog_data->output_vertex_size_hwords * 2 - 1) <<
GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
(brw->gs.prog_data->output_topology <<
GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
(prog_data->urb_read_length <<
(gs_prog_data->output_topology << GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
(vue_prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
(prog_data->base.dispatch_grf_start_reg <<
(prog_data->dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT);
/* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
@ -107,24 +111,24 @@ upload_gs_state(struct brw_context *brw)
* Bridge this will get the order close to correct but not perfect.
*/
uint32_t dw5 =
((brw->max_gs_threads - 1) << max_threads_shift) |
(brw->gs.prog_data->control_data_header_size_hwords <<
((devinfo->max_gs_threads - 1) << max_threads_shift) |
(gs_prog_data->control_data_header_size_hwords <<
GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
((brw->gs.prog_data->invocations - 1) <<
((gs_prog_data->invocations - 1) <<
GEN7_GS_INSTANCE_CONTROL_SHIFT) |
SET_FIELD(prog_data->dispatch_mode, GEN7_GS_DISPATCH_MODE) |
SET_FIELD(vue_prog_data->dispatch_mode, GEN7_GS_DISPATCH_MODE) |
GEN6_GS_STATISTICS_ENABLE |
(brw->gs.prog_data->include_primitive_id ?
(gs_prog_data->include_primitive_id ?
GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
GEN7_GS_REORDER_TRAILING |
GEN7_GS_ENABLE;
uint32_t dw6 = 0;
if (brw->is_haswell) {
dw6 |= brw->gs.prog_data->control_data_format <<
dw6 |= gs_prog_data->control_data_format <<
HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
} else {
dw5 |= brw->gs.prog_data->control_data_format <<
dw5 |= gs_prog_data->control_data_format <<
IVB_GS_CONTROL_DATA_FORMAT_SHIFT;
}
@ -155,6 +159,7 @@ const struct brw_tracked_state gen7_gs_state = {
.dirty = {
.mesa = _NEW_TRANSFORM,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_GS_PROG_DATA,

6
lib/mesa/src/mesa/drivers/dri/i965/gen7_te_state.c
View File

@ -32,7 +32,8 @@ upload_te_state(struct brw_context *brw)
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
const struct brw_tes_prog_data *tes_prog_data =
brw_tes_prog_data(brw->tes.base.prog_data);
if (active) {
BEGIN_BATCH(4);
@ -57,7 +58,8 @@ upload_te_state(struct brw_context *brw)
const struct brw_tracked_state gen7_te_state = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT |
.brw = BRW_NEW_BLORP |
BRW_NEW_CONTEXT |
BRW_NEW_TES_PROG_DATA |
BRW_NEW_TESS_PROGRAMS,
},

97
lib/mesa/src/mesa/drivers/dri/i965/gen7_vs_state.c
View File

@ -29,94 +29,22 @@
#include "program/prog_statevars.h"
#include "intel_batchbuffer.h"
void
gen7_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode)
{
uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
/* Disable if the shader stage is inactive or there are no push constants. */
active = active && stage_state->push_const_size != 0;
int dwords = brw->gen >= 8 ? 11 : 7;
BEGIN_BATCH(dwords);
OUT_BATCH(opcode << 16 | (dwords - 2));
/* Workaround for SKL+ (we use option #2 until we have a need for more
* constant buffers). This comes from the documentation for 3DSTATE_CONSTANT_*
*
* The driver must ensure The following case does not occur without a flush
* to the 3D engine: 3DSTATE_CONSTANT_* with buffer 3 read length equal to
* zero committed followed by a 3DSTATE_CONSTANT_* with buffer 0 read length
* not equal to zero committed. Possible ways to avoid this condition
* include:
* 1. always force buffer 3 to have a non zero read length
* 2. always force buffer 0 to a zero read length
*/
if (brw->gen >= 9 && active) {
OUT_BATCH(0);
OUT_BATCH(stage_state->push_const_size);
} else {
OUT_BATCH(active ? stage_state->push_const_size : 0);
OUT_BATCH(0);
}
/* Pointer to the constant buffer. Covered by the set of state flags
* from gen6_prepare_wm_contants
*/
if (brw->gen >= 9 && active) {
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
/* XXX: When using buffers other than 0, you need to specify the
* graphics virtual address regardless of INSPM/debug bits
*/
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
stage_state->push_const_offset);
OUT_BATCH(0);
OUT_BATCH(0);
} else if (brw->gen>= 8) {
OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
} else {
OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
}
ADVANCE_BATCH();
/* On SKL+ the new constants don't take effect until the next corresponding
* 3DSTATE_BINDING_TABLE_POINTER_* command is parsed so we need to ensure
* that is sent
*/
if (brw->gen >= 9)
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
static void
upload_vs_state(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct brw_stage_state *stage_state = &brw->vs.base;
const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
const struct brw_vue_prog_data *vue_prog_data =
brw_vue_prog_data(stage_state->prog_data);
uint32_t floating_point_mode = 0;
const int max_threads_shift = brw->is_haswell ?
HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base;
if (!brw->is_haswell && !brw->is_baytrail)
gen7_emit_vs_workaround_flush(brw);
if (brw->vs.prog_data->base.base.use_alt_mode)
if (prog_data->use_alt_mode)
floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
BEGIN_BATCH(6);
@ -125,23 +53,23 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(floating_point_mode |
((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_VS_SAMPLER_COUNT_SHIFT) |
((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
((prog_data->binding_table.size_bytes / 4) <<
GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (prog_data->base.total_scratch) {
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(prog_data->base.total_scratch) - 11);
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
}
OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
OUT_BATCH((prog_data->dispatch_grf_start_reg <<
GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(vue_prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
OUT_BATCH(((devinfo->max_vs_threads - 1) << max_threads_shift) |
GEN6_VS_STATISTICS_ENABLE |
GEN6_VS_ENABLE);
ADVANCE_BATCH();
@ -149,8 +77,9 @@ upload_vs_state(struct brw_context *brw)
const struct brw_tracked_state gen7_vs_state = {
.dirty = {
.mesa = _NEW_TRANSFORM,
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_CONTEXT |
BRW_NEW_VS_PROG_DATA,
},

20
lib/mesa/src/mesa/drivers/dri/i965/gen8_hs_state.c
View File

@ -29,36 +29,39 @@
static void
gen8_upload_hs_state(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct brw_stage_state *stage_state = &brw->tcs.base;
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
/* BRW_NEW_HS_PROG_DATA */
const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;
/* BRW_NEW_TCS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
const struct brw_tcs_prog_data *tcs_prog_data =
brw_tcs_prog_data(stage_state->prog_data);
if (active) {
BEGIN_BATCH(9);
OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
GEN7_HS_SAMPLER_COUNT) |
SET_FIELD(prog_data->base.binding_table.size_bytes / 4,
SET_FIELD(prog_data->binding_table.size_bytes / 4,
GEN7_HS_BINDING_TABLE_ENTRY_COUNT));
OUT_BATCH(GEN7_HS_ENABLE |
GEN7_HS_STATISTICS_ENABLE |
(brw->max_hs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
SET_FIELD(brw->tcs.prog_data->instances - 1,
(devinfo->max_tcs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
SET_FIELD(tcs_prog_data->instances - 1,
GEN7_HS_INSTANCE_COUNT));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
if (prog_data->base.total_scratch) {
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
ffs(prog_data->base.total_scratch) - 11);
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
}
OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
SET_FIELD(prog_data->base.dispatch_grf_start_reg,
SET_FIELD(prog_data->dispatch_grf_start_reg,
GEN7_HS_DISPATCH_START_GRF));
OUT_BATCH(0); /* MBZ */
ADVANCE_BATCH();
@ -82,6 +85,7 @@ const struct brw_tracked_state gen8_hs_state = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_TESS_PROGRAMS,
},