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xf86-video-mga 1.4.6

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This commit is contained in:
matthieu 2006-12-17 11:05:41 +00:00
parent 61e72838e5
commit b915b0be10
10 changed files with 136 additions and 111 deletions
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37
driver/xf86-video-mga/ChangeLog
View File

@ -1,3 +1,40 @@
commit ede471a547a24e7f9688917fc3329a3d67fb2dc4
Author: Daniel Stone <daniel@fooishbar.org>
Date: Sat Dec 16 01:44:49 2006 +0200
bump to 1.4.6
commit 55d283a8c2347e809dadace3fb9a026bab6d57dd
Author: Daniel Stone <daniel@fooishbar.org>
Date: Wed Dec 6 18:46:00 2006 +0200
Makefile.am: fix ChangeLog hook
Make ChangeLog hook safe for all situations I could think of, including
carrying the ChangeLog through for distcheck when objdir != srcdir. It's
significantly more ugly, but eh.
commit fbbbb853041ae4af36eeffb24188b9a5513ba7d5
Author: Tilman Sauerbeck <tilman@code-monkey.de>
Date: Sat Dec 2 12:42:34 2006 +0100
Removed a duplicated register definition.
commit 447aae84d07cab34987ab08ead9319e176ccd904
Author: Tilman Sauerbeck <tilman@code-monkey.de>
Date: Fri Dec 1 20:19:13 2006 +0100
More janitoring work.
Moved the XPWRCTRL, XDISPCTRL and C2CTL register definitions
to mga_reg.h.
Cleaned up the DAC2 routing.
commit 10b2202c254b71b8d0da987a225d5e78a030bca4
Author: Tilman Sauerbeck <tilman@code-monkey.de>
Date: Fri Dec 1 19:10:55 2006 +0100
Use the XORG_RELEASE_VERSION autoconf macro.
commit 00efdc4959a0b240eb2dc7a3188c0ef64b2ad74a
Author: Daniel Stone <daniel@fooishbar.org>
Date: Thu Nov 30 19:59:38 2006 +0200

2
driver/xf86-video-mga/Makefile.am
View File

@ -27,6 +27,6 @@ EXTRA_DIST = README_HALLIB mga_PInS.txt ChangeLog
.PHONY: ChangeLog
ChangeLog:
git-log > ChangeLog
(GIT_DIR=$(top_srcdir)/.git git-log > .changelog.tmp && mv .changelog.tmp ChangeLog; rm -f .changelog.tmp) || (touch ChangeLog; echo 'git directory not found: installing possibly empty changelog.' >&2)
dist-hook: ChangeLog

9
driver/xf86-video-mga/config.h.in
View File

@ -50,6 +50,15 @@
/* Define to the version of this package. */
#undef PACKAGE_VERSION
/* Major version of this package */
#undef PACKAGE_VERSION_MAJOR
/* Minor version of this package */
#undef PACKAGE_VERSION_MINOR
/* Patch version of this package */
#undef PACKAGE_VERSION_PATCHLEVEL
/* Define to 1 if you have the ANSI C header files. */
#undef STDC_HEADERS

4
driver/xf86-video-mga/configure.ac
View File

@ -24,10 +24,12 @@ AC_PREREQ(2.57)
# When the version number is modified here, also modify it in src/mga.h.
AC_INIT([xf86-video-mga],
1.4.5,
1.4.6,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-mga)
XORG_RELEASE_VERSION
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
AC_CONFIG_AUX_DIR(.)

3
driver/xf86-video-mga/src/mga.h
View File

@ -154,9 +154,6 @@ void MGAdbg_outreg32(ScrnInfoPtr, int,int, char*);
#define MGA_C_NAME MGA
#define MGA_MODULE_DATA mgaModuleData
#define MGA_DRIVER_NAME "mga"
#define MGA_MAJOR_VERSION 1
#define MGA_MINOR_VERSION 4
#define MGA_PATCHLEVEL 4
typedef struct {
unsigned char ExtVga[6];

106
driver/xf86-video-mga/src/mga_dh.c
View File

@ -26,36 +26,6 @@
#define CLKSEL_MGA 0x0c
#define PLLLOCK 0x40
/* CRTC2 control field*/
#define C2_EN_A 0
#define C2_EN_M (1 << C2_EN_A)
#define C2_HIPRILVL_A 4
#define C2_HIPRILVL_M (7 << C2_HIPRILVL_A)
#define C2_MAXHIPRI_A 8
#define C2_MAXHIPRI_M (7 << C2_MAXHIPRI_A)
#define C2CTL_PIXCLKSEL_SHIFT 1L
#define C2CTL_PIXCLKSEL_MASK (3L << C2CTL_PIXCLKSEL_SHIFT)
#define C2CTL_PIXCLKSELH_SHIFT 14L
#define C2CTL_PIXCLKSELH_MASK (1L << C2CTL_PIXCLKSELH_SHIFT)
#define C2CTL_PIXCLKSEL_PCICLK 0L
#define C2CTL_PIXCLKSEL_VDOCLK (1L << C2CTL_PIXCLKSEL_SHIFT)
#define C2CTL_PIXCLKSEL_PIXELPLL (2L << C2CTL_PIXCLKSEL_SHIFT)
#define C2CTL_PIXCLKSEL_VIDEOPLL (3L << C2CTL_PIXCLKSEL_SHIFT)
#define C2CTL_PIXCLKSEL_VDCLK (1L << C2CTL_PIXCLKSELH_SHIFT)
#define C2CTL_PIXCLKSEL_CRISTAL (1L << C2CTL_PIXCLKSEL_SHIFT) | (1L << C2CTL_PIXCLKSELH_SHIFT)
#define C2CTL_PIXCLKSEL_SYSTEMPLL (2L << C2CTL_PIXCLKSEL_SHIFT) | (1L << C2CTL_PIXCLKSELH_SHIFT)
#define C2CTL_PIXCLKDIS_SHIFT 3L
#define C2CTL_PIXCLKDIS_MASK (1L << C2CTL_PIXCLKDIS_SHIFT)
#define C2CTL_PIXCLKDIS_DISABLE (1L << C2CTL_PIXCLKDIS_SHIFT)
#define C2CTL_CRTCDACSEL_SHIFT 20L
#define C2CTL_CRTCDACSEL_MASK (1L << C2CTL_CRTCDACSEL_SHIFT)
#define C2CTL_CRTCDACSEL_CRTC1 0
#define C2CTL_CRTCDACSEL_CRTC2 (1L << C2CTL_CRTCDACSEL_SHIFT)
/* Misc field*/
#define IOADDSEL 0x01
#define RAMMAPEN 0x02
@ -101,39 +71,6 @@
#define XSYNCCTRL_DAC2VSOFF_OFF (1 << XSYNCCTRL_DAC2VSOFF_SHIFT)
#define XSYNCCTRL_DAC2VSOFF_ON 0
/* XDISPCTRL field */
#define XDISPCTRL_DAC1OUTSEL_SHIFT 0L
#define XDISPCTRL_DAC1OUTSEL_MASK 1L
#define XDISPCTRL_DAC1OUTSEL_DIS 0L
#define XDISPCTRL_DAC1OUTSEL_EN 1L
#define XDISPCTRL_DAC2OUTSEL_SHIFT 2L
#define XDISPCTRL_DAC2OUTSEL_MASK (3L << XDISPCTRL_DAC2OUTSEL_SHIFT)
#define XDISPCTRL_DAC2OUTSEL_DIS 0L
#define XDISPCTRL_DAC2OUTSEL_CRTC1 (1L << XDISPCTRL_DAC2OUTSEL_SHIFT)
#define XDISPCTRL_DAC2OUTSEL_CRTC2 (2L << XDISPCTRL_DAC2OUTSEL_SHIFT)
#define XDISPCTRL_DAC2OUTSEL_TVE (3L << XDISPCTRL_DAC2OUTSEL_SHIFT)
#define XDISPCTRL_PANOUTSEL_SHIFT 5L
#define XDISPCTRL_PANOUTSEL_MASK (3L << XDISPCTRL_PANOUTSEL_SHIFT)
#define XDISPCTRL_PANOUTSEL_DIS 0L
#define XDISPCTRL_PANOUTSEL_CRTC1 (1L << XDISPCTRL_PANOUTSEL_SHIFT)
#define XDISPCTRL_PANOUTSEL_CRTC2RGB (2L << XDISPCTRL_PANOUTSEL_SHIFT)
#define XDISPCTRL_PANOUTSEL_CRTC2656 (3L << XDISPCTRL_PANOUTSEL_SHIFT)
/* XPWRCTRL field*/
#define XPWRCTRL_DAC2PDN_SHIFT 0
#define XPWRCTRL_DAC2PDN_MASK (1 << XPWRCTRL_DAC2PDN_SHIFT)
#define XPWRCTRL_VIDPLLPDN_SHIFT 1
#define XPWRCTRL_VIDPLLPDN_MASK (1 << XPWRCTRL_VIDPLLPDN_SHIFT)
#define XPWRCTRL_PANPDN_SHIFT 2
#define XPWRCTRL_PANPDN_MASK (1 << XPWRCTRL_PANPDN_SHIFT)
#define XPWRCTRL_RFIFOPDN_SHIFT 3
#define XPWRCTRL_RFIFOPDN_MASK (1 << XPWRCTRL_RFIFOPDN_SHIFT)
#define XPWRCTRL_CFIFOPDN_SHIFT 4
#define XPWRCTRL_CFIFOPDN_MASK (1 << XPWRCTRL_CFIFOPDN_SHIFT)
#define POS_HSYNC 0x00000004
#define POS_VSYNC 0x00000008
@ -295,20 +232,23 @@ void MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo)
ulC2CTL = INREG( MGAREG_C2CTL);
/*--- Disable Pixel clock oscillations On Crtc1 */
OUTREG( MGAREG_C2CTL, ulC2CTL | C2CTL_PIXCLKDIS_MASK);
OUTREG( MGAREG_C2CTL, ulC2CTL | MGAREG_C2CTL_PIXCLKDIS_MASK);
/*--- Have to wait minimum time (2 acces will be ok) */
(void) INREG( MGAREG_Status);
(void) INREG( MGAREG_Status);
ulC2CTL &= ~(C2CTL_PIXCLKSEL_MASK | C2CTL_PIXCLKSELH_MASK);
ulC2CTL &= ~MGAREG_C2CTL_PIXCLKSEL_MASK;
ulC2CTL &= ~MGAREG_C2CTL_PIXCLKSELH_MASK;
ulC2CTL |= C2CTL_PIXCLKSEL_VIDEOPLL;
ulC2CTL |= MGAREG_C2CTL_PIXCLKSEL_VIDEOPLL;
OUTREG( MGAREG_C2CTL, ulC2CTL);
/*--- Enable Pixel clock oscillations on CRTC2*/
OUTREG( MGAREG_C2CTL, ulC2CTL & ~C2CTL_PIXCLKDIS_MASK);
ulC2CTL &= ~MGAREG_C2CTL_PIXCLKDIS_MASK;
OUTREG( MGAREG_C2CTL, ulC2CTL);
/* We don't use MISC synch pol, must be 0*/
@ -336,24 +276,21 @@ void MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo)
ulC2CTL = INREG(MGAREG_C2CTL);
ucXDispCtrl = inMGAdac(MGA1064_DISP_CTL);
ucXDispCtrl &= ~XDISPCTRL_DAC2OUTSEL_MASK;
ucXDispCtrl |= XDISPCTRL_DAC2OUTSEL_CRTC2;
ucXDispCtrl &= ~MGA1064_DISP_CTL_DAC2OUTSEL_MASK;
if (!pMga->SecondOutput) {
/* Route Crtc2 on Output1 */
ucXDispCtrl &= ~XDISPCTRL_DAC2OUTSEL_MASK;
ucXDispCtrl |= XDISPCTRL_DAC2OUTSEL_CRTC1;
ulC2CTL |= C2CTL_CRTCDACSEL_CRTC2;
ucXDispCtrl |= MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1;
ulC2CTL |= MGAREG_C2CTL_CRTCDACSEL_CRTC2;
}
else {
/* Route Crtc2 on Output2*/
ucXDispCtrl &= ~XDISPCTRL_DAC2OUTSEL_MASK;
ucXDispCtrl |= XDISPCTRL_DAC2OUTSEL_CRTC2;
ulC2CTL &= ~C2CTL_CRTCDACSEL_MASK;
ucXDispCtrl |= MGA1064_DISP_CTL_DAC2OUTSEL_CRTC2;
ulC2CTL &= ~MGAREG_C2CTL_CRTCDACSEL_MASK;
}
/* Enable CRTC2*/
ulC2CTL |= C2_EN_M;
ulC2CTL |= MGAREG_C2CTL_C2_EN;
pReg->dac2[ MGA1064_DISP_CTL - 0x80] = ucXDispCtrl;
@ -377,15 +314,14 @@ void MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo)
ucByte &= ~(XSYNCCTRL_DAC2HSOFF_MASK | XSYNCCTRL_DAC2VSOFF_MASK);
pReg->dac2[ MGA1064_SYNC_CTL - 0x80] = ucByte;
/* Powerup DAC2*/
ucByte = inMGAdac( MGA1064_PWR_CTL);
pReg->dac2[ MGA1064_PWR_CTL - 0x80] = /* 0x0b; */ (ucByte | XPWRCTRL_DAC2PDN_MASK);
/* Power up Fifo*/
ucByte = inMGAdac( MGA1064_PWR_CTL);
pReg->dac2[ MGA1064_PWR_CTL - 0x80] = 0x1b; /* (ucByte | XPWRCTRL_CFIFOPDN_MASK) */;
/* Power up DAC2, Fifo.
* The TMDS is powered down here, which is likely wrong.
*/
pReg->dac2[MGA1064_PWR_CTL - 0x80] =
MGA1064_PWR_CTL_DAC2_EN |
MGA1064_PWR_CTL_VID_PLL_EN |
MGA1064_PWR_CTL_RFIFO_EN |
MGA1064_PWR_CTL_CFIFO_EN;
#ifdef DEBUG

6
driver/xf86-video-mga/src/mga_dri.c
View File

@ -987,9 +987,9 @@ Bool MGADRIScreenInit( ScreenPtr pScreen )
((pciConfigPtr)pMga->PciInfo->thisCard)->devnum,
((pciConfigPtr)pMga->PciInfo->thisCard)->funcnum );
}
pDRIInfo->ddxDriverMajorVersion = MGA_MAJOR_VERSION;
pDRIInfo->ddxDriverMinorVersion = MGA_MINOR_VERSION;
pDRIInfo->ddxDriverPatchVersion = MGA_PATCHLEVEL;
pDRIInfo->ddxDriverMajorVersion = PACKAGE_VERSION_MAJOR;
pDRIInfo->ddxDriverMinorVersion = PACKAGE_VERSION_MINOR;
pDRIInfo->ddxDriverPatchVersion = PACKAGE_VERSION_PATCHLEVEL;
pDRIInfo->frameBufferPhysicalAddress = (void *) pMga->FbAddress;
pDRIInfo->frameBufferSize = pMga->FbMapSize;
pDRIInfo->frameBufferStride = pScrn->displayWidth*(pScrn->bitsPerPixel/8);

32
driver/xf86-video-mga/src/mga_driver.c
View File

@ -440,7 +440,7 @@ static XF86ModuleVersionInfo mgaVersRec =
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
MGA_MAJOR_VERSION, MGA_MINOR_VERSION, MGA_PATCHLEVEL,
PACKAGE_VERSION_MAJOR, PACKAGE_VERSION_MINOR, PACKAGE_VERSION_PATCHLEVEL,
ABI_CLASS_VIDEODRV, /* This is a video driver */
ABI_VIDEODRV_VERSION,
MOD_CLASS_VIDEODRV,
@ -2945,8 +2945,8 @@ void MGARestoreSecondCrtc(ScrnInfoPtr pScrn)
*/
CARD8 ucXDispCtrl = inMGAdac(MGA1064_DISP_CTL);
ucXDispCtrl &= ~0x0c; /* dac2outsel mask */
ucXDispCtrl |= 0x04; /* dac2 -> crtc1 */
ucXDispCtrl &= ~MGA1064_DISP_CTL_DAC2OUTSEL_MASK;
ucXDispCtrl |= MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1;
outMGAdac(MGA1064_DISP_CTL, ucXDispCtrl);
@ -2954,9 +2954,13 @@ void MGARestoreSecondCrtc(ScrnInfoPtr pScrn)
CARD8 ucXDispCtrl = inMGAdac(MGA1064_DISP_CTL);
CARD32 ulC2CTL = INREG(MGAREG_C2CTL);
ucXDispCtrl &= ~0x0c; /* dac2outsel mask */
ucXDispCtrl |= 0x5; /* dac1outsel -> crtcdacsel, dac2 -> crtc1 */
ulC2CTL &= ~0x00100000; /* crtcdacsel -> crtc1 */
ucXDispCtrl &= ~MGA1064_DISP_CTL_DAC2OUTSEL_MASK;
ucXDispCtrl |= MGA1064_DISP_CTL_DAC1OUTSEL_EN;
ucXDispCtrl |= MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1;
/* crtcdacsel -> crtc1 */
ulC2CTL &= ~MGAREG_C2CTL_CRTCDACSEL_CRTC2;
ulC2CTL |= MGAREG_C2CTL_CRTCDACSEL_CRTC1;
outMGAdac(MGA1064_DISP_CTL, ucXDispCtrl);
OUTREG(MGAREG_C2CTL, ulC2CTL);
@ -2966,12 +2970,10 @@ void MGARestoreSecondCrtc(ScrnInfoPtr pScrn)
/* Force to close second crtc */
CARD32 ulC2CTL = INREG(MGAREG_C2CTL);
ulC2CTL &= ~0x1; /* crtc2 disabled */
ulC2CTL &= ~MGAREG_C2CTL_C2_EN;
OUTREG(MGAREG_C2CTL, ulC2CTL);
}
return;
}
/*
@ -3692,8 +3694,6 @@ MGAAdjustFrame(int scrnIndex, int x, int y, int flags)
}
#define C2STARTADD0 0x3C28
void
MGAAdjustFrameCrtc2(int scrnIndex, int x, int y, int flags)
{
@ -3723,7 +3723,7 @@ MGAAdjustFrameCrtc2(int scrnIndex, int x, int y, int flags)
Base = (y * pLayout->displayWidth + x) * pLayout->bitsPerPixel >> 3;
Base += pMga->DstOrg;
Base &= 0x01ffffc0;
OUTREG(C2STARTADD0, Base);
OUTREG(MGAREG_C2STARTADD0, Base);
);
}
@ -4079,8 +4079,8 @@ MGADisplayPowerManagementSetCrtc2(ScrnInfoPtr pScrn, int PowerManagementMode,
if (PowerManagementMode==DPMSModeOn) {
/* Enable CRTC2 */
val |= 0x1;
val &= ~(0x8);
val |= MGAREG_C2CTL_C2_EN;
val &= ~MGAREG_C2CTL_PIXCLKDIS_DISABLE;
OUTREG(MGAREG_C2CTL, val);
/* Restore normal MAVEN values */
if (pMga->Maven) {
@ -4108,8 +4108,8 @@ MGADisplayPowerManagementSetCrtc2(ScrnInfoPtr pScrn, int PowerManagementMode,
}
else {
/* Disable CRTC2 video */
val |= 0x8;
val &= ~(0x1);
val |= MGAREG_C2CTL_PIXCLKDIS_DISABLE;
val &= ~MGAREG_C2CTL_C2_EN;
OUTREG(MGAREG_C2CTL, val);
/* Disable MAVEN display */

4
driver/xf86-video-mga/src/mga_merge.c
View File

@ -955,7 +955,7 @@ MGASaveScreenMerged(ScreenPtr pScreen, int mode)
/* power on Dac2 */
reg = inMGAdac(MGA1064_PWR_CTL);
reg |= 1;
reg |= MGA1064_PWR_CTL_DAC2_EN;
outMGAdac(MGA1064_PWR_CTL, reg);
} else {
/* power off Dac1 */
@ -965,7 +965,7 @@ MGASaveScreenMerged(ScreenPtr pScreen, int mode)
/* power off Dac2 */
reg = inMGAdac(MGA1064_PWR_CTL);
reg &= ~1;
reg &= ~MGA1064_PWR_CTL_DAC2_EN;
outMGAdac(MGA1064_PWR_CTL, reg);
}

44
driver/xf86-video-mga/src/mga_reg.h
View File

@ -408,8 +408,29 @@
#define MGA1064_VID_PLL_N 0x8F
#define MGA1064_DISP_CTL 0x8a
#define MGA1064_DISP_CTL_DAC1OUTSEL_MASK 0x01
#define MGA1064_DISP_CTL_DAC1OUTSEL_DIS 0x00
#define MGA1064_DISP_CTL_DAC1OUTSEL_EN 0x01
#define MGA1064_DISP_CTL_DAC2OUTSEL_MASK (0x03 << 2)
#define MGA1064_DISP_CTL_DAC2OUTSEL_DIS 0x00
#define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1 (0x01 << 2)
#define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC2 (0x02 << 2)
#define MGA1064_DISP_CTL_DAC2OUTSEL_TVE (0x03 << 2)
#define MGA1064_DISP_CTL_PANOUTSEL_MASK (0x03 << 5)
#define MGA1064_DISP_CTL_PANOUTSEL_DIS 0x00
#define MGA1064_DISP_CTL_PANOUTSEL_CRTC1 (0x01 << 5)
#define MGA1064_DISP_CTL_PANOUTSEL_CRTC2RGB (0x02 << 5)
#define MGA1064_DISP_CTL_PANOUTSEL_CRTC2656 (0x03 << 5)
#define MGA1064_SYNC_CTL 0x8b
#define MGA1064_PWR_CTL 0xa0
#define MGA1064_PWR_CTL_DAC2_EN (0x01 << 0)
#define MGA1064_PWR_CTL_VID_PLL_EN (0x01 << 1)
#define MGA1064_PWR_CTL_PANEL_EN (0x01 << 2)
#define MGA1064_PWR_CTL_RFIFO_EN (0x01 << 3)
#define MGA1064_PWR_CTL_CFIFO_EN (0x01 << 4)
#define MGA1064_PAN_CTL 0xa2
/* Using crtc2 */
@ -424,6 +445,29 @@
#define MGAREG2_C2DATACTL 0x4c
#define MGAREG_C2CTL 0x3c10
#define MGAREG_C2CTL_C2_EN 0x01
#define MGAREG_C2_HIPRILVL_M (0x07 << 4)
#define MGAREG_C2_MAXHIPRI_M (0x07 << 8)
#define MGAREG_C2CTL_PIXCLKSEL_MASK (0x03 << 1)
#define MGAREG_C2CTL_PIXCLKSELH_MASK (0x01 << 14)
#define MGAREG_C2CTL_PIXCLKSEL_PCICLK 0x00
#define MGAREG_C2CTL_PIXCLKSEL_VDOCLK (0x01 << 1)
#define MGAREG_C2CTL_PIXCLKSEL_PIXELPLL (0x02 << 1)
#define MGAREG_C2CTL_PIXCLKSEL_VIDEOPLL (0x03 << 1)
#define MGAREG_C2CTL_PIXCLKSEL_VDCLK (0x01 << 14)
#define MGAREG_C2CTL_PIXCLKSEL_CRISTAL (0x01 << 1) | (0x01 << 14)
#define MGAREG_C2CTL_PIXCLKSEL_SYSTEMPLL (0x02 << 1) | (0x01 << 14)
#define MGAREG_C2CTL_PIXCLKDIS_MASK (0x01 << 3)
#define MGAREG_C2CTL_PIXCLKDIS_DISABLE (0x01 << 3)
#define MGAREG_C2CTL_CRTCDACSEL_MASK (0x01 << 20)
#define MGAREG_C2CTL_CRTCDACSEL_CRTC1 0x00
#define MGAREG_C2CTL_CRTCDACSEL_CRTC2 (0x01 << 20)
#define MGAREG_C2HPARAM 0x3c14
#define MGAREG_C2HSYNC 0x3c18
#define MGAREG_C2VPARAM 0x3c1c