Add basic support for ivy bridge and fix several cases of register

access not being adjusted for the pch split, one of which prevented
multiple display pipes from working.  The third pipe on ivy bridge
remains disabled for now.

ok kettenis@ thanks to everyone who tested

driver/xf86-video-intel/src/i830_bios.c

@@ -210,7 +210,7 @@ static void parse_general_features(intel_screen_private *intel, struct bdb_heade
 	if (intel->lvds_use_ssc) {
 		if (IS_I85X(intel))
 			intel->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
-		else if (IS_GEN5(intel) || IS_GEN6(intel))
+		else if (IS_GEN5(intel) || IS_GEN6(intel) || IS_GEN7(intel))
 			intel->lvds_ssc_freq = general->ssc_freq ? 100 : 120;
 		else
 			intel->lvds_ssc_freq = general->ssc_freq ? 100 : 96;

driver/xf86-video-intel/src/i830_display.c

@@ -1491,6 +1491,123 @@ static void gen6_fdi_link_train(xf86CrtcPtr crtc)
     ErrorF("FDI train done\n");
 }
 
+/* Manual link training for Ivy Bridge A0 parts */
+static void ivb_manual_fdi_link_train(xf86CrtcPtr crtc)
+{
+	ScrnInfoPtr scrn = crtc->scrn;
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+	I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+	int pipe = intel_crtc->pipe;
+	int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
+	int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+	int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
+	int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
+
+	uint32_t temp, i;
+
+	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+	   for train result */
+	temp = INREG(fdi_rx_imr_reg);
+	temp &= ~FDI_RX_SYMBOL_LOCK;
+	temp &= ~FDI_RX_BIT_LOCK;
+	OUTREG(fdi_rx_imr_reg, temp);
+	INREG(fdi_rx_imr_reg);
+	usleep(150);
+
+	/* enable CPU FDI TX and PCH FDI RX */
+	temp = INREG(fdi_tx_reg);
+	temp &= ~(7 << 19);
+	temp |= /*(intel_crtc->fdi_lanes - 1)*/3 << 19;
+	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
+	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
+	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+	temp |= FDI_COMPOSITE_SYNC;
+	OUTREG(fdi_tx_reg, temp | FDI_TX_ENABLE);
+	INREG(fdi_tx_reg);
+
+	temp = INREG(fdi_rx_reg);
+	temp &= ~FDI_LINK_TRAIN_AUTO;
+	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+	temp |= FDI_COMPOSITE_SYNC;
+	OUTREG(fdi_rx_reg, temp | FDI_RX_ENABLE);
+	INREG(fdi_rx_reg);
+
+	usleep(150);
+
+	if (HAS_PCH_CPT(intel)) {
+		temp = INREG(SOUTH_CHICKEN1);
+		temp |= FDI_PHASE_SYNC_OVR(pipe);
+		OUTREG(SOUTH_CHICKEN1, temp); /* once to unlock... */
+		temp |= FDI_PHASE_SYNC_EN(pipe);
+		OUTREG(SOUTH_CHICKEN1, temp); /* then again to enable */
+		INREG(SOUTH_CHICKEN1);
+		usleep(150);
+	}
+		
+	for (i = 0; i < 4; i++) {
+		temp = INREG(fdi_tx_reg);
+		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+		temp |= snb_b_fdi_train_param[i];
+		OUTREG(fdi_tx_reg, temp);
+		INREG(fdi_tx_reg);
+
+		usleep(500);
+
+		temp = INREG(fdi_rx_iir_reg);
+		ErrorF("FDI_RX_IIR 0x%x\n", temp);
+
+		if (temp & FDI_RX_BIT_LOCK) {
+			OUTREG(fdi_rx_iir_reg,
+			           temp | FDI_RX_BIT_LOCK);
+			ErrorF("FDI train 1 done.\n");
+			break;
+		}
+	}
+	if (i == 4)
+		ErrorF("FDI train 1 fail!\n");
+
+	/* Train 2 */
+	temp = INREG(fdi_tx_reg);
+	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
+	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+	OUTREG(fdi_tx_reg, temp);
+
+	temp = INREG(fdi_rx_reg);
+	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
+	OUTREG(fdi_rx_reg, temp);
+
+	usleep(150);
+
+	for (i = 0; i < 4; i++) {
+		temp = INREG(fdi_tx_reg);
+		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+		temp |= snb_b_fdi_train_param[i];
+		OUTREG(fdi_tx_reg, temp);
+		INREG(fdi_tx_reg);
+
+		usleep(500);
+
+		temp = INREG(fdi_rx_iir_reg);
+		ErrorF("FDI_RX_IIR 0x%x\n", temp);
+
+		if (temp & FDI_RX_SYMBOL_LOCK) {
+			OUTREG(fdi_rx_iir_reg,
+			           temp | FDI_RX_SYMBOL_LOCK);
+			ErrorF("FDI train 2 done.\n");
+			break;
+		}
+	}
+	if (i == 4)
+		ErrorF("FDI train 2 fail!\n");
+
+	ErrorF("FDI train done\n");
+}
+
 static void
 ironlake_crtc_enable(xf86CrtcPtr crtc)
 {
@@ -1600,6 +1717,8 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	/* Train FDI. */
 	if (IS_GEN6(intel))
 		gen6_fdi_link_train(crtc);
+	else if (IS_IVYBRIDGE(intel))
+		ivb_manual_fdi_link_train(crtc);
 	else
 		ironlake_fdi_link_train(crtc);
 
@@ -1634,9 +1753,14 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 
 	ErrorF("FDI TX link normal\n");
 	temp = INREG(fdi_tx_reg);
-	temp &= ~FDI_LINK_TRAIN_NONE;
+	if (IS_IVYBRIDGE(intel)) {
-	OUTREG(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
+		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
-		   FDI_TX_ENHANCE_FRAME_ENABLE);
+		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+	} else {
+		temp &= ~FDI_LINK_TRAIN_NONE;
+		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+	}
+	OUTREG(fdi_tx_reg, temp);
 	INREG(fdi_tx_reg);
 
 	temp = INREG(fdi_rx_reg);
@@ -2534,16 +2658,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 
 	lvds = INREG(lvds_reg);
 	lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
-	if (pipe == 1) {
+	if (HAS_PCH_CPT(intel)) {
-	    if (HAS_PCH_CPT(intel))
+	    lvds &= ~PORT_TRANS_SEL_MASK;
-		lvds |= PORT_TRANS_B_SEL_CPT;
+	    lvds |= PORT_TRANS_SEL_CPT(pipe);
-	    else
-		lvds |= LVDS_PIPEB_SELECT;
 	} else {
-	    if (HAS_PCH_CPT(intel))
+	    if (pipe == 1)
-		lvds &= ~PORT_TRANS_SEL_MASK;
+		lvds |= LVDS_PIPEB_SELECT;	
 	    else
-	    	lvds &= ~LVDS_PIPEB_SELECT;
+		lvds &= ~LVDS_PIPEB_SELECT;
 	}
 
 	/* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -2646,7 +2768,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 
     if (HAS_PCH_SPLIT(intel)) {
 	OUTREG(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
-	OUTREG(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
+	OUTREG(data_n1_reg, m_n.gmch_n);
 	OUTREG(link_m1_reg, m_n.link_m);
 	OUTREG(link_n1_reg, m_n.link_n);
 

driver/xf86-video-intel/src/i830_lvds.c

@@ -1352,6 +1352,7 @@ i830_lvds_set_property(xf86OutputPtr output, Atom property,
     intel_screen_private    *intel = intel_get_screen_private(scrn);
     I830OutputPrivatePtr    intel_output = output->driver_private;
     struct i830_lvds_priv   *dev_priv = intel_output->dev_priv;
+    uint32_t		    ctl_reg;
     
     if (property == backlight_atom) {
 	INT32 val;
@@ -1402,7 +1403,12 @@ i830_lvds_set_property(xf86OutputPtr output, Atom property,
 		       "RRConfigureOutputProperty error, %d\n", ret);
 	}
 	/* Set the current value of the backlight property */
-	if ((INREG(PP_CONTROL) & POWER_TARGET_ON) && !dev_priv->dpmsoff) 
+	if (HAS_PCH_SPLIT(intel))
+		ctl_reg = PCH_PP_CONTROL;
+	else
+		ctl_reg = PP_CONTROL;
+	
+	if ((INREG(ctl_reg) & POWER_TARGET_ON) && !dev_priv->dpmsoff) 
 	    data = dev_priv->get_backlight(output);
 	else
 	    data = dev_priv->backlight_duty_cycle;
@@ -1462,6 +1468,7 @@ i830_lvds_get_property(xf86OutputPtr output, Atom property)
     I830OutputPrivatePtr    intel_output = output->driver_private;
     struct i830_lvds_priv   *dev_priv = intel_output->dev_priv;
     int ret;
+    uint32_t		    ctl_reg;
 
     /*
      * Only need to update properties that might change out from under
@@ -1469,7 +1476,12 @@ i830_lvds_get_property(xf86OutputPtr output, Atom property)
      */
     if (property == backlight_atom) {
 	int val;
-	if ((INREG(PP_CONTROL) & POWER_TARGET_ON) && !dev_priv->dpmsoff) {
+ 	if (HAS_PCH_SPLIT(intel))
+		ctl_reg = PCH_PP_CONTROL;
+	else
+		ctl_reg = PP_CONTROL;
+
+	if ((INREG(ctl_reg) & POWER_TARGET_ON) && !dev_priv->dpmsoff) {
 	    val = dev_priv->get_backlight(output);
 	    dev_priv->backlight_duty_cycle = val;
 	} else
@@ -1491,7 +1503,19 @@ i830_lvds_get_crtc(xf86OutputPtr output)
 {
     ScrnInfoPtr	scrn = output->scrn;
     intel_screen_private    *intel = intel_get_screen_private(scrn);
-    int pipe = !!(INREG(LVDS) & LVDS_PIPEB_SELECT);
+    uint32_t		    lvds_reg, pipeb_mask;
+
+    if (HAS_PCH_SPLIT(intel))
+        lvds_reg = PCH_LVDS;
+    else
+        lvds_reg = LVDS;
+
+    if (HAS_PCH_CPT(intel))
+        pipeb_mask = PORT_TRANS_B_SEL_CPT;
+    else
+        pipeb_mask = LVDS_PIPEB_SELECT;
+
+    int pipe = !!(INREG(lvds_reg) & pipeb_mask);
    
     return intel_pipe_to_crtc(scrn, pipe);
 }
@@ -1560,7 +1584,7 @@ i830_lvds_init(ScrnInfoPtr scrn)
     }
     intel_output->type = I830_OUTPUT_LVDS;
     intel_output->pipe_mask = (1 << 1);
-    if (0 && IS_IGDNG(intel)) /* XXX put me back */
+    if (HAS_PCH_SPLIT(intel))
 	intel_output->pipe_mask |= (1 << 0);
     intel_output->clone_mask = (1 << I830_OUTPUT_LVDS);
     

driver/xf86-video-intel/src/i830_reg.h

@@ -4096,11 +4096,18 @@ typedef enum {
 #define  TRANS_6BPC		(2<<5)
 #define  TRANS_12BPC		(3<<5)
 
+#define SOUTH_CHICKEN1          0xc2000
+#define  FDIA_PHASE_SYNC_SHIFT_OVR      19
+#define  FDIA_PHASE_SYNC_SHIFT_EN       18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT   0
 #define  PORT_TRANS_B_SEL_CPT   (1<<29)
 #define  PORT_TRANS_C_SEL_CPT   (2<<29)
 #define  PORT_TRANS_SEL_MASK    (3<<29)
+#define  PORT_TRANS_SEL_CPT(pipe)       ((pipe) << 29)
 
 #define FDI_RXA_CHICKEN		0xc200c
 #define FDI_RXB_CHICKEN		0xc2010
@@ -4145,7 +4152,16 @@ typedef enum {
 #define  FDI_TX_ENHANCE_FRAME_ENABLE	(1<<18)
 /* IGDNG: hardwired to 1 */
 #define  FDI_TX_PLL_ENABLE		(1<<14)
+
+/* Ivybridge has different bits for lolz */
+#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
+#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
+#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
+
 /* both Tx and Rx */
+#define  FDI_COMPOSITE_SYNC		(1<<11)
+#define  FDI_LINK_TRAIN_AUTO		(1<<10)
 #define  FDI_SCRAMBLING_ENABLE		(0<<7)
 #define  FDI_SCRAMBLING_DISABLE		(1<<7)
 
@@ -4155,6 +4171,8 @@ typedef enum {
 #define  FDI_RX_ENABLE		(1<<31)
 #define  FDI_RX_DISABLE		(0<<31)
 /* train, dp width same as FDI_TX */
+#define  FDI_FS_ERRC_ENABLE		(1<<27)
+#define  FDI_FE_ERRC_ENABLE		(1<<26)
 #define  FDI_DP_PORT_WIDTH_X8		(7<<19)
 #define  FDI_8BPC			(0<<16)
 #define  FDI_10BPC			(1<<16)
@@ -4262,9 +4280,13 @@ typedef enum {
 
 #define BLC_PWM_CPU_CTL2	0x48250
 #define  PWM_ENABLE		(1 << 31)
+#define  PWM_PIPE_SELECT	(1 << 29)
+#define  PWM_PIPE_SELECT_IVB	(3 << 29)
 #define  PWM_PIPE_A		(0 << 29)
 #define  PWM_PIPE_B		(1 << 29)
-#define BLC_PWM_CPU_CTL		0x48254
+#define  PWM_PIPE_C		(2 << 29) /* ivb + */
+#define  PWM_PIPE(pipe)		((pipe) << 29)
+#define  BLC_PWM_CPU_CTL	0x48254
 
 #define BLC_PWM_PCH_CTL1	0xc8250
 #define  PWM_PCH_ENABLE		(1 << 31)

driver/xf86-video-intel/src/i965_reg.h

@@ -219,7 +219,7 @@
 # define GEN7_PS_FLOATING_POINT_MODE_ALT                (1 << 16)
 /* DW3: scratch space */
 /* DW4 */
-# define GEN7_PS_MAX_THREADS_SHIFT                      23
+# define GEN7_PS_MAX_THREADS_SHIFT                      24
 # define GEN7_PS_PUSH_CONSTANT_ENABLE                   (1 << 11)
 # define GEN7_PS_ATTRIBUTE_ENABLE                       (1 << 10)
 # define GEN7_PS_OMASK_TO_RENDER_TARGET                 (1 << 9)

driver/xf86-video-intel/src/i965_render.c

@@ -2644,7 +2644,7 @@ gen7_composite_wm_state(intel_screen_private *intel,
 	OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
 		  (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 	OUT_BATCH(0); /* scratch space base offset */
-	OUT_BATCH(((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+	OUT_BATCH(((48 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
 		  GEN7_PS_ATTRIBUTE_ENABLE |
 		  GEN7_PS_16_DISPATCH_ENABLE);
 	OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));

driver/xf86-video-intel/src/i965_video.c

@@ -1723,7 +1723,7 @@ gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
 
 	OUT_BATCH(0); /* scratch space base offset */
 	OUT_BATCH(
-		((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+		((48 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
 		GEN7_PS_ATTRIBUTE_ENABLE |
 		GEN7_PS_16_DISPATCH_ENABLE);
 	OUT_BATCH(

driver/xf86-video-intel/src/intel_driver.c

@@ -205,7 +205,7 @@ I830DetectMemory(ScrnInfoPtr scrn)
    int range;
    struct pci_device *bridge = intel_host_bridge ();
 
-   if (IS_GEN6(intel))
+   if (IS_GEN6(intel) || IS_GEN7(intel))
       pci_device_cfg_read_u16(bridge, &gmch_ctrl, SNB_GMCH_CTRL);
    else
       pci_device_cfg_read_u16(bridge, &gmch_ctrl, I830_GMCH_CTRL);
@@ -263,10 +263,11 @@ I830DetectMemory(ScrnInfoPtr scrn)
    range = gtt_size + 4;
 
    /* new 4 series hardware has seperate GTT stolen with GFX stolen */
-   if (IS_G4X(intel) || IS_IGD(intel) || IS_GEN5(intel) || IS_GEN6(intel))
+   if (IS_G4X(intel) || IS_IGD(intel) || IS_GEN5(intel) || IS_GEN6(intel) ||
+     IS_GEN7(intel))
        range = 4;
 
-   if (IS_GEN6(intel)) {
+   if (IS_GEN6(intel) || IS_GEN7(intel)) {
       switch (gmch_ctrl & SNB_GMCH_GMS_STOLEN_MASK) {
       case SNB_GMCH_GMS_STOLEN_32M:
 	 memsize = MB(32) - KB(range);
@@ -430,7 +431,8 @@ I830MapMMIO(ScrnInfoPtr scrn)
 
       if (IS_I965G(intel)) 
       {
-	 if (IS_G4X(intel) || IS_GEN5(intel) || IS_GEN6(intel)) {
+	 if (IS_G4X(intel) || IS_GEN5(intel) || IS_GEN6(intel) ||
+	    IS_GEN7(intel)) {
 	     gttaddr = intel->MMIOAddr + MB(2);
 	     intel->GTTMapSize = MB(2);
 	 } else {
@@ -710,7 +712,7 @@ static void i830_init_clock_gating(ScrnInfoPtr scrn)
 
     /* Disable clock gating reported to work incorrectly according to the specs.
      */
-	if (IS_GEN6(intel)) {
+	if (IS_GEN6(intel) || IS_GEN7(intel)) {
 		uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
 		OUTREG(PCH_DSPCLK_GATE_D, dspclk_gate);
 	} else if (IS_G4X(intel)) {
@@ -1757,8 +1759,12 @@ static Bool SaveHWState(ScrnInfoPtr scrn)
 	if (IS_I965GM(intel) || IS_GM45(intel))
 		intel->savePWRCTXA = INREG(PWRCTXA);
 
-	if (IS_MOBILE(intel) && !IS_I830(intel))
+	if (IS_MOBILE(intel) && !IS_I830(intel)) {
-		intel->saveLVDS = INREG(LVDS);
+		if (HAS_PCH_SPLIT(intel))
+			intel->saveLVDS = INREG(PCH_LVDS);
+		else
+			intel->saveLVDS = INREG(LVDS);
+	}
 	intel->savePFIT_CONTROL = INREG(PFIT_CONTROL);
 
 	for (i = 0; i < xf86_config->num_output; i++) {

driver/xf86-video-intel/src/intel_driver.h

@@ -190,6 +190,7 @@
 #define PCI_CHIP_IVYBRIDGE_D_GT1	0x0152
 #define PCI_CHIP_IVYBRIDGE_D_GT2	0x0162
 #define PCI_CHIP_IVYBRIDGE_S_GT1	0x015a
+#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a
 
 #endif
 
@@ -242,6 +243,15 @@
 #define IS_IVYBRIDGE_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_M_GT1  || \
 			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_M_GT2)
 
+#define IS_IVYBRIDGE_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_D_GT1 || \
+			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_D_GT2)
+
+#define IS_IVYBRIDGE_S(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_S_GT1 || \
+			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IVYBRIDGE_S_GT2)
+
+#define IS_IVYBRIDGE(dev) (IS_IVYBRIDGE_M(dev) || IS_IVYBRIDGE_D(dev) || \
+			IS_IVYBRIDGE_S(dev))
+
 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 	IS_I945GM(dev) || IS_CRESTLINE(dev) || IS_GM45(dev) || \
 	IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev) || IS_SANDYBRIDGE_M(dev) || \
@@ -250,8 +260,10 @@
 #define SUPPORTS_TV(dev) (IS_I915GM(dev) || IS_I945GM(dev) || \
 	IS_CRESTLINE(dev) || IS_GM45(dev))
 
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
-#define HAS_PCH_CPT(dev) (IS_GEN6(dev))	/* XXX */
+#define HAS_PCH_IBX(dev) (IS_GEN5(dev))
+/* PantherPoint is CPT compatible */
+#define HAS_PCH_CPT(dev) (IS_GEN6(dev) || IS_GEN7(dev))	/* XXX */
 
 
 /* Some chips have specific errata (or limits) that we need to workaround. */
@@ -276,7 +288,8 @@
 			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \
 			 IS_G4X(pI810) || \
 			 IS_GEN5(pI810) || \
-			 IS_GEN6(pI810))
+			 IS_GEN6(pI810) || \
+			 IS_GEN7(pI810))
 #define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
  			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
 			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
@@ -292,16 +305,21 @@
 /* mark chipsets for using gfx VM offset for overlay */
 #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
 /* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || \
+    IS_GEN6(pI810) || IS_GEN7(pI810))
 /* chipsets require graphics mem for hardware status page */
 #define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
 			     (IS_G33CLASS(pI810) ||\
-			      IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810)))
+			      IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810) || \
+			      IS_GEN7(pI810)))
 /* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || \
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810))
+    IS_GEN6(pI810) || IS_GEN7(pI810))
+#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || \
+    IS_GEN6(pI810) || IS_GEN7(pI810))
 /* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || IS_GEN6(pI810))
+#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_GEN5(pI810) || \
+    IS_GEN6(pI810) || IS_GEN7(pI810))
 
 extern SymTabRec *intel_chipsets;
 

driver/xf86-video-intel/src/intel_module.c

@@ -119,13 +119,12 @@ static const SymTabRec _intel_chipsets[] = {
 	{PCI_CHIP_SANDYBRIDGE_M_GT2,		"Sandybridge Mobile (GT2)" },
 	{PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	"Sandybridge Mobile (GT2+)" },
 	{PCI_CHIP_SANDYBRIDGE_S_GT,		"Sandybridge Server" },
-#if 0
 	{PCI_CHIP_IVYBRIDGE_M_GT1,		"Ivybridge Mobile (GT1)" },
 	{PCI_CHIP_IVYBRIDGE_M_GT2,		"Ivybridge Mobile (GT2)" },
 	{PCI_CHIP_IVYBRIDGE_D_GT1,		"Ivybridge Desktop (GT1)" },
 	{PCI_CHIP_IVYBRIDGE_D_GT2,		"Ivybridge Desktop (GT2)" },
-	{PCI_CHIP_IVYBRIDGE_S_GT1,		"Ivybridge Server" },
+	{PCI_CHIP_IVYBRIDGE_S_GT1,		"Ivybridge Server (GT1)" },
-#endif
+	{PCI_CHIP_IVYBRIDGE_S_GT2,		"Ivybridge Server (GT2)" },
 	{-1,					NULL}
 };
 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
@@ -187,13 +186,12 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
 
-#if 0
 	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
-#endif
+	INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
 
 	{ 0, 0, 0 },
 };