Update to Intel driver 2.2.1. But change default accelmethod to XAA.

Tested by landry@, oga@, steven@, jakemsr@.

driver/xf86-video-intel/configure

@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59 for xf86-video-intel 2.2.0.90.
+# Generated by GNU Autoconf 2.59 for xf86-video-intel 2.2.1.
 #
 # Report bugs to <https://bugs.freedesktop.org/enter_bug.cgi?product=xorg>.
 #
@@ -423,8 +423,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
 # Identity of this package.
 PACKAGE_NAME='xf86-video-intel'
 PACKAGE_TARNAME='xf86-video-intel'
-PACKAGE_VERSION='2.2.0.90'
+PACKAGE_VERSION='2.2.1'
-PACKAGE_STRING='xf86-video-intel 2.2.0.90'
+PACKAGE_STRING='xf86-video-intel 2.2.1'
 PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg'
 
 ac_unique_file="Makefile.am"
@@ -990,7 +990,7 @@ if test "$ac_init_help" = "long"; then
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
-\`configure' configures xf86-video-intel 2.2.0.90 to adapt to many kinds of systems.
+\`configure' configures xf86-video-intel 2.2.1 to adapt to many kinds of systems.
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
@@ -1056,7 +1056,7 @@ fi
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
-     short | recursive ) echo "Configuration of xf86-video-intel 2.2.0.90:";;
+     short | recursive ) echo "Configuration of xf86-video-intel 2.2.1:";;
    esac
   cat <<\_ACEOF
 
@@ -1218,7 +1218,7 @@ fi
 test -n "$ac_init_help" && exit 0
 if $ac_init_version; then
   cat <<\_ACEOF
-xf86-video-intel configure 2.2.0.90
+xf86-video-intel configure 2.2.1
 generated by GNU Autoconf 2.59
 
 Copyright (C) 2003 Free Software Foundation, Inc.
@@ -1232,7 +1232,7 @@ cat >&5 <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
-It was created by xf86-video-intel $as_me 2.2.0.90, which was
+It was created by xf86-video-intel $as_me 2.2.1, which was
 generated by GNU Autoconf 2.59.  Invocation command line was
 
   $ $0 $@
@@ -1835,7 +1835,7 @@ fi
 
 # Define the identity of the package.
  PACKAGE='xf86-video-intel'
- VERSION='2.2.0.90'
+ VERSION='2.2.1'
 
 
 cat >>confdefs.h <<_ACEOF
@@ -21878,7 +21878,7 @@ _ASBOX
 } >&5
 cat >&5 <<_CSEOF
 
-This file was extended by xf86-video-intel $as_me 2.2.0.90, which was
+This file was extended by xf86-video-intel $as_me 2.2.1, which was
 generated by GNU Autoconf 2.59.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
@@ -21941,7 +21941,7 @@ _ACEOF
 
 cat >>$CONFIG_STATUS <<_ACEOF
 ac_cs_version="\\
-xf86-video-intel config.status 2.2.0.90
+xf86-video-intel config.status 2.2.1
 configured by $0, generated by GNU Autoconf 2.59,
   with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
 

driver/xf86-video-intel/configure.ac

@@ -22,7 +22,7 @@
 
 AC_PREREQ(2.57)
 AC_INIT([xf86-video-intel],
-        2.2.0.90,
+        2.2.1,
         [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
         xf86-video-intel)
 

driver/xf86-video-intel/src/common.h

@@ -441,6 +441,8 @@ extern int I810_DEBUG;
 #define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
 /* mark chipsets for using gfx VM offset for overlay */
 #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
+/* chipsets require graphics mem for hardware status page */
+#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810))
 
 #define GTT_PAGE_SIZE			KB(4)
 #define ROUND_TO(x, y)			(((x) + (y) - 1) / (y) * (y))

driver/xf86-video-intel/src/i810_reg.h

@@ -365,7 +365,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define CACHE_MODE_0           0x2120
 #define CACHE_MODE_1           0x2124
+#define MI_MODE		       0x209c
+#define MI_DISPLAY_POWER_DOWN  0x20e0
 #define MI_ARB_STATE           0x20e4
+#define MI_RDRET_STATE	       0x20fc
 
 /* Start addresses for each of the primary rings:
  */
@@ -976,6 +979,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define D_STATE			0x6104
 #define DSPCLK_GATE_D		0x6200
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
@@ -990,7 +1000,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
-# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
@@ -1995,6 +2005,32 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define PIPEAGCMAXGREEN		0x70014
 #define PIPEAGCMAXBLUE		0x70018
 #define PIPEASTAT		0x70024
+# define FIFO_UNDERRUN		(1 << 31)
+# define CRC_ERROR_ENABLE	(1 << 29)
+# define CRC_DONE_ENABLE	(1 << 28)
+# define GMBUS_EVENT_ENABLE	(1 << 27)
+# define VSYNC_INT_ENABLE	(1 << 25)
+# define DLINE_COMPARE_ENABLE	(1 << 24)
+# define DPST_EVENT_ENABLE	(1 << 23)
+# define LBLC_EVENT_ENABLE	(1 << 22)
+# define OFIELD_INT_ENABLE	(1 << 21)
+# define EFIELD_INT_ENABLE	(1 << 20)
+# define SVBLANK_INT_ENABLE	(1 << 18)
+# define VBLANK_INT_ENABLE	(1 << 17)
+# define OREG_UPDATE_ENABLE	(1 << 16)
+# define CRC_ERROR_INT_STATUS	(1 << 13)
+# define CRC_DONE_INT_STATUS	(1 << 12)
+# define GMBUS_INT_STATUS	(1 << 11)
+# define VSYNC_INT_STATUS	(1 << 9)
+# define DLINE_COMPARE_STATUS	(1 << 8)
+# define DPST_EVENT_STATUS	(1 << 7)
+# define LBLC_EVENT_STATUS	(1 << 6)
+# define OFIELD_INT_STATUS	(1 << 5)
+# define EFIELD_INT_STATUS	(1 << 4)
+# define SVBLANK_INT_STATUS	(1 << 2)
+# define VBLANK_INT_STATUS	(1 << 1)
+# define OREG_UPDATE_STATUS	(1 << 0)
+				 
 
 #define DSPARB			0x70030
 #define DSPFW1			0x70034
@@ -2134,7 +2170,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define I830_GMCH_MEM_64M	0x1
 #define I830_GMCH_MEM_128M	0
 
-#define I830_GMCH_GMS_MASK			0xF0
+#define I830_GMCH_GMS_MASK			0x70
 #define I830_GMCH_GMS_DISABLED			0x00
 #define I830_GMCH_GMS_LOCAL			0x10
 #define I830_GMCH_GMS_STOLEN_512		0x20
@@ -2145,7 +2181,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define I830_RDRAM_ND(x)			(((x) & 0x20) >> 5)
 #define I830_RDRAM_DDT(x)			(((x) & 0x18) >> 3)
 
-#define I855_GMCH_GMS_MASK			(0x7 << 4)
+#define I855_GMCH_GMS_MASK			(0xF << 4)
 #define I855_GMCH_GMS_DISABLED			0x00
 #define I855_GMCH_GMS_STOLEN_1M			(0x1 << 4)
 #define I855_GMCH_GMS_STOLEN_4M			(0x2 << 4)

driver/xf86-video-intel/src/i830.h

@@ -696,7 +696,9 @@ extern Bool I830DRIFinishScreenInit(ScreenPtr pScreen);
 extern void I830DRIUnlock(ScrnInfoPtr pScrn);
 extern Bool I830DRILock(ScrnInfoPtr pScrn);
 extern Bool I830DRISetVBlankInterrupt (ScrnInfoPtr pScrn, Bool on);
-Bool i830_update_dri_buffers(ScrnInfoPtr pScrn);
+extern Bool i830_update_dri_buffers(ScrnInfoPtr pScrn);
+extern Bool I830DRISetHWS(ScrnInfoPtr pScrn);
+extern Bool I830DRIInstIrqHandler(ScrnInfoPtr pScrn);
 #endif
 
 unsigned long intel_get_pixmap_offset(PixmapPtr pPix);
@@ -838,6 +840,7 @@ extern const int I830CopyROP[16];
 #define QUIRK_IGNORE_LVDS		0x00000002
 #define QUIRK_IGNORE_MACMINI_LVDS 	0x00000004
 #define QUIRK_PIPEA_FORCE		0x00000008
+#define QUIRK_IVCH_NEED_DVOB		0x00000010
 extern void i830_fixup_devices(ScrnInfoPtr);
 
 #endif /* _I830_H_ */

driver/xf86-video-intel/src/i830_debug.c

@@ -88,6 +88,61 @@ DEBUGSTRING(i830_debug_pipeconf)
     return XNFprintf("%s, %s", enabled, bit30);
 }
 
+DEBUGSTRING(i830_debug_pipestat)
+{
+    char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
+    char *_CRC_ERROR_ENABLE = val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
+    char *_CRC_DONE_ENABLE = val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
+    char *_GMBUS_EVENT_ENABLE = val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
+    char *_VSYNC_INT_ENABLE = val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
+    char *_DLINE_COMPARE_ENABLE = val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
+    char *_DPST_EVENT_ENABLE = val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
+    char *_LBLC_EVENT_ENABLE = val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
+    char *_OFIELD_INT_ENABLE = val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
+    char *_EFIELD_INT_ENABLE = val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
+    char *_SVBLANK_INT_ENABLE = val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
+    char *_VBLANK_INT_ENABLE = val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
+    char *_OREG_UPDATE_ENABLE = val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
+    char *_CRC_ERROR_INT_STATUS = val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
+    char *_CRC_DONE_INT_STATUS = val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
+    char *_GMBUS_INT_STATUS = val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
+    char *_VSYNC_INT_STATUS = val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
+    char *_DLINE_COMPARE_STATUS = val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
+    char *_DPST_EVENT_STATUS = val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
+    char *_LBLC_EVENT_STATUS = val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
+    char *_OFIELD_INT_STATUS = val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
+    char *_EFIELD_INT_STATUS = val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
+    char *_SVBLANK_INT_STATUS = val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
+    char *_VBLANK_INT_STATUS = val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
+    char *_OREG_UPDATE_STATUS = val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
+    return XNFprintf("status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+		     _FIFO_UNDERRUN,
+		     _CRC_ERROR_ENABLE,
+		     _CRC_DONE_ENABLE,
+		     _GMBUS_EVENT_ENABLE,
+		     _VSYNC_INT_ENABLE,
+		     _DLINE_COMPARE_ENABLE,
+		     _DPST_EVENT_ENABLE,
+		     _LBLC_EVENT_ENABLE,
+		     _OFIELD_INT_ENABLE,
+		     _EFIELD_INT_ENABLE,
+		     _SVBLANK_INT_ENABLE,
+		     _VBLANK_INT_ENABLE,
+		     _OREG_UPDATE_ENABLE,
+		     _CRC_ERROR_INT_STATUS,
+		     _CRC_DONE_INT_STATUS,
+		     _GMBUS_INT_STATUS,
+		     _VSYNC_INT_STATUS,
+		     _DLINE_COMPARE_STATUS,
+		     _DPST_EVENT_STATUS,
+		     _LBLC_EVENT_STATUS,
+		     _OFIELD_INT_STATUS,
+		     _EFIELD_INT_STATUS,
+		     _SVBLANK_INT_STATUS,
+		     _VBLANK_INT_STATUS,
+		     _OREG_UPDATE_STATUS);
+}
+
 DEBUGSTRING(i830_debug_hvtotal)
 {
     return XNFprintf("%d active, %d total", (val & 0xffff) + 1,
@@ -340,6 +395,76 @@ DEBUGSTRING(i830_debug_sdvo)
 		     enable, pipe, stall, detected, sdvoextra, gang);
 }
 
+DEBUGSTRING(i830_debug_dspclk_gate_d)
+{
+    char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
+    char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
+    char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
+    char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
+    char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
+    char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
+    char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
+    char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
+    char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
+    char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
+    char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
+    char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
+    char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
+    char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
+    char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
+    char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
+    char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
+    char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
+    char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
+    char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
+    char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
+    char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
+    char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
+    char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
+    char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
+    char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
+    char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
+    char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
+    char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
+    char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
+    char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
+    char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
+
+    return XNFprintf ("clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+		      DPUNIT_B,
+		      VSUNIT,
+		      VRHUNIT,
+		      VRDUNIT,
+		      AUDUNIT,
+		      DPUNIT_A,
+		      DPCUNIT,
+		      TVRUNIT,
+		      TVCUNIT,
+		      TVFUNIT,
+		      TVEUNIT,
+		      DVSUNIT,
+		      DSSUNIT,
+		      DDBUNIT,
+		      DPRUNIT,
+		      DPFUNIT,
+		      DPBMUNIT,
+		      DPLSUNIT,
+		      DPLUNIT,
+		      DPOUNIT,
+		      DPBUNIT,
+		      DCUNIT,
+		      DPUNIT,
+		      VRUNIT,
+		      OVHUNIT,
+		      DPIOUNIT,
+		      OVFUNIT,
+		      OVBUNIT,
+		      OVRUNIT,
+		      OVCUNIT,
+		      OVUUNIT,
+		      OVLUNIT);
+}
+
 #if 0
 DEBUGSTRING(i810_debug_fence_new)
 {
@@ -368,8 +493,9 @@ static struct i830SnapshotRec {
     DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
     DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
     DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
+    DEFINEREG(CACHE_MODE_0),
     DEFINEREG(D_STATE),
-    DEFINEREG(DSPCLK_GATE_D),
+    DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
     DEFINEREG(RENCLK_GATE_D1),
     DEFINEREG(RENCLK_GATE_D2),
 /*  DEFINEREG(RAMCLK_GATE_D),	CRL only */
@@ -408,6 +534,7 @@ static struct i830SnapshotRec {
     DEFINEREG(DSPATILEOFF),
     DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
     DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
+    DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
 
     DEFINEREG(FBC_CFB_BASE),
     DEFINEREG(FBC_LL_BASE),
@@ -440,6 +567,7 @@ static struct i830SnapshotRec {
     DEFINEREG(DSPBTILEOFF),
     DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
     DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
+    DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
 
     DEFINEREG2(FPB0, i830_debug_fp),
     DEFINEREG2(FPB1, i830_debug_fp),
@@ -494,6 +622,11 @@ static struct i830SnapshotRec {
     DEFINEREG(TV_H_CHROMA_0),
     DEFINEREG(TV_H_CHROMA_59),
 
+    DEFINEREG(MI_MODE),
+    DEFINEREG(MI_DISPLAY_POWER_DOWN),
+    DEFINEREG(MI_ARB_STATE),
+    DEFINEREG(MI_RDRET_STATE),
+    DEFINEREG(ECOSKPD),
 #if 0
     DEFINEREG2(FENCE_NEW + 0, i810_debug_fence_new),
     DEFINEREG2(FENCE_NEW + 8, i810_debug_fence_new),
@@ -601,6 +734,7 @@ static void i830DumpAR(ScrnInfoPtr pScrn)
     }
     INREG8(st01);
     OUTREG8(0x3c0, orig_arx);
+    INREG8(st01); /* switch back to index mode */
 }
 
 void i830DumpRegs (ScrnInfoPtr pScrn)

driver/xf86-video-intel/src/i830_display.c

@@ -637,6 +637,7 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
 
     /* Here we disable it to catch one->two pipe enabled configs */
     if (count > 1) {
+	if (i830_fb_compression_supported(pI830))
 	    i830_disable_fb_compression(crtc);
 	return FALSE;
     }
@@ -1639,10 +1640,11 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
 	    clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 			   DPLL_FPA01_P1_POST_DIV_SHIFT);
 
+	    /* if LVDS is dual-channel, p2 = 7 */
 	    if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
-		clock.p2 = I8XX_P2_LVDS_SLOW;
+		clock.p2 = 7;
 	    else
-		clock.p2 = I8XX_P2_LVDS_FAST;
+		clock.p2 = 14;
 
 	    if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
 		i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */

driver/xf86-video-intel/src/i830_dri.c

@@ -236,18 +236,18 @@ I830SetParam(ScrnInfoPtr pScrn, int param, int value)
    return TRUE;
 }
 
-static Bool
+Bool
-I830SetHWS(ScrnInfoPtr pScrn, int addr)
+I830DRISetHWS(ScrnInfoPtr pScrn)
 {
     I830Ptr pI830 = I830PTR(pScrn);
     drmI830HWS hws;
 
-    hws.addr = addr;
+    hws.addr = pI830->hw_status->offset;
 
     if (drmCommandWrite(pI830->drmSubFD, DRM_I830_HWS_PAGE_ADDR,
 		&hws, sizeof(drmI830HWS))) {
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-		"G33 status page initialization Failed\n");
+		"hw status page initialization Failed\n");
 	return FALSE;
     }
     return TRUE;
@@ -813,12 +813,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
       return FALSE;
    }
 
-   if (IS_G33CLASS(pI830)) {
-       if (!I830SetHWS(pScrn, pI830->hw_status->offset)) {
-	   DRICloseScreen(pScreen);
-	   return FALSE;
-       }
-   }
    /* init to zero to be safe */
    sarea->front_handle = 0;
    sarea->back_handle = 0;
@@ -881,17 +875,11 @@ I830DRIDoMappings(ScreenPtr pScreen)
 }
 
 Bool
-I830DRIResume(ScreenPtr pScreen)
+I830DRIInstIrqHandler(ScrnInfoPtr pScrn)
 {
-   ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
    I830Ptr pI830 = I830PTR(pScrn);
    I830DRIPtr pI830DRI = (I830DRIPtr) pI830->pDRIInfo->devPrivate;
 
-   DPRINTF(PFX, "I830DRIResume\n");
-
-   I830ResumeDma(pScrn);
-
-   {
    pI830DRI->irq = drmGetInterruptFromBusID(pI830->drmSubFD,
 #if XSERVER_LIBPCIACCESS
 					       ((pI830->PciInfo->domain << 8) |
@@ -913,14 +901,26 @@ I830DRIResume(ScreenPtr pScreen)
 	       "[drm] failure adding irq handler\n");
        pI830DRI->irq = 0;
        return FALSE;
-      }
+   } else
-      else
        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 	       "[drm] dma control initialized, using IRQ %d\n",
 	       pI830DRI->irq);
-   }
 
-   return FALSE;
+   return TRUE;
+}
+
+Bool
+I830DRIResume(ScreenPtr pScreen)
+{
+   ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+
+   DPRINTF(PFX, "I830DRIResume\n");
+
+   I830ResumeDma(pScrn);
+
+   I830DRIInstIrqHandler(pScrn);
+
+   return TRUE;
 }
 
 void
@@ -976,47 +976,16 @@ I830DestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
 Bool
 I830DRIFinishScreenInit(ScreenPtr pScreen)
 {
-   ScrnInfoPtr        pScrn = xf86Screens[pScreen->myNum];
-   I830Ptr pI830 = I830PTR(pScrn);
-
    DPRINTF(PFX, "I830DRIFinishScreenInit\n");
 
    if (!DRIFinishScreenInit(pScreen))
       return FALSE;
 
-   /* Okay now initialize the dma engine */
+   /* move irq initialize later in EnterVT, as then we
-   {
+    * would finish binding possible hw status page, which
-      I830DRIPtr pI830DRI = (I830DRIPtr) pI830->pDRIInfo->devPrivate;
+    * requires irq ctrl ioctl not be called that early.
-
+    */
-      pI830DRI->irq = drmGetInterruptFromBusID(pI830->drmSubFD,
-#if XSERVER_LIBPCIACCESS
-					       ((pI830->PciInfo->domain << 8) |
-						pI830->PciInfo->bus),
-					       pI830->PciInfo->dev,
-					       pI830->PciInfo->func
-#else
-					       ((pciConfigPtr) pI830->
-						PciInfo->thisCard)->busnum,
-					       ((pciConfigPtr) pI830->
-						PciInfo->thisCard)->devnum,
-					       ((pciConfigPtr) pI830->
-						PciInfo->thisCard)->funcnum
-#endif
-					       );
-
-      if (drmCtlInstHandler(pI830->drmSubFD, pI830DRI->irq)) {
-	 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-		    "[drm] failure adding irq handler\n");
-	 pI830DRI->irq = 0;
-	 DRICloseScreen(pScreen);
-	 return FALSE;
-      }
-      else
-	 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-		    "[drm] dma control initialized, using IRQ %d\n",
-		    pI830DRI->irq);
    return TRUE;
-   }
 }
 
 #ifdef DAMAGE

driver/xf86-video-intel/src/i830_driver.c

@@ -495,7 +495,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
    range = gtt_size + 4;
 
    if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+      switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
       case I855_GMCH_GMS_STOLEN_1M:
 	 memsize = MB(1) - KB(range);
 	 break;
@@ -2120,12 +2120,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
     * enabled if pipe A is actually on (otherwise we have a bug in the initial
     * state).
     */
-   if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_A) {
+   if ((pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_MASK) ==
+       DISPPLANE_SEL_PIPE_A) {
        OUTREG(DSPACNTR, pI830->saveDSPACNTR);
        OUTREG(DSPABASE, INREG(DSPABASE));
        i830WaitForVblank(pScrn);
    }
-   if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_A) {
+   if ((pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_MASK) ==
+       DISPPLANE_SEL_PIPE_A) {
        OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
        OUTREG(DSPBBASE, INREG(DSPBBASE));
        i830WaitForVblank(pScrn);
@@ -2177,12 +2179,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
        * Note that pipe B may be disabled, and in that case, the plane
        * should also be disabled or we must have had a bad initial state.
        */
-      if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_B) {
+      if ((pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_MASK) ==
+	  DISPPLANE_SEL_PIPE_B) {
 	  OUTREG(DSPACNTR, pI830->saveDSPACNTR);
 	  OUTREG(DSPABASE, INREG(DSPABASE));
 	  i830WaitForVblank(pScrn);
       }
-      if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_B) {
+      if ((pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_MASK) ==
+	  DISPPLANE_SEL_PIPE_B) {
 	  OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
 	  OUTREG(DSPBBASE, INREG(DSPBBASE));
 	  i830WaitForVblank(pScrn);
@@ -3186,6 +3190,22 @@ I830EnterVT(int scrnIndex, int flags)
 
 #ifdef XF86DRI
    if (pI830->directRenderingEnabled) {
+       /* HW status is fixed, we need to set it up before any drm
+	* operation which accessing that page, like irq install, etc.
+	*/
+       if (pI830->starting) {
+	   if (HWS_NEED_GFX(pI830) && !I830DRISetHWS(pScrn)) {
+		   xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+			   "Fail to setup hardware status page.\n");
+		   I830DRICloseScreen(pScrn->pScreen);
+		   return FALSE;
+	   }
+	   if (!I830DRIInstIrqHandler(pScrn)) {
+	       I830DRICloseScreen(pScrn->pScreen);
+	       return FALSE;
+	   }
+       }
+
       /* Update buffer offsets in sarea and mappings, since buffer offsets
        * may have changed.
        */

driver/xf86-video-intel/src/i830_dvo.c

@@ -83,7 +83,7 @@ struct _I830DVODriver i830_dvo_drivers[] =
 	.type = I830_OUTPUT_DVO_LVDS,
 	.modulename = "ivch",
 	.fntablename = "ivch_methods",
-	.dvo_reg = DVOB,
+	.dvo_reg = DVOA,
 	.address = 0x04, /* Might also be 0x44, 0x84, 0xc4 */
 	.symbols = ivch_symbols
     },
@@ -398,6 +398,7 @@ i830_dvo_get_current_mode (xf86OutputPtr output)
 void
 i830_dvo_init(ScrnInfoPtr pScrn)
 {
+    I830Ptr pI830 = I830PTR(pScrn);
     I830OutputPrivatePtr intel_output;
     int ret;
     int i;
@@ -431,6 +432,11 @@ i830_dvo_init(ScrnInfoPtr pScrn)
 	ret_ptr = NULL;
 	drv->vid_rec = LoaderSymbol(drv->fntablename);
 
+	if (!strcmp(drv->modulename, "ivch") &&
+	    pI830->quirk_flag & QUIRK_IVCH_NEED_DVOB) {
+	    drv->dvo_reg = DVOB;
+	}
+
 	/* Allow the I2C driver info to specify the GPIO to be used in
 	 * special cases, but otherwise default to what's defined in the spec.
 	 */

driver/xf86-video-intel/src/i830_memory.c

@@ -474,6 +474,9 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
 	/* Can't do TTM on stolen memory */
 	mmsize -= pI830->stolen_size;
 
+	if (HWS_NEED_GFX(pI830) && IS_IGD_GM(pI830))
+	    mmsize -= HWSTATUS_PAGE_SIZE;
+
 	/* Create the aperture allocation */
 	pI830->memory_manager =
 	    i830_allocate_aperture(pScrn, "DRI memory manager",
@@ -1636,16 +1639,20 @@ static Bool
 i830_allocate_hwstatus(ScrnInfoPtr pScrn)
 {
     I830Ptr pI830 = I830PTR(pScrn);
+    int flags;
 
     /* The current DRM will leak the HWS mapping if we update the address
      * after init (at best), so allocate it fixed for its lifetime
      * (i.e. not through buffer objects).
      */
-    pI830->hw_status = i830_allocate_memory(pScrn, "G33 hw status",
+    flags = NEED_LIFETIME_FIXED;
-	    HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, NEED_LIFETIME_FIXED);
+    if (IS_IGD_GM(pI830))
+	    flags |= NEED_NON_STOLEN;
+    pI830->hw_status = i830_allocate_memory(pScrn, "HW status",
+	    HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, flags);
     if (pI830->hw_status == NULL) {
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		"Failed to allocate hw status page for G33.\n");
+		"Failed to allocate hw status page.\n");
 	return FALSE;
     }
     return TRUE;
@@ -1658,7 +1665,7 @@ i830_allocate_3d_memory(ScrnInfoPtr pScrn)
 
     DPRINTF(PFX, "i830_allocate_3d_memory\n");
 
-    if (IS_G33CLASS(pI830)) {
+    if (HWS_NEED_GFX(pI830)) {
 	if (!i830_allocate_hwstatus(pScrn))
 	    return FALSE;
     }

driver/xf86-video-intel/src/i830_quirks.c

@@ -32,6 +32,9 @@
 
 #define SUBSYS_ANY (~0)
 
+#define DMIID_DIR "/sys/class/dmi/id/"
+#define DMIID_FILE(x) (DMIID_DIR # x)
+
 typedef struct {
     int chipType;
     int subsysVendor;
@@ -39,6 +42,125 @@ typedef struct {
     void (*hook)(I830Ptr);
 } i830_quirk, *i830_quirk_ptr;
 
+enum i830_dmi_data_t {
+    bios_vendor,
+    bios_version,
+    bios_date,
+    sys_vendor,
+    product_name,
+    product_version,
+    product_serial,
+    product_uuid,
+    board_vendor,
+    board_name,
+    board_version,
+    board_serial,
+    board_asset_tag,
+    chassis_vendor,
+    chassis_type,
+    chassis_version,
+    chassis_serial,
+    chassis_asset_tag,
+    dmi_data_max,
+};
+
+static char *i830_dmi_data[dmi_data_max];
+
+#define I830_DMI_FIELD_FUNC(field) \
+static void i830_dmi_store_##field(void) \
+{\
+    FILE *f = NULL;\
+    f = fopen(DMIID_FILE(field), "r");\
+    if (f == NULL) {\
+	xfree(i830_dmi_data[field]); i830_dmi_data[field] = NULL;\
+	return;\
+    }\
+    fread(i830_dmi_data[field], 64, 1, f);\
+    fclose(f);\
+}
+
+I830_DMI_FIELD_FUNC(bios_vendor);
+I830_DMI_FIELD_FUNC(bios_version);
+I830_DMI_FIELD_FUNC(bios_date);
+I830_DMI_FIELD_FUNC(sys_vendor);
+I830_DMI_FIELD_FUNC(product_name);
+I830_DMI_FIELD_FUNC(product_version);
+I830_DMI_FIELD_FUNC(product_serial);
+I830_DMI_FIELD_FUNC(product_uuid);
+I830_DMI_FIELD_FUNC(board_vendor);
+I830_DMI_FIELD_FUNC(board_name);
+I830_DMI_FIELD_FUNC(board_version);
+I830_DMI_FIELD_FUNC(board_serial);
+I830_DMI_FIELD_FUNC(board_asset_tag);
+I830_DMI_FIELD_FUNC(chassis_vendor);
+I830_DMI_FIELD_FUNC(chassis_type);
+I830_DMI_FIELD_FUNC(chassis_version);
+I830_DMI_FIELD_FUNC(chassis_serial);
+I830_DMI_FIELD_FUNC(chassis_asset_tag);
+
+static void i830_dmi_scan(void)
+{
+    int i;
+
+    for (i = 0; i < dmi_data_max; i++) {
+	i830_dmi_data[i] = xcalloc(64, sizeof(char));
+	if (!i830_dmi_data[i]) {
+	    int j;
+	    for (j = 0; j < i; j++) {
+		xfree(i830_dmi_data[j]);
+		i830_dmi_data[i] = NULL;
+	    }
+	    return;
+	}
+    }
+
+    i830_dmi_store_bios_vendor();
+    i830_dmi_store_bios_version();
+    i830_dmi_store_bios_date();
+    i830_dmi_store_sys_vendor();
+    i830_dmi_store_product_name();
+    i830_dmi_store_product_version();
+    i830_dmi_store_product_serial();
+    i830_dmi_store_product_uuid();
+    i830_dmi_store_board_vendor();
+    i830_dmi_store_board_name();
+    i830_dmi_store_board_version();
+    i830_dmi_store_board_serial();
+    i830_dmi_store_board_asset_tag();
+    i830_dmi_store_chassis_vendor();
+    i830_dmi_store_chassis_type();
+    i830_dmi_store_chassis_version();
+    i830_dmi_store_chassis_serial();
+    i830_dmi_store_chassis_asset_tag();
+}
+
+#define DMIID_DUMP(field) \
+    ErrorF("\t" # field ": %s", i830_dmi_data[field] ?\
+	    i830_dmi_data[field] : "unknown")
+
+static void i830_dmi_dump(void)
+{
+    ErrorF("i830_dmi_dump:\n");
+    DMIID_DUMP(bios_vendor);
+    DMIID_DUMP(bios_version);
+    DMIID_DUMP(bios_date);
+    DMIID_DUMP(sys_vendor);
+    DMIID_DUMP(product_name);
+    DMIID_DUMP(product_version);
+    DMIID_DUMP(product_serial);
+    DMIID_DUMP(product_uuid);
+    DMIID_DUMP(board_vendor);
+    DMIID_DUMP(board_name);
+    DMIID_DUMP(board_version);
+    DMIID_DUMP(board_serial);
+    DMIID_DUMP(board_asset_tag);
+    DMIID_DUMP(chassis_vendor);
+    DMIID_DUMP(chassis_type);
+    DMIID_DUMP(chassis_version);
+    DMIID_DUMP(chassis_serial);
+    DMIID_DUMP(chassis_asset_tag);
+}
+
 static void quirk_pipea_force (I830Ptr pI830)
 {
     pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
@@ -59,6 +181,28 @@ static void quirk_mac_mini (I830Ptr pI830)
     pI830->quirk_flag |= QUIRK_IGNORE_MACMINI_LVDS;
 }
 
+static void quirk_lenovo_tv_dmi (I830Ptr pI830)
+{
+    /* X60, X60s has no TV output.
+     * Z61 has S-video TV output.
+     * And they have same subsys ids...
+     *
+     * http://www-307.ibm.com/pc/support/site.wss/MIGR-45120.html
+     * http://www.thinkwiki.org/wiki/List_of_DMI_IDs
+     */
+    if (!i830_dmi_data[bios_version]) {
+	ErrorF("Failed to load DMI info, X60 TV quirk not applied.\n");
+	return;
+    }
+    if (!strncmp(i830_dmi_data[bios_version], "7B", 2))
+	pI830->quirk_flag |= QUIRK_IGNORE_TV;
+}
+
+static void quirk_ivch_dvob (I830Ptr pI830)
+{
+	pI830->quirk_flag |= QUIRK_IVCH_NEED_DVOB;
+}
+
 /* keep this list sorted by OEM, then by chip ID */
 static i830_quirk i830_quirk_list[] = {
     /* Aopen mini pc */
@@ -77,8 +221,8 @@ static i830_quirk i830_quirk_list[] = {
     /* Dell XPS 1330 */
     { PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
 
-    /* Lenovo X60s has no TV output */
+    /* Lenovo Napa TV (use dmi)*/
-    { PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_ignore_tv },
+    { PCI_CHIP_I945_GM, 0x17aa, SUBSYS_ANY, quirk_lenovo_tv_dmi },
     /* Lenovo T61 has no TV output */
     { PCI_CHIP_I965_GM, 0x17aa, 0x20b5, quirk_ignore_tv },
     /* Lenovo 3000 v200 */
@@ -91,6 +235,8 @@ static i830_quirk i830_quirk_list[] = {
 
     /* Toshiba Satellite U300 has no TV output */
     { PCI_CHIP_I965_GM, 0x1179, 0xff50, quirk_ignore_tv },
+    /* Toshiba i830M laptop (fix bug 11148) */
+    { PCI_CHIP_I830_M, 0x1179, 0xff00, quirk_ivch_dvob },
 
     /* Samsung Q35 has no TV output */
     { PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
@@ -103,6 +249,9 @@ static i830_quirk i830_quirk_list[] = {
     /* ThinkPad X40 needs pipe A force quirk */
     { PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
 
+    /* Sony vaio PCG-r600HFP (fix bug 13722) */
+    { PCI_CHIP_I830_M, 0x104d, 0x8100, quirk_ivch_dvob },
+
     { 0, 0, 0, NULL },
 };
 
@@ -110,6 +259,12 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
 {
     I830Ptr pI830 = I830PTR(scrn);
     i830_quirk_ptr p = i830_quirk_list;
+    int i;
+
+    i830_dmi_scan();
+
+    if (0)
+	i830_dmi_dump();
 
     while (p && p->chipType != 0) {
 	if (DEVICE_ID(pI830->PciInfo) == p->chipType &&
@@ -119,4 +274,8 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
 	    p->hook(pI830);
 	++p;
     }
+
+    for (i = 0; i < dmi_data_max; i++)
+	if (i830_dmi_data[i])
+	    xfree(i830_dmi_data[i]);
 }

driver/xf86-video-intel/src/i830_video.c

@@ -475,7 +475,6 @@ i830_overlay_continue(ScrnInfoPtr pScrn, Bool update_filter)
     OVERLAY_DEBUG("overlay_continue\n");
 }
 
-
 static void
 i830_overlay_off(ScrnInfoPtr pScrn)
 {