Update to xf86-video-ati 7.3.0. Tested by jsg@ ajacoutot@.
This commit is contained in:
matthieu
parent
7e0340c177
commit
2274e656b9
@ -1,3 +1,340 @@
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commit 0333f5bda27dc0ec2edc180c7a4dc9a432f13f97
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri Jan 24 10:19:49 2014 -0500
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radeon: bump version for release
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit fc4167f2a85d9cba65078d8fc6f08c7a619ad66e
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri Jan 24 10:17:08 2014 -0500
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Require glamor 0.6.0
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This is required for Xv support and a number of important
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performance improvements.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit f2a0a5cf6c5a21e2a02280e110a4eb8e6609dace
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Author: Michel Dänzer <michel.daenzer@amd.com>
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Date: Wed Jan 22 11:04:42 2014 +0900
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Don't require the glamoregl module to be pre-loaded with xserver >= 1.15
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The issues with loading it on demand have been fixed in xserver 1.15.
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Inspired by Jérôme Glisse on IRC.
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commit 3213df16d61302148be0088c8f93c6a5a88558f1
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Author: Michel Dänzer <michel.daenzer@amd.com>
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Date: Wed Jan 8 11:30:59 2014 +0900
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dri2: Make last_vblank_seq local unsigned to match dpms_last_seq
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Without this, I was occasionally running into gnome-shell hangs due to
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wildly off vblank sequence values. Doesn't seem to happen anymore with
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this change.
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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commit bcc454ea2fb239e13942270faec7801270615b9c
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon Jan 6 09:52:50 2014 -0500
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radeon/exa: Always use a scratch surface for UTS to vram
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If we don't, we may hit a buffer that crosses the
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visible vram boundary resulting in a sigbus when the
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CPU accesses the buffer beyond the PCI aperture.
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This will introduce an extra copy in certain cases.
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This is based on Michel's patch from bug 44099 updated
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for all asic families.
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Bug:
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https://bugs.freedesktop.org/show_bug.cgi?id=44099
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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commit 04ef035c9315b4a6fbf1b14720be87cee4099a9f
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Dec 24 15:14:35 2013 -0500
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drm/radeon: fix SUMO2 pci id
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0x9649 is sumo2, not sumo.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit bfbff3b246db509c820df17b8fcf5899882ffcfa
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Author: Robert Millan <rmh@freebsd.org>
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Date: Fri Dec 20 11:03:14 2013 +0000
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radeon: Restore kernel module load on FreeBSD.
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Since the introduction of a call to drmCheckModesettingSupported()
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in radeon_kernel_mode_enabled(), with abort condition if such call
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fails, the drmOpen() call in radeon_open_drm_master() no longer
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takes the responsibility of loading the radeon kernel module.
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However at least on FreeBSD (and GNU/kFreeBSD), X is still relied
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on to load the modules it needs. This commit restores the old
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behaviour of loading kernel modules on these systems.
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72852
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Signed-off-by: Robert Millan <rmh@freebsd.org>
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commit 796c9a0cb587f528326bede11fa3f3eb7d3edaf1
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Author: Robert Millan <rmh@freebsd.org>
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Date: Fri Dec 20 10:55:09 2013 +0000
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radeon: Set first parameter of drmOpen() to NULL
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Since the introduction of a call to drmCheckModesettingSupported()
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in radeon_kernel_mode_enabled(), with abort condition if such call
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fails, the first argument to drmOpen() call in radeon_open_drm_master()
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has become a no-op red herring.
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Such argument (a kernel module name) is supposed to result in load
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of specified kernel module. However, this will never happen. The
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problem is that if the code containing drmOpen() call is reached, it
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means that drmCheckModesettingSupported() check has previously
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succeeded, which implies the module is already loaded.
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So, drmOpen() will never load a kernel module. But it gives the
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impression that it will.
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In order to avoid this confusion, this commit replaces it with NULL,
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like xf86-video-intel driver does.
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72849
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Signed-off-by: Robert Millan <rmh@freebsd.org>
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commit d571d6af70ef27efd1ed6420eb892bdde963ed7a
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Sep 24 11:39:10 2013 -0400
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radeon/kms: add Hawaii pci ids
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit e38a92e00d015a6b80a1f3a16d58c61f084b066f
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Sep 24 11:35:00 2013 -0400
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radeon: add support for Hawaii
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Disabled by default until the acceleration code stablizes.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit e4cd0f4392ea11c93088ad429f36eaaf9bcbf505
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Wed Oct 30 15:21:26 2013 -0400
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radeon: enable tiling on SI by default (v2)
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Now that mesa 9.2 is out with support for tiling
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on SI asics, we can enable it here. Tiling improves
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memory bandwidth utilization.
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V2: update man page
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 3b38701a72fa1cad1e4610a2f4330b3da4cc6391
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Author: Vadim Girlin <vadimgirlin@gmail.com>
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Date: Fri Nov 1 10:36:39 2013 -0400
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radeon: disable 2D tiling on buffers < 128 pixels
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Seems to run into alignment problems with certain
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card configurations.
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bug:
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https://bugs.freedesktop.org/show_bug.cgi?id=70675
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 0c921edf0162fed616cea9d02e168b719243bcd2
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Author: Jerome Glisse <jglisse@redhat.com>
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Date: Wed Oct 30 13:01:02 2013 -0400
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radeon/glamor: with new pixmap for dri2 drawable no need to create new texture
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When creating a new pixmap/bo for dri2 drawable there is no need to create a
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new texture, instead the texture associated with the new pixmap should be use
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otherwise there is a missmatch between the bo backing the texture for the
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drawable and the bo used by dri2 client.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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commit f1dc677e79cd7a88d7379a934ebc7d87a3b18805
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Author: Christopher James Halse Rogers <raof@ubuntu.com>
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Date: Mon Sep 23 12:25:29 2013 -0700
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EXA/evergreen: Paranoia around linear tiling. (v2)
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The last two bytes of tiling_mode contain the actual tiling mode; the rest are
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extra tiling configuration bits. These configuration bits are not necessarily
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zero for a linear buffer, so mask them out before checking for linearity
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v2: Also fix up evergreen_textured_videofuncs.c
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agd5f: remove trailing whitespace
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Signed-off-by: Christopher James Halse Rogers <raof@ubuntu.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 67fb82a3f0759b171fea21b475a70fa825693570
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Oct 1 09:35:30 2013 -0400
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radeon: fix the non-glamor build harder...
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I need to stop pushing patches first thing in the morning.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit afc0374fdec3e24ece25805724459463e9a19f5e
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Oct 1 09:32:02 2013 -0400
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drm/radeon: fix non-glamor build
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 2d791370dfc5570eb74d7a1fb3baf4d4c8ecf243
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Author: Dave Airlie <airlied@redhat.com>
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Date: Mon Sep 23 07:57:15 2013 +0100
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radeon: use glamor Xv support if present.
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This creates adaptors using glamor if possible.
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Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit cbb99f659ee7b18ded0008a606e41ded38c1a194
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon Sep 30 08:55:16 2013 -0400
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Revert "radeon: add glamor Xv support (v2)"
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This causes problems if glamor doesn't have Xv support
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enabled. I just noticed that Dave has a better version,
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so use that instead.
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This reverts commit 4fc1fa920584ace2c84d75af82d06962d0c84ec8.
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commit 4fc1fa920584ace2c84d75af82d06962d0c84ec8
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Thu Sep 26 11:02:55 2013 -0400
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radeon: add glamor Xv support (v2)
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v2: guard new glamor Xv bits with USE_GLAMOR
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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commit 41dfe327ac8740ac2cd84def96b5947224e422e7
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Thu Sep 26 11:00:49 2013 -0400
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radeon: fix limit handling for cards with >4G of ram
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We can overflow the 32-bit limit.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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commit c45e728107269c6f51599dad4f6a02ccfef703f1
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Author: Michel Dänzer <michel.daenzer@amd.com>
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Date: Wed Sep 18 10:57:52 2013 +0200
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DRI2: Install client callback only once
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60182
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Acked-by: Alex Deucher <alexander.deucher@amd.com>
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commit b955ddd0d41801e4ca0c30a70a5d0b27c3f366c8
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon Sep 16 10:58:22 2013 -0400
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glamor: require 0.5.1 or newer
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0.5.1 fixes a number of issues.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 282587cd0709850e7bacb1d8307065d95dc2c97d
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Mon Sep 16 09:41:13 2013 -0400
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radeon: enable glamor by default (v4)
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It's required for newer asics, so enable it by
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default.
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v2: update the autoconf help. Require --disable-glamor
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to build without glamor support.
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v3: default to yes rather than auto
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v4: fix help text
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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commit fdb7563a5cbc736b09c2864b67a93b475c98b2bd
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Thu Jan 24 21:17:11 2013 -0500
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radeon/kms: add berlin pci ids
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit 8927d33f76ee12bc618fecfc59fc7ff1fcedcd5e
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Author: Mark Kettenis <kettenis@openbsd.org>
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Date: Thu Aug 22 10:32:46 2013 -0400
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Fix shadowfb on big-endian machines
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For shadowfb, the framebuffer needs to have the RADEON_TILING_SURFACE
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flag set, otherwise the appropriate byte swapping won't happen.
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See https://bugs.freedesktop.org/show_bug.cgi?id=66663
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Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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commit fa83d3d1636c315bc43dd622d407eb058e3ef976
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Author: Alex Deucher <alexander.deucher@amd.com>
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Date: Tue Aug 20 09:29:23 2013 -0400
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radeon: disallow glamor on pre-R600 asics
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I'm not sure they can handle the shaders properly, especially
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only older parts like r300.
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This will avoid display corruption problems reported by people
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using glamor on older asics by falling back to EXA if they try
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and enable glamor.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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commit d0323622ee9b97a5f246baffbb2c65930a78ed14
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Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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Date: Wed Aug 7 11:27:07 2013 +0200
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bump version post release
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Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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commit 9c97cca5c24409ca8447c99f051a12fd2d494e79
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Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
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Date: Wed Aug 7 10:48:17 2013 +0200
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@ -1,7 +1,9 @@
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# $OpenBSD: Makefile.bsd-wrapper,v 1.9 2013/08/12 04:13:31 jsg Exp $
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# $OpenBSD: Makefile.bsd-wrapper,v 1.10 2014/04/09 20:21:16 matthieu Exp $
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.include <bsd.xconf.mk>
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CONFIGURE_ARGS= --disable-glamor
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.if ${XENOCARA_BUILD_DRI:L} != "yes"
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CONFIGURE_ARGS+= --disable-dri
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.endif
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8
driver/xf86-video-ati/aclocal.m4
vendored
8
driver/xf86-video-ati/aclocal.m4
vendored
@ -9898,7 +9898,7 @@ dnl DEALINGS IN THE SOFTWARE.
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# See the "minimum version" comment for each macro you use to see what
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# version you require.
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m4_defun([XORG_MACROS_VERSION],[
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m4_define([vers_have], [1.16.2])
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m4_define([vers_have], [1.17.1])
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m4_define([maj_have], m4_substr(vers_have, 0, m4_index(vers_have, [.])))
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m4_define([maj_needed], m4_substr([$1], 0, m4_index([$1], [.])))
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m4_if(m4_cmp(maj_have, maj_needed), 0,,
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@ -11404,18 +11404,18 @@ fi
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found="no"
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m4_foreach([flag], m4_cdr($@), [
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if test $found = "no" ; then
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if test "x$xorg_testset_unknown_warning_option" = "xyes" ; then
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if test "x$xorg_testset_]CACHE_PREFIX[_unknown_warning_option" = "xyes" ; then
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PREFIX[FLAGS]="$PREFIX[FLAGS] -Werror=unknown-warning-option"
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fi
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if test "x$xorg_testset_unused_command_line_argument" = "xyes" ; then
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if test "x$xorg_testset_]CACHE_PREFIX[_unused_command_line_argument" = "xyes" ; then
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PREFIX[FLAGS]="$PREFIX[FLAGS] -Werror=unused-command-line-argument"
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fi
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PREFIX[FLAGS]="$PREFIX[FLAGS] ]flag["
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dnl Some hackery here since AC_CACHE_VAL can't handle a non-literal varname
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AC_MSG_CHECKING([if ]COMPILER[ supports]flag[])
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AC_MSG_CHECKING([if ]COMPILER[ supports ]flag[])
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cacheid=AS_TR_SH([xorg_cv_]CACHE_PREFIX[_flag_]flag[])
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AC_CACHE_VAL($cacheid,
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[AC_LINK_IFELSE([AC_LANG_PROGRAM([int i;])],
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444
driver/xf86-video-ati/configure
vendored
444
driver/xf86-video-ati/configure
vendored
File diff suppressed because it is too large
Load Diff
@ -23,7 +23,7 @@
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# Initialize Autoconf
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AC_PREREQ([2.60])
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AC_INIT([xf86-video-ati],
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[7.2.0],
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[7.3.0],
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[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
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[xf86-video-ati])
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@ -100,14 +100,14 @@ CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
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||||
AC_MSG_CHECKING([whether to include GLAMOR support])
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AC_ARG_ENABLE(glamor,
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AS_HELP_STRING([--enable-glamor],
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||||
[Enable glamor, a new GL-based acceleration [default=no]]),
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||||
AS_HELP_STRING([--disable-glamor],
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||||
[Disable glamor, a new GL-based acceleration [default=enabled]]),
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||||
[GLAMOR="$enableval"],
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||||
[GLAMOR=no])
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||||
[GLAMOR=yes])
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AC_MSG_RESULT([$GLAMOR])
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AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno)
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||||
if test "x$GLAMOR" != "xno"; then
|
||||
PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.3.1])
|
||||
PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0])
|
||||
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
|
||||
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
|
||||
fi
|
||||
|
||||
@ -205,6 +205,9 @@ KAVERI APUs
|
||||
.TP 12
|
||||
.B KABINI
|
||||
KABINI APUs
|
||||
.TP 12
|
||||
.B HAWAII
|
||||
Radeon R9 series
|
||||
.PD
|
||||
.SH CONFIGURATION DETAILS
|
||||
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
|
||||
@ -245,7 +248,7 @@ this enables 1D tiling mode.
|
||||
The default value is
|
||||
.B on
|
||||
for R/RV3XX, R/RV4XX, R/RV5XX, RS6XX, RS740, R/RV6XX, R/RV7XX, RS780, RS880,
|
||||
EVERGREEN, CAYMAN, and ARUBA and
|
||||
EVERGREEN, CAYMAN, ARUBA, and Southern Islands and
|
||||
.B off
|
||||
for R/RV/RS1XX, R/RV/RS2XX, RS3XX, and RS690/RS780/RS880 when fast fb feature is enabled.
|
||||
.TP
|
||||
@ -254,11 +257,11 @@ The framebuffer can be addressed either in linear, 1D, or 2D tiled modes. 2D til
|
||||
provide significant performance benefits over 1D tiling with 3D applications. Tiling
|
||||
will be disabled if the drm module is too old or if the current display configuration
|
||||
does not support it. KMS ColorTiling2D is only supported on R600 and newer chips and requires
|
||||
Mesa 9.0 or newer.
|
||||
Mesa 9.0 or newer for R6xx-ARUBA and Mesa 9.2 or newer for Southern Islands.
|
||||
.br
|
||||
The default value is
|
||||
.B on
|
||||
for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, and ARUBA.
|
||||
for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, ARUBA, and Southern Islands.
|
||||
.TP
|
||||
.BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
|
||||
Enable DRI2 page flipping. The default is
|
||||
|
||||
@ -460,7 +460,7 @@
|
||||
#define PCI_CHIP_SUMO2_9645 0x9645
|
||||
#define PCI_CHIP_SUMO_9647 0x9647
|
||||
#define PCI_CHIP_SUMO_9648 0x9648
|
||||
#define PCI_CHIP_SUMO_9649 0x9649
|
||||
#define PCI_CHIP_SUMO2_9649 0x9649
|
||||
#define PCI_CHIP_SUMO_964A 0x964A
|
||||
#define PCI_CHIP_SUMO_964B 0x964B
|
||||
#define PCI_CHIP_SUMO_964C 0x964C
|
||||
@ -722,3 +722,36 @@
|
||||
#define PCI_CHIP_KABINI_983D 0x983D
|
||||
#define PCI_CHIP_KABINI_983E 0x983E
|
||||
#define PCI_CHIP_KABINI_983F 0x983F
|
||||
#define PCI_CHIP_KAVERI_1304 0x1304
|
||||
#define PCI_CHIP_KAVERI_1305 0x1305
|
||||
#define PCI_CHIP_KAVERI_1306 0x1306
|
||||
#define PCI_CHIP_KAVERI_1307 0x1307
|
||||
#define PCI_CHIP_KAVERI_1309 0x1309
|
||||
#define PCI_CHIP_KAVERI_130A 0x130A
|
||||
#define PCI_CHIP_KAVERI_130B 0x130B
|
||||
#define PCI_CHIP_KAVERI_130C 0x130C
|
||||
#define PCI_CHIP_KAVERI_130D 0x130D
|
||||
#define PCI_CHIP_KAVERI_130E 0x130E
|
||||
#define PCI_CHIP_KAVERI_130F 0x130F
|
||||
#define PCI_CHIP_KAVERI_1310 0x1310
|
||||
#define PCI_CHIP_KAVERI_1311 0x1311
|
||||
#define PCI_CHIP_KAVERI_1312 0x1312
|
||||
#define PCI_CHIP_KAVERI_1313 0x1313
|
||||
#define PCI_CHIP_KAVERI_1315 0x1315
|
||||
#define PCI_CHIP_KAVERI_1316 0x1316
|
||||
#define PCI_CHIP_KAVERI_1317 0x1317
|
||||
#define PCI_CHIP_KAVERI_131B 0x131B
|
||||
#define PCI_CHIP_KAVERI_131C 0x131C
|
||||
#define PCI_CHIP_KAVERI_131D 0x131D
|
||||
#define PCI_CHIP_HAWAII_67A0 0x67A0
|
||||
#define PCI_CHIP_HAWAII_67A1 0x67A1
|
||||
#define PCI_CHIP_HAWAII_67A2 0x67A2
|
||||
#define PCI_CHIP_HAWAII_67A8 0x67A8
|
||||
#define PCI_CHIP_HAWAII_67A9 0x67A9
|
||||
#define PCI_CHIP_HAWAII_67AA 0x67AA
|
||||
#define PCI_CHIP_HAWAII_67B0 0x67B0
|
||||
#define PCI_CHIP_HAWAII_67B1 0x67B1
|
||||
#define PCI_CHIP_HAWAII_67B8 0x67B8
|
||||
#define PCI_CHIP_HAWAII_67B9 0x67B9
|
||||
#define PCI_CHIP_HAWAII_67BA 0x67BA
|
||||
#define PCI_CHIP_HAWAII_67BE 0x67BE
|
||||
|
||||
@ -1478,7 +1478,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
|
||||
ScreenPtr screen = xf86ScrnToScreen(scrn);
|
||||
uint32_t old_fb_id;
|
||||
int i, pitch, old_width, old_height, old_pitch;
|
||||
int screen_size;
|
||||
uint32_t screen_size;
|
||||
int cpp = info->pixel_bytes;
|
||||
struct radeon_bo *front_bo;
|
||||
struct radeon_surface surface;
|
||||
@ -2014,6 +2014,9 @@ void drmmode_uevent_fini(ScrnInfoPtr scrn, drmmode_ptr drmmode)
|
||||
udev_monitor_unref(drmmode->uevent_monitor);
|
||||
udev_unref(u);
|
||||
}
|
||||
if (info->ChipFamily < CHIP_FAMILY_R600 &&
|
||||
info->r600_shadow_fb && tiling_flags)
|
||||
tiling_flags |= RADEON_TILING_SURFACE;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -156,7 +156,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
|
||||
if (accel_state->planemask & 0xff000000)
|
||||
cb_conf.pmask |= 8; /* A */
|
||||
cb_conf.rop = accel_state->rop;
|
||||
if (accel_state->dst_obj.tiling_flags == 0) {
|
||||
if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR) {
|
||||
cb_conf.array_mode = 0;
|
||||
cb_conf.non_disp_tiling = 1;
|
||||
}
|
||||
@ -335,7 +336,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 0;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
@ -378,7 +380,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
|
||||
if (accel_state->planemask & 0xff000000)
|
||||
cb_conf.pmask |= 8; /* A */
|
||||
cb_conf.rop = accel_state->rop;
|
||||
if (accel_state->dst_obj.tiling_flags == 0) {
|
||||
if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR) {
|
||||
cb_conf.array_mode = 0;
|
||||
cb_conf.non_disp_tiling = 1;
|
||||
}
|
||||
@ -1001,7 +1004,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
|
||||
tex_res.base_level = 0;
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
if (accel_state->src_obj[unit].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 0;
|
||||
evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
|
||||
|
||||
@ -1449,7 +1453,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
|
||||
cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
|
||||
cb_conf.rop = 3;
|
||||
cb_conf.pmask = 0xf;
|
||||
if (accel_state->dst_obj.tiling_flags == 0) {
|
||||
if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR) {
|
||||
cb_conf.array_mode = 0;
|
||||
cb_conf.non_disp_tiling = 1;
|
||||
}
|
||||
@ -1653,13 +1658,14 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
|
||||
if (!driver_priv || !driver_priv->bo)
|
||||
return FALSE;
|
||||
|
||||
/* If we know the BO won't be busy, don't bother with a scratch */
|
||||
/* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
|
||||
copy_dst = driver_priv->bo;
|
||||
copy_pitch = pDst->devKind;
|
||||
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
|
||||
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
|
||||
flush = FALSE;
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
|
||||
!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
|
||||
goto copy;
|
||||
}
|
||||
}
|
||||
|
||||
@ -246,7 +246,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
@ -279,7 +280,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
tex_res.base = pPriv->planev_offset;
|
||||
tex_res.mip_base = pPriv->planev_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
@ -302,7 +304,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
tex_res.base = pPriv->planeu_offset;
|
||||
tex_res.mip_base = pPriv->planeu_offset;
|
||||
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
@ -342,7 +345,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
tex_res.last_level = 0;
|
||||
tex_res.perf_modulation = 0;
|
||||
tex_res.interlaced = 0;
|
||||
if (accel_state->src_obj[0].tiling_flags == 0)
|
||||
if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR)
|
||||
tex_res.array_mode = 1;
|
||||
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
|
||||
|
||||
@ -397,7 +401,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
|
||||
cb_conf.blend_clamp = 1;
|
||||
cb_conf.pmask = 0xf;
|
||||
cb_conf.rop = 3;
|
||||
if (accel_state->dst_obj.tiling_flags == 0) {
|
||||
if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
|
||||
RADEON_TILING_LINEAR) {
|
||||
cb_conf.array_mode = 1;
|
||||
cb_conf.non_disp_tiling = 1;
|
||||
}
|
||||
|
||||
@ -461,7 +461,7 @@
|
||||
"0x9645","SUMO2_9645","SUMO2",1,1,,,1,"SUMO2"
|
||||
"0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9649","SUMO_9649","SUMO",1,1,,,1,"SUMO"
|
||||
"0x9649","SUMO2_9649","SUMO2",1,1,,,1,"SUMO2"
|
||||
"0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO"
|
||||
"0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO"
|
||||
"0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO"
|
||||
@ -723,3 +723,36 @@
|
||||
"0x983D","KABINI_983D","KABINI",,1,,,1,"KABINI"
|
||||
"0x983E","KABINI_983E","KABINI",,1,,,1,"KABINI"
|
||||
"0x983F","KABINI_983F","KABINI",,1,,,1,"KABINI"
|
||||
"0x1304","KAVERI_1304","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x1305","KAVERI_1305","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1306","KAVERI_1306","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x1307","KAVERI_1307","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1309","KAVERI_1309","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130A","KAVERI_130A","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130B","KAVERI_130B","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130C","KAVERI_130C","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130D","KAVERI_130D","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130E","KAVERI_130E","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x130F","KAVERI_130F","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1310","KAVERI_1310","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1311","KAVERI_1311","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1312","KAVERI_1312","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1313","KAVERI_1313","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1315","KAVERI_1315","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1316","KAVERI_1316","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x1317","KAVERI_1317","KAVERI",1,1,,,1,"KAVERI"
|
||||
"0x131B","KAVERI_131B","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x131C","KAVERI_131C","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x131D","KAVERI_131D","KAVERI",,1,,,1,"KAVERI"
|
||||
"0x67A0","HAWAII_67A0","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A1","HAWAII_67A1","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A2","HAWAII_67A2","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A8","HAWAII_67A8","HAWAII",,,,,,"HAWAII"
|
||||
"0x67A9","HAWAII_67A9","HAWAII",,,,,,"HAWAII"
|
||||
"0x67AA","HAWAII_67AA","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B0","HAWAII_67B0","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B1","HAWAII_67B1","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B8","HAWAII_67B8","HAWAII",,,,,,"HAWAII"
|
||||
"0x67B9","HAWAII_67B9","HAWAII",,,,,,"HAWAII"
|
||||
"0x67BA","HAWAII_67BA","HAWAII",,,,,,"HAWAII"
|
||||
"0x67BE","HAWAII_67BE","HAWAII",,,,,,"HAWAII"
|
||||
|
||||
|
@ -1538,13 +1538,14 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
|
||||
if (!driver_priv || !driver_priv->bo)
|
||||
return FALSE;
|
||||
|
||||
/* If we know the BO won't be busy, don't bother with a scratch */
|
||||
/* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
|
||||
copy_dst = driver_priv->bo;
|
||||
copy_pitch = pDst->devKind;
|
||||
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
|
||||
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
|
||||
flush = FALSE;
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
|
||||
!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
|
||||
goto copy;
|
||||
}
|
||||
/* use cpu copy for fast fb access */
|
||||
|
||||
@ -524,7 +524,7 @@ extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn);
|
||||
extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
|
||||
int num, const char *file,
|
||||
const char *func, int line);
|
||||
void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size);
|
||||
void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size);
|
||||
extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
|
||||
|
||||
drmVBlankSeqType radeon_populate_vbl_request_type(xf86CrtcPtr crtc);
|
||||
|
||||
@ -124,7 +124,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
|
||||
surface.last_level = 0;
|
||||
surface.bpe = cpp;
|
||||
surface.nsamples = 1;
|
||||
if (height < 64) {
|
||||
if (height < 128) {
|
||||
/* disable 2d tiling for small surface to work around
|
||||
* the fact that ddx align height to 8 pixel for old
|
||||
* obscure reason i can't remember
|
||||
|
||||
@ -380,7 +380,7 @@ static RADEONCardInfo RADEONCards[] = {
|
||||
{ 0x9645, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
|
||||
{ 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9649, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
|
||||
{ 0x9649, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
|
||||
{ 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
{ 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
|
||||
@ -642,4 +642,37 @@ static RADEONCardInfo RADEONCards[] = {
|
||||
{ 0x983D, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983E, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x983F, CHIP_FAMILY_KABINI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1304, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x1305, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1306, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x1307, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1309, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130A, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130B, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130C, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130D, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130E, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x130F, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1310, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1311, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1312, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1313, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1315, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1316, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x1317, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 },
|
||||
{ 0x131B, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x131C, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x131D, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
|
||||
{ 0x67A0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A2, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67A9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67AA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67B9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67BA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
{ 0x67BE, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
@ -380,7 +380,7 @@ SymTabRec RADEONChipsets[] = {
|
||||
{ PCI_CHIP_SUMO2_9645, "SUMO2" },
|
||||
{ PCI_CHIP_SUMO_9647, "SUMO" },
|
||||
{ PCI_CHIP_SUMO_9648, "SUMO" },
|
||||
{ PCI_CHIP_SUMO_9649, "SUMO" },
|
||||
{ PCI_CHIP_SUMO2_9649, "SUMO2" },
|
||||
{ PCI_CHIP_SUMO_964A, "SUMO" },
|
||||
{ PCI_CHIP_SUMO_964B, "SUMO" },
|
||||
{ PCI_CHIP_SUMO_964C, "SUMO" },
|
||||
@ -642,5 +642,38 @@ SymTabRec RADEONChipsets[] = {
|
||||
{ PCI_CHIP_KABINI_983D, "KABINI" },
|
||||
{ PCI_CHIP_KABINI_983E, "KABINI" },
|
||||
{ PCI_CHIP_KABINI_983F, "KABINI" },
|
||||
{ PCI_CHIP_KAVERI_1304, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1305, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1306, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1307, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1309, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130A, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130B, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130C, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130D, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130E, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_130F, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1310, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1311, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1312, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1313, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1315, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1316, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_1317, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_131B, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_131C, "KAVERI" },
|
||||
{ PCI_CHIP_KAVERI_131D, "KAVERI" },
|
||||
{ PCI_CHIP_HAWAII_67A0, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67A1, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67A2, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67A8, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67A9, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67AA, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67B0, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67B1, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67B8, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67B9, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67BA, "HAWAII" },
|
||||
{ PCI_CHIP_HAWAII_67BE, "HAWAII" },
|
||||
{ -1, NULL }
|
||||
};
|
||||
|
||||
@ -66,6 +66,10 @@
|
||||
|
||||
#define FALLBACK_SWAP_DELAY 16
|
||||
|
||||
#ifdef USE_GLAMOR
|
||||
#include <glamor.h>
|
||||
#endif
|
||||
|
||||
typedef DRI2BufferPtr BufferPtr;
|
||||
|
||||
struct dri2_buffer_priv {
|
||||
@ -89,7 +93,6 @@ static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
|
||||
PixmapPtr old = get_drawable_pixmap(drawable);
|
||||
#ifdef USE_GLAMOR
|
||||
ScreenPtr screen = drawable->pScreen;
|
||||
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
|
||||
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
|
||||
GCPtr gc;
|
||||
|
||||
@ -118,21 +121,13 @@ static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
|
||||
}
|
||||
|
||||
radeon_set_pixmap_private(pixmap, NULL);
|
||||
screen->DestroyPixmap(pixmap);
|
||||
|
||||
/* And redirect the pixmap to the new bo (for 3D). */
|
||||
glamor_egl_exchange_buffers(old, pixmap);
|
||||
radeon_set_pixmap_private(old, priv);
|
||||
screen->DestroyPixmap(pixmap);
|
||||
old->refcnt++;
|
||||
|
||||
/* This creating should not fail, as we already created its
|
||||
* successfully. But if it happens, we put a warning indicator
|
||||
* here, and the old pixmap will still be a glamor pixmap, and
|
||||
* latter the pixmap_flink will get a 0 name, then the X server
|
||||
* will pass a BadAlloc to the client.*/
|
||||
if (!radeon_glamor_create_textured_pixmap(old))
|
||||
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
|
||||
"Failed to get DRI drawable for glamor pixmap.\n");
|
||||
|
||||
screen->ModifyPixmapHeader(old,
|
||||
old->drawable.width,
|
||||
old->drawable.height,
|
||||
@ -520,6 +515,8 @@ typedef struct _DRI2ClientEvents {
|
||||
|
||||
#if HAS_DEVPRIVATEKEYREC
|
||||
|
||||
static int DRI2InfoCnt;
|
||||
|
||||
static DevPrivateKeyRec DRI2ClientEventsPrivateKeyRec;
|
||||
#define DRI2ClientEventsPrivateKey (&DRI2ClientEventsPrivateKeyRec)
|
||||
|
||||
@ -893,7 +890,7 @@ CARD32 radeon_dri2_extrapolate_msc_delay(xf86CrtcPtr crtc, CARD64 *target_msc,
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int nominal_frame_rate = drmmode_crtc->dpms_last_fps;
|
||||
CARD64 last_vblank_ust = drmmode_crtc->dpms_last_ust;
|
||||
int last_vblank_seq = drmmode_crtc->dpms_last_seq;
|
||||
uint32_t last_vblank_seq = drmmode_crtc->dpms_last_seq;
|
||||
int interpolated_vblanks = drmmode_crtc->interpolated_vblanks;
|
||||
int target_seq;
|
||||
CARD64 now, target_time, delta_t;
|
||||
@ -1543,7 +1540,6 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
DRI2InfoRec dri2_info = { 0 };
|
||||
#ifdef USE_DRI2_SCHEDULING
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
|
||||
const char *driverNames[2];
|
||||
Bool scheduling_works = TRUE;
|
||||
#endif
|
||||
@ -1607,7 +1603,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
|
||||
dri2_info.driverNames = driverNames;
|
||||
driverNames[0] = driverNames[1] = dri2_info.driverName;
|
||||
|
||||
if (pRADEONEnt->dri2_info_cnt == 0) {
|
||||
if (DRI2InfoCnt == 0) {
|
||||
#if HAS_DIXREGISTERPRIVATEKEY
|
||||
if (!dixRegisterPrivateKey(DRI2ClientEventsPrivateKey,
|
||||
PRIVATE_CLIENT, sizeof(DRI2ClientEventsRec))) {
|
||||
@ -1627,7 +1623,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
|
||||
AddCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0);
|
||||
}
|
||||
|
||||
pRADEONEnt->dri2_info_cnt++;
|
||||
DRI2InfoCnt++;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1646,12 +1642,12 @@ void radeon_dri2_close_screen(ScreenPtr pScreen)
|
||||
{
|
||||
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
#ifdef USE_DRI2_SCHEDULING
|
||||
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
|
||||
|
||||
if (--pRADEONEnt->dri2_info_cnt == 0)
|
||||
#ifdef USE_DRI2_SCHEDULING
|
||||
if (--DRI2InfoCnt == 0)
|
||||
DeleteCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0);
|
||||
#endif
|
||||
|
||||
DRI2CloseScreen(pScreen);
|
||||
drmFree(info->dri2.device_name);
|
||||
}
|
||||
|
||||
@ -800,6 +800,8 @@ struct drm_radeon_gem_create {
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
#define RADEON_TILING_MASK 0xff
|
||||
#define RADEON_TILING_LINEAR 0x0
|
||||
#define RADEON_TILING_MACRO 0x1
|
||||
#define RADEON_TILING_MICRO 0x2
|
||||
#define RADEON_TILING_SWAP_16BIT 0x4
|
||||
|
||||
@ -403,13 +403,14 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
|
||||
}
|
||||
#endif
|
||||
|
||||
/* If we know the BO won't be busy, don't bother with a scratch */
|
||||
/* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
|
||||
copy_dst = driver_priv->bo;
|
||||
copy_pitch = pDst->devKind;
|
||||
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
|
||||
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
|
||||
flush = FALSE;
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
|
||||
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
|
||||
!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
|
||||
goto copy;
|
||||
}
|
||||
/* use cpu copy for fast fb access */
|
||||
|
||||
@ -93,18 +93,26 @@ radeon_glamor_pre_init(ScrnInfoPtr scrn)
|
||||
if (s && strcasecmp(s, "glamor") != 0)
|
||||
return FALSE;
|
||||
|
||||
if (info->ChipFamily < CHIP_FAMILY_R600) {
|
||||
xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING,
|
||||
"glamor requires R600 or newer GPU, disabling.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (scrn->depth < 24) {
|
||||
xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING,
|
||||
"glamor requires depth >= 24, disabling.\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,15,0,0,0)
|
||||
if (!xf86LoaderCheckSymbol("glamor_egl_init")) {
|
||||
xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING,
|
||||
"glamor requires Load \"glamoregl\" in "
|
||||
"Section \"Module\", disabling.\n");
|
||||
return FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Load glamor module */
|
||||
if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) {
|
||||
@ -349,3 +357,8 @@ radeon_glamor_flush(ScrnInfoPtr pScrn)
|
||||
if (info->use_glamor)
|
||||
glamor_block_handler(pScrn->pScreen);
|
||||
}
|
||||
|
||||
XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt)
|
||||
{
|
||||
return glamor_xv_init(pScreen, num_adapt);
|
||||
}
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#ifndef RADEON_GLAMOR_H
|
||||
#define RADEON_GLAMOR_H
|
||||
|
||||
#include "xf86xv.h"
|
||||
#ifdef USE_GLAMOR
|
||||
|
||||
#include "radeon_surface.h"
|
||||
@ -43,6 +44,8 @@ void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
|
||||
|
||||
Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap);
|
||||
|
||||
XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt);
|
||||
|
||||
struct radeon_pixmap {
|
||||
struct radeon_surface surface;
|
||||
struct radeon_bo *bo;
|
||||
@ -88,6 +91,7 @@ static inline Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap) { return
|
||||
|
||||
static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
|
||||
|
||||
static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; }
|
||||
#endif
|
||||
|
||||
#endif /* RADEON_GLAMOR_H */
|
||||
|
||||
@ -489,7 +489,8 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
|
||||
info->is_fast_fb = TRUE;
|
||||
}
|
||||
|
||||
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
|
||||
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL,
|
||||
info->ChipFamily == CHIP_FAMILY_HAWAII) ||
|
||||
(!RADEONIsAccelWorking(pScrn))) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
|
||||
"GPU accel disabled or not working, using shadowfb for KMS\n");
|
||||
@ -606,7 +607,7 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
|
||||
dev->domain, dev->bus, dev->dev, dev->func);
|
||||
#endif
|
||||
|
||||
info->dri2.drm_fd = drmOpen("radeon", busid);
|
||||
info->dri2.drm_fd = drmOpen(NULL, busid);
|
||||
if (info->dri2.drm_fd == -1) {
|
||||
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
|
||||
@ -860,17 +861,17 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
|
||||
Bool colorTilingDefault =
|
||||
xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
|
||||
info->ChipFamily >= CHIP_FAMILY_R300 &&
|
||||
/* this ARUBA check could be removed sometime after a big mesa release
|
||||
/* this check could be removed sometime after a big mesa release
|
||||
* with proper bit, in the meantime you need to set tiling option in
|
||||
* xorg configuration files
|
||||
*/
|
||||
info->ChipFamily <= CHIP_FAMILY_ARUBA &&
|
||||
info->ChipFamily <= CHIP_FAMILY_HAINAN &&
|
||||
!info->is_fast_fb;
|
||||
|
||||
/* 2D color tiling */
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600) {
|
||||
info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D,
|
||||
info->ChipFamily <= CHIP_FAMILY_ARUBA);
|
||||
info->ChipFamily <= CHIP_FAMILY_HAINAN);
|
||||
}
|
||||
|
||||
if (info->ChipFamily >= CHIP_FAMILY_R600) {
|
||||
@ -1321,7 +1322,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
|
||||
*/
|
||||
/* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
|
||||
#endif
|
||||
if (!info->use_glamor && info->r600_shadow_fb == FALSE) {
|
||||
if (info->r600_shadow_fb == FALSE) {
|
||||
/* Init Xv */
|
||||
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
|
||||
"Initializing Xv\n");
|
||||
@ -1450,7 +1451,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
|
||||
int cpp = info->pixel_bytes;
|
||||
int screen_size;
|
||||
uint32_t screen_size;
|
||||
int pitch, base_align;
|
||||
uint32_t tiling_flags = 0;
|
||||
struct radeon_surface surface;
|
||||
@ -1600,11 +1601,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
|
||||
void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size)
|
||||
{
|
||||
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
|
||||
RADEONInfoPtr info = RADEONPTR(pScrn);
|
||||
int remain_size_bytes;
|
||||
uint64_t remain_size_bytes;
|
||||
int c;
|
||||
|
||||
for (c = 0; c < xf86_config->num_crtc; c++) {
|
||||
@ -1615,9 +1616,13 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
|
||||
|
||||
remain_size_bytes = info->vram_size - new_fb_size;
|
||||
remain_size_bytes = (remain_size_bytes / 10) * 9;
|
||||
radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes);
|
||||
if (remain_size_bytes > 0xffffffff)
|
||||
remain_size_bytes = 0xffffffff;
|
||||
radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM,
|
||||
(uint32_t)remain_size_bytes);
|
||||
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n",
|
||||
(uint32_t)remain_size_bytes / 1024);
|
||||
}
|
||||
|
||||
/* Used to disallow modes that are not supported by the hardware */
|
||||
|
||||
@ -380,7 +380,7 @@ static PciChipsets RADEONPciChipsets[] = {
|
||||
{ PCI_CHIP_SUMO2_9645, PCI_CHIP_SUMO2_9645, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_9649, PCI_CHIP_SUMO_9649, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO2_9649, PCI_CHIP_SUMO2_9649, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA },
|
||||
@ -642,5 +642,38 @@ static PciChipsets RADEONPciChipsets[] = {
|
||||
{ PCI_CHIP_KABINI_983D, PCI_CHIP_KABINI_983D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983E, PCI_CHIP_KABINI_983E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KABINI_983F, PCI_CHIP_KABINI_983F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1307, PCI_CHIP_KAVERI_1307, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1309, PCI_CHIP_KAVERI_1309, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130A, PCI_CHIP_KAVERI_130A, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130B, PCI_CHIP_KAVERI_130B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130C, PCI_CHIP_KAVERI_130C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130D, PCI_CHIP_KAVERI_130D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130E, PCI_CHIP_KAVERI_130E, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_130F, PCI_CHIP_KAVERI_130F, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1310, PCI_CHIP_KAVERI_1310, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1311, PCI_CHIP_KAVERI_1311, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1312, PCI_CHIP_KAVERI_1312, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1313, PCI_CHIP_KAVERI_1313, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1315, PCI_CHIP_KAVERI_1315, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1316, PCI_CHIP_KAVERI_1316, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_1317, PCI_CHIP_KAVERI_1317, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A0, PCI_CHIP_HAWAII_67A0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A1, PCI_CHIP_HAWAII_67A1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A2, PCI_CHIP_HAWAII_67A2, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A8, PCI_CHIP_HAWAII_67A8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67A9, PCI_CHIP_HAWAII_67A9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67AA, PCI_CHIP_HAWAII_67AA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B0, PCI_CHIP_HAWAII_67B0, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B1, PCI_CHIP_HAWAII_67B1, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B8, PCI_CHIP_HAWAII_67B8, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67B9, PCI_CHIP_HAWAII_67B9, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67BA, PCI_CHIP_HAWAII_67BA, RES_SHARED_VGA },
|
||||
{ PCI_CHIP_HAWAII_67BE, PCI_CHIP_HAWAII_67BE, RES_SHARED_VGA },
|
||||
{ -1, -1, RES_UNDEFINED }
|
||||
};
|
||||
|
||||
@ -380,7 +380,7 @@ static const struct pci_id_match radeon_device_match[] = {
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9645, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9649, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9649, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ),
|
||||
@ -642,5 +642,38 @@ static const struct pci_id_match radeon_device_match[] = {
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KABINI_983F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1307, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1309, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130A, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130E, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_130F, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1310, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1311, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1312, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1313, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1315, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1316, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1317, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A2, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67AA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B0, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B1, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B8, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B9, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BA, 0 ),
|
||||
ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BE, 0 ),
|
||||
{ 0, 0, 0 }
|
||||
};
|
||||
|
||||
@ -50,6 +50,10 @@
|
||||
#include "xf86drmMode.h"
|
||||
#include "dri.h"
|
||||
|
||||
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
||||
#include <xf86_OSproc.h>
|
||||
#endif
|
||||
|
||||
#ifdef XSERVER_PLATFORM_BUS
|
||||
#include <xf86platformBus.h>
|
||||
#endif
|
||||
@ -92,6 +96,12 @@ static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci
|
||||
|
||||
busIdString = DRICreatePCIBusID(pci_dev);
|
||||
ret = drmCheckModesettingSupported(busIdString);
|
||||
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
||||
if (ret) {
|
||||
if (xf86LoadKernelModule("radeonkms"))
|
||||
ret = drmCheckModesettingSupported(busIdString);
|
||||
}
|
||||
#endif
|
||||
free(busIdString);
|
||||
if (ret) {
|
||||
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
|
||||
|
||||
@ -110,6 +110,7 @@ typedef enum {
|
||||
CHIP_FAMILY_BONAIRE,
|
||||
CHIP_FAMILY_KAVERI,
|
||||
CHIP_FAMILY_KABINI,
|
||||
CHIP_FAMILY_HAWAII,
|
||||
CHIP_FAMILY_LAST
|
||||
} RADEONChipFamily;
|
||||
|
||||
@ -135,7 +136,6 @@ typedef struct
|
||||
int fd_ref;
|
||||
unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */
|
||||
int fd_wakeup_ref;
|
||||
int dri2_info_cnt;
|
||||
} RADEONEntRec, *RADEONEntPtr;
|
||||
|
||||
extern const OptionInfoRec *RADEONOptionsWeak(void);
|
||||
|
||||
@ -165,7 +165,14 @@ void RADEONInitVideo(ScreenPtr pScreen)
|
||||
memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
|
||||
adaptors = newAdaptors;
|
||||
|
||||
if ((info->ChipFamily < CHIP_FAMILY_RS400)
|
||||
if (info->use_glamor) {
|
||||
texturedAdaptor = radeon_glamor_xv_init(pScreen, 16);
|
||||
if (texturedAdaptor != NULL) {
|
||||
adaptors[num_adaptors++] = texturedAdaptor;
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video (glamor)\n");
|
||||
} else
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video (glamor)\n");
|
||||
} else if ((info->ChipFamily < CHIP_FAMILY_RS400)
|
||||
|| (info->directRenderingEnabled)
|
||||
) {
|
||||
texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user