333 lines
9.7 KiB
C
333 lines
9.7 KiB
C
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c,v 1.21 2003/09/24 02:43:18 dawes Exp $ */
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/*
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* Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of Marc Aurele La France not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. Marc Aurele La France makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as-is" without express or implied warranty.
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*
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* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
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* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "ati.h"
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#include "atichip.h"
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#include "aticrtc.h"
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#include "atidsp.h"
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#include "atimach64io.h"
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#include "atividmem.h"
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/*
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* ATIDSPPreInit --
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*
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* This function initialises global variables used to set DSP registers on a
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* VT-B or later.
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*/
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Bool
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ATIDSPPreInit
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(
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int iScreen,
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ATIPtr pATI
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)
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{
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CARD32 IOValue, dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off;
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int trp;
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/*
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* VT-B's and later have additional post-dividers that are not powers of
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* two.
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*/
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pATI->ClockDescriptor.NumD = 8;
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/* Retrieve XCLK settings */
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IOValue = ATIMach64GetPLLReg(PLL_XCLK_CNTL);
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pATI->XCLKPostDivider = GetBits(IOValue, PLL_XCLK_SRC_SEL);
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pATI->XCLKReferenceDivider = 1;
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switch (pATI->XCLKPostDivider)
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{
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case 0: case 1: case 2: case 3:
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break;
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case 4:
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pATI->XCLKReferenceDivider = 3;
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pATI->XCLKPostDivider = 0;
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break;
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default:
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xf86DrvMsg(iScreen, X_ERROR,
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"Unsupported XCLK source: %d.\n", pATI->XCLKPostDivider);
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return FALSE;
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}
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pATI->XCLKPostDivider -= GetBits(IOValue, PLL_MFB_TIMES_4_2B);
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pATI->XCLKFeedbackDivider = ATIMach64GetPLLReg(PLL_MCLK_FB_DIV);
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xf86DrvMsgVerb(iScreen, X_INFO, 2,
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"Engine XCLK %.3f MHz; Refresh rate code %ld.\n",
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ATIDivide(pATI->XCLKFeedbackDivider * pATI->ReferenceNumerator,
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pATI->XCLKReferenceDivider * pATI->ClockDescriptor.MaxM *
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pATI->ReferenceDenominator, 1 - pATI->XCLKPostDivider, 0) /
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(double)1000.0,
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GetBits(pATI->LockData.mem_cntl, CTL_MEM_REFRESH_RATE_B));
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/* Compute maximum RAS delay and friends */
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trp = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRP);
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pATI->XCLKPageFaultDelay = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRCD) +
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GetBits(pATI->LockData.mem_cntl, CTL_MEM_TCRD) + trp + 2;
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pATI->XCLKMaxRASDelay = GetBits(pATI->LockData.mem_cntl, CTL_MEM_TRAS) +
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trp + 2;
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pATI->DisplayFIFODepth = 32;
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if (pATI->Chip < ATI_CHIP_264VT4)
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{
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pATI->XCLKPageFaultDelay += 2;
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pATI->XCLKMaxRASDelay += 3;
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pATI->DisplayFIFODepth = 24;
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}
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switch (pATI->MemoryType)
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{
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case MEM_264_DRAM:
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if (pATI->VideoRAM <= 1024)
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{
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pATI->DisplayLoopLatency = 10;
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}
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else
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{
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pATI->DisplayLoopLatency = 8;
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pATI->XCLKPageFaultDelay += 2;
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}
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break;
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case MEM_264_EDO:
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case MEM_264_PSEUDO_EDO:
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if (pATI->VideoRAM <= 1024)
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{
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pATI->DisplayLoopLatency = 9;
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}
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else
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{
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pATI->DisplayLoopLatency = 8;
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pATI->XCLKPageFaultDelay++;
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}
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break;
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case MEM_264_SDRAM:
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if (pATI->VideoRAM <= 1024)
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{
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pATI->DisplayLoopLatency = 11;
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}
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else
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{
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pATI->DisplayLoopLatency = 10;
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pATI->XCLKPageFaultDelay++;
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}
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break;
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case MEM_264_SGRAM:
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pATI->DisplayLoopLatency = 8;
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pATI->XCLKPageFaultDelay += 3;
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break;
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default: /* Set maximums */
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pATI->DisplayLoopLatency = 11;
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pATI->XCLKPageFaultDelay += 3;
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break;
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}
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if (pATI->XCLKMaxRASDelay <= pATI->XCLKPageFaultDelay)
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pATI->XCLKMaxRASDelay = pATI->XCLKPageFaultDelay + 1;
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/* Allow BIOS to override */
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dsp_config = inr(DSP_CONFIG);
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dsp_on_off = inr(DSP_ON_OFF);
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vga_dsp_config = inr(VGA_DSP_CONFIG);
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vga_dsp_on_off = inr(VGA_DSP_ON_OFF);
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if (dsp_config)
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pATI->DisplayLoopLatency = GetBits(dsp_config, DSP_LOOP_LATENCY);
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if ((!dsp_on_off && (pATI->Chip < ATI_CHIP_264GTPRO)) ||
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((dsp_on_off == vga_dsp_on_off) &&
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(!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW))))
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{
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if (ATIDivide(GetBits(vga_dsp_on_off, VGA_DSP_OFF),
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GetBits(vga_dsp_config, VGA_DSP_XCLKS_PER_QW), 5, 1) > 24)
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pATI->DisplayFIFODepth = 32;
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else
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pATI->DisplayFIFODepth = 24;
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}
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return TRUE;
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}
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/*
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* ATIDSPSave --
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*
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* This function is called to remember DSP register values on VT-B and later
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* controllers.
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*/
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void
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ATIDSPSave
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(
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ATIPtr pATI,
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ATIHWPtr pATIHW
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)
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{
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pATIHW->dsp_on_off = inr(DSP_ON_OFF);
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pATIHW->dsp_config = inr(DSP_CONFIG);
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}
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/*
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* ATIDSPCalculate --
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*
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* This function sets up DSP register values for a VTB or later. Note that
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* this would be slightly different if VCLK 0 or 1 were used for the mode
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* instead. In that case, this function would set VGA_DSP_CONFIG and
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* VGA_DSP_ON_OFF, would have to zero out DSP_CONFIG and DSP_ON_OFF, and would
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* have to consider that VGA_DSP_CONFIG is partitioned slightly differently
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* than DSP_CONFIG.
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*/
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void
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ATIDSPCalculate
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(
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ATIPtr pATI,
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ATIHWPtr pATIHW,
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DisplayModePtr pMode
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)
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{
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int Multiplier, Divider;
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int RASMultiplier = pATI->XCLKMaxRASDelay, RASDivider = 1;
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int dsp_precision, dsp_on, dsp_off, dsp_xclks;
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int tmp, vshift, xshift;
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# define Maximum_DSP_PRECISION ((int)MaxBits(DSP_PRECISION))
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/* Compute a memory-to-screen bandwidth ratio */
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Multiplier = pATI->XCLKFeedbackDivider *
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pATI->ClockDescriptor.PostDividers[pATIHW->PostDivider];
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Divider = pATIHW->FeedbackDivider * pATI->XCLKReferenceDivider;
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#ifndef AVOID_CPIO
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if (pATI->depth >= 8)
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#endif /* AVOID_CPIO */
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{
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Divider *= pATI->bitsPerPixel / 4;
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}
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/* Start by assuming a display FIFO width of 64 bits */
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vshift = (6 - 2) - pATI->XCLKPostDivider;
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#ifndef AVOID_CPIO
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if (pATIHW->crtc == ATI_CRTC_VGA)
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vshift--; /* Nope, it's 32 bits wide */
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#endif /* AVOID_CPIO */
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if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0))
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{
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/* Compensate for horizontal stretching */
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Multiplier *= pATI->LCDHorizontal;
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Divider *= pMode->HDisplay & ~7;
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RASMultiplier *= pATI->LCDHorizontal;
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RASDivider *= pMode->HDisplay & ~7;
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}
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/* Determine dsp_precision first */
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tmp = ATIDivide(Multiplier * pATI->DisplayFIFODepth, Divider, vshift, -1);
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for (dsp_precision = -5; tmp; dsp_precision++)
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tmp >>= 1;
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if (dsp_precision < 0)
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dsp_precision = 0;
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else if (dsp_precision > Maximum_DSP_PRECISION)
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dsp_precision = Maximum_DSP_PRECISION;
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xshift = 6 - dsp_precision;
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vshift += xshift;
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/* Move on to dsp_off */
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dsp_off = ATIDivide(Multiplier * (pATI->DisplayFIFODepth - 1), Divider,
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vshift, -1) - ATIDivide(1, 1, vshift - xshift, 1);
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/* Next is dsp_on */
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#ifndef AVOID_CPIO
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if ((pATIHW->crtc == ATI_CRTC_VGA) /* && (dsp_precision < 3) */)
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{
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/*
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* TODO: I don't yet know why something like this appears necessary.
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* But I don't have time to explore this right now.
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*/
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dsp_on = ATIDivide(Multiplier * 5, Divider, vshift + 2, 1);
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}
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else
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#endif /* AVOID_CPIO */
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{
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dsp_on = ATIDivide(Multiplier, Divider, vshift, 1);
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tmp = ATIDivide(RASMultiplier, RASDivider, xshift, 1);
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if (dsp_on < tmp)
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dsp_on = tmp;
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dsp_on += (tmp * 2) +
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ATIDivide(pATI->XCLKPageFaultDelay, 1, xshift, 1);
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}
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/* Calculate rounding factor and apply it to dsp_on */
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tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
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dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
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if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1)))
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{
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dsp_on = dsp_off - ATIDivide(Multiplier, Divider, vshift, -1);
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dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
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}
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/* Last but not least: dsp_xclks */
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dsp_xclks = ATIDivide(Multiplier, Divider, vshift + 5, 1);
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/* Build DSP register contents */
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pATIHW->dsp_on_off = SetBits(dsp_on, DSP_ON) |
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SetBits(dsp_off, DSP_OFF);
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pATIHW->dsp_config = SetBits(dsp_precision, DSP_PRECISION) |
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SetBits(dsp_xclks, DSP_XCLKS_PER_QW) |
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SetBits(pATI->DisplayLoopLatency, DSP_LOOP_LATENCY);
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}
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/*
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* ATIDSPSet --
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*
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* This function is called to set DSP registers on VT-B and later controllers.
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*/
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void
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ATIDSPSet
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(
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ATIPtr pATI,
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ATIHWPtr pATIHW
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)
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{
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outr(DSP_ON_OFF, pATIHW->dsp_on_off);
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outr(DSP_CONFIG, pATIHW->dsp_config);
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}
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