2006-11-26 11:13:41 -07:00
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#include <xf86RamDac.h>
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2010-07-27 13:02:24 -06:00
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extern _X_EXPORT unsigned long TIramdacCalculateMNPForClock(unsigned long RefClock,
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2006-11-26 11:13:41 -07:00
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unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
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unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
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unsigned long *rP);
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2010-07-27 13:02:24 -06:00
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extern _X_EXPORT RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
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extern _X_EXPORT void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
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extern _X_EXPORT void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
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extern _X_EXPORT void TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
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extern _X_EXPORT void TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
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extern _X_EXPORT void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
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extern _X_EXPORT void TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices,
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2006-11-26 11:13:41 -07:00
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LOCO *colors, VisualPtr pVisual);
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typedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
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VisualPtr);
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extern _X_EXPORT TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
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2006-11-26 11:13:41 -07:00
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#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
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#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
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/*
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* TI Ramdac registers
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*/
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#define TIDAC_rev 0x01
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#define TIDAC_ind_curs_ctrl 0x06
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#define TIDAC_byte_router_ctrl 0x07
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#define TIDAC_latch_ctrl 0x0f
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#define TIDAC_true_color_ctrl 0x18
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#define TIDAC_multiplex_ctrl 0x19
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#define TIDAC_clock_select 0x1a
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#define TIDAC_palette_page 0x1c
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#define TIDAC_general_ctrl 0x1d
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#define TIDAC_misc_ctrl 0x1e
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#define TIDAC_pll_addr 0x2c
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#define TIDAC_pll_pixel_data 0x2d
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#define TIDAC_pll_memory_data 0x2e
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#define TIDAC_pll_loop_data 0x2f
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#define TIDAC_key_over_low 0x30
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#define TIDAC_key_over_high 0x31
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#define TIDAC_key_red_low 0x32
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#define TIDAC_key_red_high 0x33
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#define TIDAC_key_green_low 0x34
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#define TIDAC_key_green_high 0x35
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#define TIDAC_key_blue_low 0x36
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#define TIDAC_key_blue_high 0x37
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#define TIDAC_key_ctrl 0x38
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#define TIDAC_clock_ctrl 0x39
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#define TIDAC_sense_test 0x3a
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#define TIDAC_test_mode_data 0x3b
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#define TIDAC_crc_remain_lsb 0x3c
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#define TIDAC_crc_remain_msb 0x3d
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#define TIDAC_crc_bit_select 0x3e
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#define TIDAC_id 0x3f
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/* These are pll values that are accessed via TIDAC_pll_pixel_data */
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#define TIDAC_PIXEL_N 0x80
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#define TIDAC_PIXEL_M 0x81
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#define TIDAC_PIXEL_P 0x82
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#define TIDAC_PIXEL_VALID 0x83
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/* These are pll values that are accessed via TIDAC_pll_loop_data */
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#define TIDAC_LOOP_N 0x90
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#define TIDAC_LOOP_M 0x91
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#define TIDAC_LOOP_P 0x92
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#define TIDAC_LOOP_VALID 0x93
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/* Direct mapping addresses */
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#define TIDAC_INDEX 0xa0
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#define TIDAC_PALETTE_DATA 0xa1
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#define TIDAC_READ_MASK 0xa2
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#define TIDAC_READ_ADDR 0xa3
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#define TIDAC_CURS_WRITE_ADDR 0xa4
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#define TIDAC_CURS_COLOR 0xa5
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#define TIDAC_CURS_READ_ADDR 0xa7
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#define TIDAC_CURS_CTL 0xa9
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#define TIDAC_INDEXED_DATA 0xaa
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#define TIDAC_CURS_RAM_DATA 0xab
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#define TIDAC_CURS_XLOW 0xac
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#define TIDAC_CURS_XHIGH 0xad
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#define TIDAC_CURS_YLOW 0xae
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#define TIDAC_CURS_YHIGH 0xaf
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#define TIDAC_sw_reset 0xff
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/* Constants */
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#define TIDAC_TVP_3026_ID 0x26
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#define TIDAC_TVP_3030_ID 0x30
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