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xenocara/driver/xf86-video-intel/xvmc/shader/vld/read_frame_x1y1_y.g4i

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Update the intel driver to 2.9.1 plus backports. 2.9.1 is the last version of the intel DDX that supports UMS (User modesetting), with 2.10 onwards being purely KMS only. As such, this driver contains backports of almost every correctness or performance related fix to the rendering layer in later intel drivers. This driver *REQUIRES* a GEM enabled kernel. it claims to support non-gem mode but this is essentially unmaintained and due to the way the abstraciton works is slow, if it works at all (it often does not). You have been warned. tested by many many people on tech over the last few weeks.
2010-05-10 16:32:28 -06:00
/*
* Copyright © 2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Author:
* Zou Nan hai <nanhai.zou@intel.com>
* Yan Li <li.l.yan@intel.com>
* Liu Xi bin<xibin.liu@intel.com>
*/
/* GRF allocation:
g1~g30: constant buffer
g1~g2:intra IQ matrix
g3~g4:non intra IQ matrix
g5~g20:IDCT table
g31: thread payload
g32: message descriptor for reading reference data
g58~g81:reference data
g82: thread payload backup
g83~g106:IDCT data */
mov (1) g32.8<1>UD 0x007001FUD {align1};
send (16) 0 g38.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1};
add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1};
send (16) 0 g46.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1};
add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1};
mov (1) g32.8<1>UD 0x1FUD {align1};
send (16) 0 g54.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 1 {align1};
add (16) g58.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1};
add (16) g59.0<1>UW g39.0<16,16,1>UB g39.1<16,16,1>UB {align1};
add (16) g60.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1};
add (16) g61.0<1>UW g41.0<16,16,1>UB g41.1<16,16,1>UB {align1};
add (16) g62.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1};
add (16) g63.0<1>UW g43.0<16,16,1>UB g43.1<16,16,1>UB {align1};
add (16) g64.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1};
add (16) g65.0<1>UW g45.0<16,16,1>UB g45.1<16,16,1>UB {align1};
add (16) g66.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1};
add (16) g67.0<1>UW g47.0<16,16,1>UB g47.1<16,16,1>UB {align1};
add (16) g68.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1};
add (16) g69.0<1>UW g49.0<16,16,1>UB g49.1<16,16,1>UB {align1};
add (16) g70.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1};
add (16) g71.0<1>UW g51.0<16,16,1>UB g51.1<16,16,1>UB {align1};
add (16) g72.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1};
add (16) g73.0<1>UW g53.0<16,16,1>UB g53.1<16,16,1>UB {align1};
add (16) g58.0<1>UW g58.0<16,16,1>UW g39.0<16,16,1>UB {align1};
add (16) g59.0<1>UW g59.0<16,16,1>UW g40.0<16,16,1>UB {align1};
add (16) g60.0<1>UW g60.0<16,16,1>UW g41.0<16,16,1>UB {align1};
add (16) g61.0<1>UW g61.0<16,16,1>UW g42.0<16,16,1>UB {align1};
add (16) g62.0<1>UW g62.0<16,16,1>UW g43.0<16,16,1>UB {align1};
add (16) g63.0<1>UW g63.0<16,16,1>UW g44.0<16,16,1>UB {align1};
add (16) g64.0<1>UW g64.0<16,16,1>UW g45.0<16,16,1>UB {align1};
add (16) g65.0<1>UW g65.0<16,16,1>UW g46.0<16,16,1>UB {align1};
add (16) g66.0<1>UW g66.0<16,16,1>UW g47.0<16,16,1>UB {align1};
add (16) g67.0<1>UW g67.0<16,16,1>UW g48.0<16,16,1>UB {align1};
add (16) g68.0<1>UW g68.0<16,16,1>UW g49.0<16,16,1>UB {align1};
add (16) g69.0<1>UW g69.0<16,16,1>UW g50.0<16,16,1>UB {align1};
add (16) g70.0<1>UW g70.0<16,16,1>UW g51.0<16,16,1>UB {align1};
add (16) g71.0<1>UW g71.0<16,16,1>UW g52.0<16,16,1>UB {align1};
add (16) g72.0<1>UW g72.0<16,16,1>UW g53.0<16,16,1>UB {align1};
add (16) g73.0<1>UW g73.0<16,16,1>UW g54.0<16,16,1>UB {align1};
add (16) g58.0<1>UW g58.0<16,16,1>UW g39.1<16,16,1>UB {align1};
add (16) g59.0<1>UW g59.0<16,16,1>UW g40.1<16,16,1>UB {align1};
add (16) g60.0<1>UW g60.0<16,16,1>UW g41.1<16,16,1>UB {align1};
add (16) g61.0<1>UW g61.0<16,16,1>UW g42.1<16,16,1>UB {align1};
add (16) g62.0<1>UW g62.0<16,16,1>UW g43.1<16,16,1>UB {align1};
add (16) g63.0<1>UW g63.0<16,16,1>UW g44.1<16,16,1>UB {align1};
add (16) g64.0<1>UW g64.0<16,16,1>UW g45.1<16,16,1>UB {align1};
add (16) g65.0<1>UW g65.0<16,16,1>UW g46.1<16,16,1>UB {align1};
add (16) g66.0<1>UW g66.0<16,16,1>UW g47.1<16,16,1>UB {align1};
add (16) g67.0<1>UW g67.0<16,16,1>UW g48.1<16,16,1>UB {align1};
add (16) g68.0<1>UW g68.0<16,16,1>UW g49.1<16,16,1>UB {align1};
add (16) g69.0<1>UW g69.0<16,16,1>UW g50.1<16,16,1>UB {align1};
add (16) g70.0<1>UW g70.0<16,16,1>UW g51.1<16,16,1>UB {align1};
add (16) g71.0<1>UW g71.0<16,16,1>UW g52.1<16,16,1>UB {align1};
add (16) g72.0<1>UW g72.0<16,16,1>UW g53.1<16,16,1>UB {align1};
add (16) g73.0<1>UW g73.0<16,16,1>UW g54.1<16,16,1>UB {align1};
shr.sat (16) g58.0<1>UW g58.0<16,16,1>UW 2UW {align1};
shr.sat (16) g59.0<1>UW g59.0<16,16,1>UW 2UW {align1};
shr.sat (16) g60.0<1>UW g60.0<16,16,1>UW 2UW {align1};
shr.sat (16) g61.0<1>UW g61.0<16,16,1>UW 2UW {align1};
shr.sat (16) g62.0<1>UW g62.0<16,16,1>UW 2UW {align1};
shr.sat (16) g63.0<1>UW g63.0<16,16,1>UW 2UW {align1};
shr.sat (16) g64.0<1>UW g64.0<16,16,1>UW 2UW {align1};
shr.sat (16) g65.0<1>UW g65.0<16,16,1>UW 2UW {align1};
shr.sat (16) g66.0<1>UW g66.0<16,16,1>UW 2UW {align1};
shr.sat (16) g67.0<1>UW g67.0<16,16,1>UW 2UW {align1};
shr.sat (16) g68.0<1>UW g68.0<16,16,1>UW 2UW {align1};
shr.sat (16) g69.0<1>UW g69.0<16,16,1>UW 2UW {align1};
shr.sat (16) g70.0<1>UW g70.0<16,16,1>UW 2UW {align1};
shr.sat (16) g71.0<1>UW g71.0<16,16,1>UW 2UW {align1};
shr.sat (16) g72.0<1>UW g72.0<16,16,1>UW 2UW {align1};
shr.sat (16) g73.0<1>UW g73.0<16,16,1>UW 2UW {align1};
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