65 lines
2.9 KiB
Plaintext
65 lines
2.9 KiB
Plaintext
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Author:
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* Zou Nan hai <nanhai.zou@intel.com>
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* Yan Li <li.l.yan@intel.com>
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* Liu Xi bin<xibin.liu@intel.com>
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*/
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/* GRF allocation:
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g1~g30: constant buffer
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g1~g2:intra IQ matrix
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g3~g4:non intra IQ matrix
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g5~g20:IDCT table
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g112~g115: intra IQ matrix in UW format (in order to use instruction compress), copys from g1~g2
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g[a0.0]:DCT data of a block
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g125: ip before jump
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if(v==0 && u==0 && intra_mb)
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F''[v][u] = QF[v][u] * intra_dc_mult
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else
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F''[v][u] = (QF[v][u]*W[w][v][u]*quantiser_scale*2)/32
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*/
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DO_IQ_INTRA:
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add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
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mov (1) g111.0<1>W g[a0.0]<1,1,1>W {align1};
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mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr};
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mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
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asr (16) g116.0<1>D g116.0<8,8,1>D 4UW {align1 compr};
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mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1}; //intra_dc_mult
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add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
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mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr};
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mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
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asr (16) g118.0<1>D g118.0<8,8,1>D 4UW {align1 compr};
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add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
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mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr};
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mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
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asr (16) g120.0<1>D g120.0<8,8,1>D 4UW {align1 compr};
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add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1};
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mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr};
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mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr};
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asr (16) g122.0<1>D g122.0<8,8,1>D 4UW {align1 compr};
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add (1) ip g125.0<1,1,1>UD 0x20UD {align1}; //jump back
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