228 lines
7.3 KiB
C
228 lines
7.3 KiB
C
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/*
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* Copyright 1999 SuSE, Inc.
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of SuSE not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. SuSE makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE
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* BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* Author: Keith Packard, SuSE, Inc.
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*/
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#ifndef _S3REG_H_
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#define _S3REG_H_
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#include "vga.h"
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#define S3_SR 0
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#define S3_NSR 0x70
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#define S3_GR (S3_SR+S3_NSR)
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#define S3_NGR 0x09
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#define S3_AR (S3_GR+S3_NGR)
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#define S3_NAR 0x15
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#define S3_CR (S3_AR+S3_NAR)
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#define S3_NCR 0xc0
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#define S3_DAC (S3_CR+S3_NCR)
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#define S3_NDAC 4
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#define S3_MISC_OUT (S3_DAC + S3_NDAC)
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#define S3_INPUT_STATUS_1 (S3_MISC_OUT+1)
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#define S3_NREG (S3_INPUT_STATUS_1+1)
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extern VgaReg s3_h_total[];
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extern VgaReg s3_h_display_end[];
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extern VgaReg s3_h_blank_start[];
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extern VgaReg s3_h_blank_end[];
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extern VgaReg s3_display_skew[];
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extern VgaReg s3_h_sync_start[];
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extern VgaReg s3_h_sync_end[];
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extern VgaReg s3_h_skew[];
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extern VgaReg s3_v_total[];
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extern VgaReg s3_preset_row_scan[];
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extern VgaReg s3_max_scan_line[];
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extern VgaReg s3_start_address[];
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extern VgaReg s3_v_retrace_start[];
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extern VgaReg s3_v_retrace_end[];
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extern VgaReg s3_clear_v_retrace_int[];
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extern VgaReg s3_disable_v_retrace_int[];
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extern VgaReg s3_lock_crtc[];
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extern VgaReg s3_v_display_end[];
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extern VgaReg s3_screen_offset[];
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extern VgaReg s3_count_by_4_mode[];
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extern VgaReg s3_doubleword_mode[];
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extern VgaReg s3_v_blank_start[];
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extern VgaReg s3_v_blank_end[];
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extern VgaReg s3_2bk_cga[];
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extern VgaReg s3_4bk_hga[];
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extern VgaReg s3_v_total_double[];
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extern VgaReg s3_address_16k_wrap[];
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extern VgaReg s3_word_mode[];
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extern VgaReg s3_byte_mode[];
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extern VgaReg s3_hardware_reset[];
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extern VgaReg s3_line_compare[];
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extern VgaReg s3_delay_primary_load[];
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extern VgaReg s3_device_id[];
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extern VgaReg s3_revision[];
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extern VgaReg s3_enable_vga_16bit[];
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extern VgaReg s3_enhanced_memory_mapping[];
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extern VgaReg s3_enable_sff[];
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extern VgaReg s3_lock_dac_writes[];
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extern VgaReg s3_border_select[];
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extern VgaReg s3_lock_palette[];
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extern VgaReg s3_lock_vert[];
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extern VgaReg s3_lock_horz[];
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extern VgaReg s3_io_disable[];
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extern VgaReg s3_mem_size[];
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extern VgaReg s3_register_lock_1 [];
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extern VgaReg s3_register_lock_2 [];
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extern VgaReg s3_refresh_control[];
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extern VgaReg s3_enable_256[];
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extern VgaReg s3_disable_pci_read_bursts[];
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extern VgaReg s3_h_start_fifo_fetch[];
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extern VgaReg s3_enable_2d_access[];
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extern VgaReg s3_interlace[];
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extern VgaReg s3_old_screen_off_8[];
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extern VgaReg s3_h_counter_double_mode[];
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extern VgaReg s3_cursor_enable[];
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extern VgaReg s3_cursor_right[];
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extern VgaReg s3_cursor_xhigh[];
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extern VgaReg s3_cursor_xlow[];
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extern VgaReg s3_cursor_yhigh[];
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extern VgaReg s3_cursor_ylow[];
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extern VgaReg s3_cursor_fg[];
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extern VgaReg s3_cursor_bg[];
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extern VgaReg s3_cursor_address[];
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extern VgaReg s3_cursor_xoff[];
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extern VgaReg s3_cursor_yoff[];
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extern VgaReg s3_ge_screen_width[];
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extern VgaReg s3_pixel_length[];
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extern VgaReg s3_big_endian_linear[];
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extern VgaReg s3_mmio_select[];
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extern VgaReg s3_mmio_window[];
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extern VgaReg s3_swap_nibbles[];
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extern VgaReg s3_cursor_ms_x11[];
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extern VgaReg s3_linear_window_size[];
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extern VgaReg s3_enable_linear[];
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extern VgaReg s3_h_blank_extend[];
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extern VgaReg s3_h_sync_extend[];
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extern VgaReg s3_sdclk_skew[];
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extern VgaReg s3_delay_blank[];
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extern VgaReg s3_delay_h_enable[];
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extern VgaReg s3_enable_2d_3d[];
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extern VgaReg s3_pci_disconnect_enable[];
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extern VgaReg s3_primary_load_control[];
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extern VgaReg s3_secondary_load_control[];
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extern VgaReg s3_pci_retry_enable[];
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extern VgaReg s3_streams_mode[];
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extern VgaReg s3_color_mode[];
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extern VgaReg s3_primary_stream_definition[];
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extern VgaReg s3_primary_stream_timeout[];
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extern VgaReg s3_master_control_unit_timeout[];
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extern VgaReg s3_command_buffer_timeout[];
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extern VgaReg s3_lpb_timeout[];
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extern VgaReg s3_cpu_timeout[];
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extern VgaReg s3_2d_graphics_engine_timeout[];
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extern VgaReg s3_fifo_drain_delay[];
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extern VgaReg s3_fifo_fetch_timing[];
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extern VgaReg s3_dac_power_up_time[];
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extern VgaReg s3_dac_power_saving_disable[];
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extern VgaReg s3_flat_panel_output_control_1[];
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extern VgaReg s3_streams_fifo_delay[];
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extern VgaReg s3_flat_panel_output_control_2[];
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extern VgaReg s3_enable_l1_parameter[];
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extern VgaReg s3_primary_stream_l1[];
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extern VgaReg s3_dot_clock_8[];
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extern VgaReg s3_screen_off[];
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extern VgaReg s3_enable_write_plane[];
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extern VgaReg s3_extended_memory_access[];
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extern VgaReg s3_sequential_addressing_mode[];
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extern VgaReg s3_select_chain_4_mode[];
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extern VgaReg s3_unlock_extended_sequencer[];
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extern VgaReg s3_linear_addressing_control[];
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extern VgaReg s3_disable_io_ports[];
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extern VgaReg s3_hsync_control[];
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extern VgaReg s3_vsync_control[];
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extern VgaReg s3_mclk_n[];
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extern VgaReg s3_mclk_r[];
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extern VgaReg s3_mclk_m[];
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extern VgaReg s3_dclk_n[];
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extern VgaReg s3_dclk_r[];
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extern VgaReg s3_dclk_m[];
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extern VgaReg s3_mclk_load[];
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extern VgaReg s3_dclk_load[];
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extern VgaReg s3_dclk_over_2[];
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extern VgaReg s3_clock_load_imm[];
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extern VgaReg s3_dclk_invert[];
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extern VgaReg s3_enable_clock_double[];
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extern VgaReg s3_dclk_double_15_16_invert[];
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extern VgaReg s3_enable_gamma_correction[];
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extern VgaReg s3_enable_8_bit_luts[];
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extern VgaReg s3_dclk_control[];
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extern VgaReg s3_eclk_n[];
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extern VgaReg s3_eclk_r[];
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extern VgaReg s3_eclk_m[];
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extern VgaReg s3_vga_dclk_n[];
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extern VgaReg s3_vga_dclk_r[];
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extern VgaReg s3_vga_dclk_m1[];
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extern VgaReg s3_vga_dclk_m2[];
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extern VgaReg s3_vga_clk_select[];
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extern VgaReg s3_select_graphics_mode[];
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extern VgaReg s3_enable_blinking[];
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extern VgaReg s3_border_color[];
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extern VgaReg s3_io_addr_select[];
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extern VgaReg s3_enable_ram[];
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extern VgaReg s3_clock_select[];
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extern VgaReg s3_horz_sync_neg[];
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extern VgaReg s3_vert_sync_neg[];
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extern VgaReg s3_display_mode_inactive[];
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extern VgaReg s3_vertical_sync_active[];
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extern VgaReg s3_dac_mask[];
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extern VgaReg s3_dac_read_index[];
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extern VgaReg s3_dac_write_index[];
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extern VgaReg s3_dac_data[];
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#define s3Get(sv,r) VgaGet(&(sv)->card, (r))
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#define s3GetImm(sv,r) VgaGetImm(&(sv)->card, (r))
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#define s3Set(sv,r,v) VgaSet(&(sv)->card, (r), (v))
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#define s3SetImm(sv,r,v) VgaSetImm(&(sv)->card, (r), (v))
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typedef struct _s3Vga {
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VgaCard card;
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VgaValue values[S3_NREG];
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VGA32 save_lock_crtc;
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VGA32 save_register_lock_1;
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VGA32 save_register_lock_2;
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VGA32 save_unlock_extended_sequencer;
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VGA32 save_lock_dac_writes;
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VGA32 save_lock_horz;
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VGA32 save_lock_vert;
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VGA32 save_dot_clock_8;
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} S3Vga;
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void
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s3RegInit (S3Vga *s3vga, VGAVOL8 *mmio);
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void
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s3Save (S3Vga *s3vga);
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void
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s3Reset (S3Vga *s3vga);
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#endif /* _S3REG_H_ */
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