471 lines
12 KiB
C
471 lines
12 KiB
C
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c,v 1.1 2003/07/24 22:08:28 tsi Exp $ */
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/*
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* Copyright 2003 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of Marc Aurele La France not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. Marc Aurele La France makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as-is" without express or implied warranty.
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*
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* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
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* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "ati.h"
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#include "atichip.h"
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#include "atii2c.h"
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#include "atimach64i2c.h"
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#include "atimach64io.h"
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#include "atituner.h"
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/* MPP_CONFIG register values */
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#define MPP_INIT pATI->NewHW.mpp_config
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#define MPP_WRITE (MPP_INIT )
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#define MPP_WRITEINC (MPP_INIT | (MPP_AUTO_INC_EN ))
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#define MPP_READ (MPP_INIT | ( MPP_BUFFER_MODE_PREFETCH))
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#define MPP_READINC (MPP_INIT | (MPP_AUTO_INC_EN | MPP_BUFFER_MODE_PREFETCH))
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/*
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* ATIMach64MPPWaitForIdle --
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*
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* Support function to wait for the Multimedia Peripheral Port to become idle.
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* Currently, this function's return value indicates whether or not the port
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* became idle within 512 polling iterations. For now, this value is ignored
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* by the rest of the code, but might be used in the future.
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*/
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static Bool
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ATIMach64MPPWaitForIdle
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(
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ATIPtr pATI
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)
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{
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CARD32 Count = 0x0200;
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while (in8(MPP_CONFIG + 3) & GetByte(MPP_BUSY, 3))
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{
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if (!--Count)
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return FALSE;
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usleep(1); /* XXX Excessive? */
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}
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return TRUE;
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}
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/*
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* ATIMach64MPPSetAddress --
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*
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* Sets a 16-bit ImpacTV address on the Multimedia Peripheral Port.
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*/
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static void
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ATIMach64MPPSetAddress
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(
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ATIPtr pATI,
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CARD16 Address
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)
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{
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_CONFIG, MPP_WRITEINC);
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outr(MPP_ADDR, 0x00000008U);
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out8(MPP_DATA, (CARD8)Address);
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ATIMach64MPPWaitForIdle(pATI);
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out8(MPP_DATA, (CARD8)(Address >> 8));
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_CONFIG, MPP_WRITE);
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outr(MPP_ADDR, 0x00000018U);
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ATIMach64MPPWaitForIdle(pATI);
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}
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/*
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* ATIMach64ImpacTVProbe --
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*
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* This probes for an ImpacTV chip and returns its chip ID, or 0.
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*/
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static int
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ATIMach64ImpacTVProbe
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(
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int iScreen,
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ATIPtr pATI
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)
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{
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CARD8 ChipID = 0;
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/* Assume ATIModePreInit() has already been called */
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outr(MPP_STROBE_SEQ, pATI->NewHW.mpp_strobe_seq);
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outr(TVO_CNTL, pATI->NewHW.tvo_cntl);
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outr(MPP_CONFIG, MPP_READ);
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_ADDR, 0x0000000AU);
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if (!(ChipID = in8(MPP_DATA)))
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{
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_ADDR, 0x00000023U);
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if ((ChipID = in8(MPP_DATA)) != 0x54U)
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{
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_ADDR, 0x0000000BU);
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ChipID = in8(MPP_DATA);
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}
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}
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ATIMach64MPPWaitForIdle(pATI);
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outr(MPP_CONFIG, MPP_WRITE);
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if (ChipID)
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xf86DrvMsg(iScreen, X_PROBED, "ImpacTV chip ID 0x%02X detected.\n",
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ChipID);
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return (int)(CARD16)ChipID;
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}
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/*
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* ATIMach64ImpacTVSetBits --
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*
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* Controls I2C SDA and SCL lines through ImpacTV.
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*/
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static void
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ATIMach64ImpacTVSetBits
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(
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ATII2CPtr pATII2C,
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ATIPtr pATI,
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CARD32 Bits
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)
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{
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pATII2C->I2CCur = Bits;
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ATIMach64MPPSetAddress(pATI, IT_I2C_CNTL);
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outr(MPP_CONFIG, MPP_WRITE);
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out8(MPP_DATA, (CARD8)Bits);
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ATIMach64MPPWaitForIdle(pATI);
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}
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/*
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* ATIMach64ImpacTVGetBits --
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*
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* Returns the status of an ImpacTV's I2C control lines.
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*/
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static CARD32
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ATIMach64ImpacTVGetBits
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(
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ATIPtr pATI
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)
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{
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ATIMach64MPPSetAddress(pATI, IT_I2C_CNTL);
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outr(MPP_CONFIG, MPP_READ);
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ATIMach64MPPWaitForIdle(pATI);
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return in8(MPP_DATA);
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}
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/*
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* ATIMach64I2C_CNTLSetBits --
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*
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* Controls SDA and SCL lines through a 3D Rage Pro's hardware assisted I2C.
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*/
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static void
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ATIMach64I2C_CNTLSetBits
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(
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ATII2CPtr pATII2C,
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ATIPtr pATI,
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CARD32 Bits
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)
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{
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pATII2C->I2CCur = Bits;
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out8(I2C_CNTL_0 + 1, (CARD8)Bits);
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}
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/*
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* ATIMach64I2C_CNTLGetBits --
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*
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* Returns the status of a 3D Rage Pro's hardware assisted I2C control lines.
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*/
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static CARD32
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ATIMach64I2C_CNTLGetBits
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(
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ATIPtr pATI
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)
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{
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return in8(I2C_CNTL_0 + 1);
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}
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/*
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* ATIMach64GP_IOSetBits --
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*
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* Controls SDA and SCL control lines through a Mach64's GP_IO register.
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*/
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static void
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ATIMach64GP_IOSetBits
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(
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ATII2CPtr pATII2C,
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ATIPtr pATI,
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CARD32 Bits
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)
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{
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pATII2C->I2CCur = Bits;
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outr(GP_IO, Bits);
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}
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/*
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* ATIMach64GP_IOGetBits --
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*
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* Returns the status of I2C control lines through a Mach64's GP_IO register.
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*/
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static CARD32
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ATIMach64GP_IOGetBits
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(
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ATIPtr pATI
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)
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{
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return inr(GP_IO);
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}
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#define GPIO1_MASK \
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(DAC_GIO_STATE_1 | DAC_GIO_DIR_1)
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#define GPIO2_MASK \
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(GEN_GIO2_DATA_OUT | GEN_GIO2_DATA_IN | GEN_GIO2_WRITE)
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/*
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* ATIMach64DAC_GENSetBits --
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*
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* Controls SDA and SCL control lines through a Mach64's GEN_TEST_CNTL and
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* DAC_CNTL registers.
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*/
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static void
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ATIMach64DAC_GENSetBits
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(
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ATII2CPtr pATII2C,
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ATIPtr pATI,
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CARD32 Bits
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)
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{
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CARD32 tmp;
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pATII2C->I2CCur = Bits;
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tmp = inr(DAC_CNTL) & ~GPIO1_MASK;
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outr(DAC_CNTL, tmp | (Bits & GPIO1_MASK));
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tmp = inr(GEN_TEST_CNTL) & ~GPIO2_MASK;
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outr(GEN_TEST_CNTL, tmp | (Bits & GPIO2_MASK));
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}
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/*
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* ATIMach64DAC_GENGetBits --
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*
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* Returns the status of I2C control lines through a Mach64's GEN_TEST_CNTL and
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* DAC_CNTL registers.
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*/
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static CARD32
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ATIMach64DAC_GENGetBits
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(
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ATIPtr pATI
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)
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{
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return (inr(DAC_CNTL) & GPIO1_MASK) | (inr(GEN_TEST_CNTL) & GPIO2_MASK);
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}
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/*
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* ATITVAddOnProbe --
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*
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* Probe for an ATI-TV add-on card at specific addresses on an I2C bus.
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*/
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static Bool
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ATITVAddOnProbe
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(
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ScrnInfoPtr pScreenInfo,
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ATIPtr pATI,
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I2CBusPtr pI2CBus
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)
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{
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I2CDevPtr pI2CDev = xnfcalloc(1, SizeOf(I2CDevRec));
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int Index;
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I2CByte tmp;
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static const CARD8 ATITVAddOnAddresses[] = {0x70, 0x40, 0x78, 0x72, 0x42};
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pI2CDev->DevName = "ATI-TV Add-on";
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pI2CDev->pI2CBus = pI2CBus;
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pI2CDev->StartTimeout = pI2CBus->StartTimeout;
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pI2CDev->BitTimeout = pI2CBus->BitTimeout;
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pI2CDev->AcknTimeout = pI2CBus->AcknTimeout;
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pI2CDev->ByteTimeout = pI2CBus->ByteTimeout;
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for (Index = 0; Index < NumberOf(ATITVAddOnAddresses); Index++)
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{
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pI2CDev->SlaveAddr = ATITVAddOnAddresses[Index];
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if (xf86I2CFindDev(pI2CBus, pI2CDev->SlaveAddr))
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continue;
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tmp = 0xFFU;
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if (!(*pI2CBus->I2CWriteRead)(pI2CDev, &tmp, 1, NULL, 0) ||
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!(*pI2CBus->I2CWriteRead)(pI2CDev, NULL, 0, &tmp, 1) ||
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(tmp == 0xFFU) || ((tmp = tmp & 0x1FU) == /*ATI_TUNER_NONE*/0))
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continue;
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if (!xf86I2CDevInit(pI2CDev))
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{
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xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
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"Failed to register I2C device for ATI-TV add-on.\n");
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break;
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}
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if (pATI->Tuner != tmp)
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{
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if (pATI->Tuner != ATI_TUNER_NONE)
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xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
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"Tuner type mismatch: BIOS 0x%x, ATI-TV 0x%x.\n",
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pATI->Tuner, tmp);
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pATI->Tuner = tmp;
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}
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xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED,
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"%s tuner detected on ATI-TV add-on adapter at I2C bus address"
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" 0x%2x.\n", ATITuners[pATI->Tuner].name, pI2CDev->SlaveAddr);
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return TRUE;
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}
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xfree(pI2CDev);
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return FALSE;
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}
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/*
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* ATIMach64I2CPreInit --
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*
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* This function potentially allocates an I2CBusRec and initialises it with
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* ATI-specific and Mach64-specific information.
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*/
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void
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ATIMach64I2CPreInit
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(
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ScrnInfoPtr pScreenInfo,
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ATIPtr pATI
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)
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{
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I2CBusPtr pI2CBus;
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ATII2CPtr pATII2C;
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if ((pATI->Chip < ATI_CHIP_264CT) || (pATI->Chip >= ATI_CHIP_Mach64))
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return;
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/* Create an I2CBusRec and generically prime it */
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if (!(pI2CBus = ATICreateI2CBusRec(pScreenInfo->scrnIndex, pATI, "Mach64")))
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return;
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pATII2C = pI2CBus->DriverPrivate.ptr;
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switch (pATI->Chip)
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{
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case ATI_CHIP_264GTPRO:
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case ATI_CHIP_264LTPRO:
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case ATI_CHIP_264XL:
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case ATI_CHIP_MOBILITY:
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/*
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* These have I2C-specific registers. Assume older I2C access
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* mechanisms are inoperative.
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*/
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pATII2C->I2CSetBits = ATIMach64I2C_CNTLSetBits;
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pATII2C->I2CGetBits = ATIMach64I2C_CNTLGetBits;
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pATII2C->SCLDir = pATII2C->SDADir = 0;
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pATII2C->SCLGet = pATII2C->SCLSet = GetByte(I2C_CNTL_SCL, 1);
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pATII2C->SDAGet = pATII2C->SDASet = GetByte(I2C_CNTL_SDA, 1);
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out8(I2C_CNTL_1 + 2, GetByte(I2C_SEL, 2));
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out8(I2C_CNTL_0 + 0,
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GetByte(I2C_CNTL_STAT | I2C_CNTL_HPTR_RST, 0));
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break;
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case ATI_CHIP_264VTB:
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case ATI_CHIP_264GTB:
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case ATI_CHIP_264VT3:
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case ATI_CHIP_264GTDVD:
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case ATI_CHIP_264LT:
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case ATI_CHIP_264VT4:
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case ATI_CHIP_264GT2C:
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/* If an ImpacTV chip is found, use it to provide I2C access */
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if (ATIMach64ImpacTVProbe(pScreenInfo->scrnIndex, pATI))
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{
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pATII2C->I2CSetBits = ATIMach64ImpacTVSetBits;
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pATII2C->I2CGetBits = ATIMach64ImpacTVGetBits;
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pATII2C->SCLDir = IT_SCL_DIR;
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pATII2C->SCLGet = IT_SCL_GET;
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pATII2C->SCLSet = IT_SCL_SET;
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pATII2C->SDADir = IT_SDA_DIR;
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pATII2C->SDAGet = IT_SDA_GET;
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pATII2C->SDASet = IT_SDA_SET;
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ATIMach64MPPSetAddress(pATI, IT_I2C_CNTL);
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outr(MPP_CONFIG, MPP_WRITEINC);
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||
|
out8(MPP_DATA, 0x00U);
|
||
|
out8(MPP_DATA, 0x55U);
|
||
|
out8(MPP_DATA, 0x00U);
|
||
|
out8(MPP_DATA, 0x00U);
|
||
|
ATIMach64MPPWaitForIdle(pATI);
|
||
|
break;
|
||
|
}
|
||
|
/* Otherwise, fall through to the older case */
|
||
|
|
||
|
case ATI_CHIP_264VT:
|
||
|
case ATI_CHIP_264GT:
|
||
|
/* First try GIO pins 11 (clock) and 4 (data) */
|
||
|
pATII2C->I2CSetBits = ATIMach64GP_IOSetBits;
|
||
|
pATII2C->I2CGetBits = ATIMach64GP_IOGetBits;
|
||
|
pATII2C->SCLDir = GP_IO_DIR_B;
|
||
|
pATII2C->SCLGet = pATII2C->SCLSet = GP_IO_B;
|
||
|
pATII2C->SDADir = GP_IO_DIR_4;
|
||
|
pATII2C->SDAGet = pATII2C->SDASet = GP_IO_4;
|
||
|
|
||
|
if (ATITVAddOnProbe(pScreenInfo, pATI, pI2CBus))
|
||
|
break;
|
||
|
|
||
|
/* Next, try pins 10 (clock) and 12 (data) */
|
||
|
pATII2C->SCLDir = GP_IO_DIR_A;
|
||
|
pATII2C->SCLGet = pATII2C->SCLSet = GP_IO_A;
|
||
|
pATII2C->SDADir = GP_IO_DIR_C;
|
||
|
pATII2C->SDAGet = pATII2C->SDASet = GP_IO_C;
|
||
|
|
||
|
if (ATITVAddOnProbe(pScreenInfo, pATI, pI2CBus))
|
||
|
break;
|
||
|
/* Otherwise, fall back to ATI's first I2C implementation */
|
||
|
|
||
|
default:
|
||
|
/*
|
||
|
* First generation integrated controllers access GIO pin 1 (clock)
|
||
|
* though DAC_CNTL, and pin 2 (data) through GEN_TEST_CNTL.
|
||
|
*/
|
||
|
pATII2C->I2CSetBits = ATIMach64DAC_GENSetBits;
|
||
|
pATII2C->I2CGetBits = ATIMach64DAC_GENGetBits;
|
||
|
pATII2C->SCLDir = DAC_GIO_DIR_1;
|
||
|
pATII2C->SCLGet = pATII2C->SCLSet = DAC_GIO_STATE_1;
|
||
|
pATII2C->SDADir = GEN_GIO2_WRITE;
|
||
|
pATII2C->SDAGet = GEN_GIO2_DATA_IN;
|
||
|
pATII2C->SDASet = GEN_GIO2_DATA_OUT;
|
||
|
|
||
|
(void)ATITVAddOnProbe(pScreenInfo, pATI, pI2CBus);
|
||
|
break;
|
||
|
}
|
||
|
}
|