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https://github.com/golang/go
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7c17982f72
The new linker will disallow this on arm (it is already disallowed on amd64 and 386) in order to be able to lay out each function separately. The restriction is only for jumps into the middle of a function; jumps to the beginning of a function remain fine. Prereq for linker cleanup (golang.org/s/go13linker). R=iant, r, minux.ma CC=golang-dev https://golang.org/cl/35800043
297 lines
8.6 KiB
ArmAsm
297 lines
8.6 KiB
ArmAsm
// Inferno's libkern/vlop-arm.s
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// http://code.google.com/p/inferno-os/source/browse/libkern/vlop-arm.s
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Revisions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com). All rights reserved.
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// Portions Copyright 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#include "zasm_GOOS_GOARCH.h"
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#include "../../cmd/ld/textflag.h"
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arg=0
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/* replaced use of R10 by R11 because the former can be the data segment base register */
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TEXT _mulv(SB), NOSPLIT, $0
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MOVW 0(FP), R0
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MOVW 4(FP), R2 /* l0 */
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MOVW 8(FP), R11 /* h0 */
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MOVW 12(FP), R4 /* l1 */
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MOVW 16(FP), R5 /* h1 */
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MULLU R4, R2, (R7,R6)
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MUL R11, R4, R8
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ADD R8, R7
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MUL R2, R5, R8
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ADD R8, R7
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MOVW R6, 0(R(arg))
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MOVW R7, 4(R(arg))
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RET
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// trampoline for _sfloat2. passes LR as arg0 and
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// saves registers R0-R13 and CPSR on the stack. R0-R12 and CPSR flags can
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// be changed by _sfloat2.
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TEXT _sfloat(SB), NOSPLIT, $64-0 // 4 arg + 14*4 saved regs + cpsr
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MOVW R14, 4(R13)
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MOVW R0, 8(R13)
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MOVW $12(R13), R0
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MOVM.IA.W [R1-R12], (R0)
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MOVW $68(R13), R1 // correct for frame size
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MOVW R1, 60(R13)
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WORD $0xe10f1000 // mrs r1, cpsr
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MOVW R1, 64(R13)
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// Disable preemption of this goroutine during _sfloat2 by
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// m->locks++ and m->locks-- around the call.
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// Rescheduling this goroutine may cause the loss of the
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// contents of the software floating point registers in
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// m->freghi, m->freglo, m->fflag, if the goroutine is moved
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// to a different m or another goroutine runs on this m.
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// Rescheduling at ordinary function calls is okay because
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// all registers are caller save, but _sfloat2 and the things
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// that it runs are simulating the execution of individual
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// program instructions, and those instructions do not expect
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// the floating point registers to be lost.
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// An alternative would be to move the software floating point
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// registers into G, but they do not need to be kept at the
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// usual places a goroutine reschedules (at function calls),
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// so it would be a waste of 132 bytes per G.
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MOVW m_locks(m), R1
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ADD $1, R1
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MOVW R1, m_locks(m)
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BL runtime·_sfloat2(SB)
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MOVW m_locks(m), R1
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SUB $1, R1
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MOVW R1, m_locks(m)
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MOVW R0, 0(R13)
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MOVW 64(R13), R1
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WORD $0xe128f001 // msr cpsr_f, r1
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MOVW $12(R13), R0
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// Restore R1-R8 and R11-R12, but ignore the saved R9 (m) and R10 (g).
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// Both are maintained by the runtime and always have correct values,
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// so there is no need to restore old values here.
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// The g should not have changed, but m may have, if we were preempted
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// and restarted on a different thread, in which case restoring the old
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// value is incorrect and will cause serious confusion in the runtime.
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MOVM.IA.W (R0), [R1-R8]
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MOVW $52(R13), R0
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MOVM.IA.W (R0), [R11-R12]
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MOVW 8(R13), R0
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RET
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// func udiv(n, d uint32) (q, r uint32)
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// Reference:
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// Sloss, Andrew et. al; ARM System Developer's Guide: Designing and Optimizing System Software
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// Morgan Kaufmann; 1 edition (April 8, 2004), ISBN 978-1558608740
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q = 0 // input d, output q
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r = 1 // input n, output r
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s = 2 // three temporary variables
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M = 3
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a = 11
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// Be careful: R(a) == R11 will be used by the linker for synthesized instructions.
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TEXT udiv<>(SB),NOSPLIT,$-4
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CLZ R(q), R(s) // find normalizing shift
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MOVW.S R(q)<<R(s), R(a)
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MOVW $fast_udiv_tab<>-64(SB), R(M)
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MOVBU.NE R(a)>>25(R(M)), R(a) // index by most significant 7 bits of divisor
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SUB.S $7, R(s)
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RSB $0, R(q), R(M) // M = -q
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MOVW.PL R(a)<<R(s), R(q)
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// 1st Newton iteration
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MUL.PL R(M), R(q), R(a) // a = -q*d
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BMI udiv_by_large_d
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MULAWT R(a), R(q), R(q), R(q) // q approx q-(q*q*d>>32)
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TEQ R(M)->1, R(M) // check for d=0 or d=1
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// 2nd Newton iteration
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MUL.NE R(M), R(q), R(a)
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MOVW.NE $0, R(s)
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MULAL.NE R(q), R(a), (R(q),R(s))
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BEQ udiv_by_0_or_1
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// q now accurate enough for a remainder r, 0<=r<3*d
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MULLU R(q), R(r), (R(q),R(s)) // q = (r * q) >> 32
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ADD R(M), R(r), R(r) // r = n - d
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MULA R(M), R(q), R(r), R(r) // r = n - (q+1)*d
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// since 0 <= n-q*d < 3*d; thus -d <= r < 2*d
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CMN R(M), R(r) // t = r-d
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SUB.CS R(M), R(r), R(r) // if (t<-d || t>=0) r=r+d
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ADD.CC $1, R(q)
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ADD.PL R(M)<<1, R(r)
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ADD.PL $2, R(q)
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RET
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udiv_by_large_d:
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// at this point we know d>=2^(31-6)=2^25
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SUB $4, R(a), R(a)
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RSB $0, R(s), R(s)
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MOVW R(a)>>R(s), R(q)
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MULLU R(q), R(r), (R(q),R(s))
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MULA R(M), R(q), R(r), R(r)
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// q now accurate enough for a remainder r, 0<=r<4*d
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CMN R(r)>>1, R(M) // if(r/2 >= d)
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ADD.CS R(M)<<1, R(r)
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ADD.CS $2, R(q)
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CMN R(r), R(M)
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ADD.CS R(M), R(r)
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ADD.CS $1, R(q)
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RET
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udiv_by_0_or_1:
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// carry set if d==1, carry clear if d==0
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BCC udiv_by_0
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MOVW R(r), R(q)
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MOVW $0, R(r)
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RET
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udiv_by_0:
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// The ARM toolchain expects it can emit references to DIV and MOD
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// instructions. The linker rewrites each pseudo-instruction into
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// a sequence that pushes two values onto the stack and then calls
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// _divu, _modu, _div, or _mod (below), all of which have a 16-byte
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// frame plus the saved LR. The traceback routine knows the expanded
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// stack frame size at the pseudo-instruction call site, but it
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// doesn't know that the frame has a non-standard layout. In particular,
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// it expects to find a saved LR in the bottom word of the frame.
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// Unwind the stack back to the pseudo-instruction call site, copy the
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// saved LR where the traceback routine will look for it, and make it
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// appear that panicdivide was called from that PC.
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MOVW 0(R13), LR
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ADD $20, R13
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MOVW 8(R13), R1 // actual saved LR
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MOVW R1, 0(R13) // expected here for traceback
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B runtime·panicdivide(SB)
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TEXT fast_udiv_tab<>(SB),NOSPLIT,$-4
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// var tab [64]byte
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// tab[0] = 255; for i := 1; i <= 63; i++ { tab[i] = (1<<14)/(64+i) }
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// laid out here as little-endian uint32s
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WORD $0xf4f8fcff
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WORD $0xe6eaedf0
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WORD $0xdadde0e3
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WORD $0xcfd2d4d7
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WORD $0xc5c7cacc
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WORD $0xbcbec0c3
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WORD $0xb4b6b8ba
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WORD $0xacaeb0b2
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WORD $0xa5a7a8aa
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WORD $0x9fa0a2a3
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WORD $0x999a9c9d
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WORD $0x93949697
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WORD $0x8e8f9092
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WORD $0x898a8c8d
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WORD $0x85868788
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WORD $0x81828384
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// The linker will pass numerator in R(TMP), and it also
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// expects the result in R(TMP)
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TMP = 11
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TEXT _divu(SB), NOSPLIT, $16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(M), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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BL udiv<>(SB)
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MOVW R(q), R(TMP)
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(M)
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RET
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TEXT _modu(SB), NOSPLIT, $16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(M), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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BL udiv<>(SB)
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MOVW R(r), R(TMP)
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(M)
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RET
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TEXT _div(SB),NOSPLIT,$16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(M), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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CMP $0, R(r)
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BGE d1
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RSB $0, R(r), R(r)
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CMP $0, R(q)
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BGE d2
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RSB $0, R(q), R(q)
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d0:
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BL udiv<>(SB) /* none/both neg */
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MOVW R(q), R(TMP)
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B out1
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d1:
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CMP $0, R(q)
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BGE d0
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RSB $0, R(q), R(q)
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d2:
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BL udiv<>(SB) /* one neg */
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RSB $0, R(q), R(TMP)
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out1:
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(M)
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RET
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TEXT _mod(SB),NOSPLIT,$16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(M), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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CMP $0, R(q)
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RSB.LT $0, R(q), R(q)
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CMP $0, R(r)
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BGE m1
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RSB $0, R(r), R(r)
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BL udiv<>(SB) /* neg numerator */
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RSB $0, R(r), R(TMP)
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B out
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m1:
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BL udiv<>(SB) /* pos numerator */
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MOVW R(r), R(TMP)
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out:
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(M)
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RET
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