mirror of
https://github.com/golang/go
synced 2024-10-05 00:21:21 -06:00
d9c989fa25
The Plan 9 tools assume that long is 32 bits. We converted all instances of long to int32 when importing the code but missed the print formats. Because int32 is always int on the compilers we use, it is never correct to use %lux, %ld, etc. Convert to %ux, %d, etc. (It matters because on 64-bit gcc, long is 64 bits, so we were printing 32-bit quantities with 64-bit formats.) R=ken2 CC=golang-dev https://golang.org/cl/2491041
1574 lines
26 KiB
C
1574 lines
26 KiB
C
// Derived from Inferno utils/6c/reg.c
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// http://code.google.com/p/inferno-os/source/browse/utils/6c/reg.c
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#include "gg.h"
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#undef EXTERN
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#define EXTERN
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#include "opt.h"
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#define P2R(p) (Reg*)(p->reg)
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static int first = 1;
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Reg*
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rega(void)
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{
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Reg *r;
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r = freer;
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if(r == R) {
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r = mal(sizeof(*r));
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} else
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freer = r->link;
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*r = zreg;
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return r;
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}
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int
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rcmp(const void *a1, const void *a2)
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{
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Rgn *p1, *p2;
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int c1, c2;
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p1 = (Rgn*)a1;
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p2 = (Rgn*)a2;
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c1 = p2->cost;
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c2 = p1->cost;
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if(c1 -= c2)
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return c1;
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return p2->varno - p1->varno;
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}
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static void
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setoutvar(void)
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{
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Type *t;
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Node *n;
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Addr a;
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Iter save;
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Bits bit;
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int z;
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t = structfirst(&save, getoutarg(curfn->type));
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while(t != T) {
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n = nodarg(t, 1);
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a = zprog.from;
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naddr(n, &a, 0);
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bit = mkvar(R, &a);
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for(z=0; z<BITS; z++)
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ovar.b[z] |= bit.b[z];
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t = structnext(&save);
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}
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//if(bany(b))
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//print("ovars = %Q\n", &ovar);
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}
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static void
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setaddrs(Bits bit)
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{
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int i, n;
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Var *v;
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Sym *s;
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while(bany(&bit)) {
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// convert each bit to a variable
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i = bnum(bit);
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s = var[i].sym;
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n = var[i].name;
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bit.b[i/32] &= ~(1L<<(i%32));
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// disable all pieces of that variable
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for(i=0; i<nvar; i++) {
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v = var+i;
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if(v->sym == s && v->name == n)
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v->addr = 2;
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}
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}
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}
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void
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regopt(Prog *firstp)
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{
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Reg *r, *r1;
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Prog *p;
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int i, z, nr;
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uint32 vreg;
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Bits bit;
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if(first) {
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fmtinstall('Q', Qconv);
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exregoffset = D_R13; // R14,R15 are external
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first = 0;
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}
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// count instructions
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nr = 0;
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for(p=firstp; p!=P; p=p->link)
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nr++;
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// if too big dont bother
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if(nr >= 10000) {
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// print("********** %S is too big (%d)\n", curfn->nname->sym, nr);
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return;
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}
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r1 = R;
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firstr = R;
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lastr = R;
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nvar = 0;
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regbits = RtoB(D_SP);
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for(z=0; z<BITS; z++) {
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externs.b[z] = 0;
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params.b[z] = 0;
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consts.b[z] = 0;
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addrs.b[z] = 0;
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ovar.b[z] = 0;
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}
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// build list of return variables
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setoutvar();
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/*
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* pass 1
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* build aux data structure
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* allocate pcs
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* find use and set of variables
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*/
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nr = 0;
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for(p=firstp; p!=P; p=p->link) {
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switch(p->as) {
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case ADATA:
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case AGLOBL:
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case ANAME:
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case ASIGNAME:
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continue;
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}
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r = rega();
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nr++;
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if(firstr == R) {
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firstr = r;
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lastr = r;
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} else {
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lastr->link = r;
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r->p1 = lastr;
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lastr->s1 = r;
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lastr = r;
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}
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r->prog = p;
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p->reg = r;
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r1 = r->p1;
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if(r1 != R) {
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switch(r1->prog->as) {
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case ARET:
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case AJMP:
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case AIRETL:
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case AIRETQ:
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r->p1 = R;
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r1->s1 = R;
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}
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}
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bit = mkvar(r, &p->from);
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if(bany(&bit))
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switch(p->as) {
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/*
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* funny
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*/
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case ALEAL:
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case ALEAQ:
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setaddrs(bit);
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break;
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/*
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* left side read
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*/
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default:
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for(z=0; z<BITS; z++)
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r->use1.b[z] |= bit.b[z];
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break;
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/*
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* left side read+write
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*/
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case AXCHGB:
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case AXCHGW:
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case AXCHGL:
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case AXCHGQ:
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for(z=0; z<BITS; z++) {
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r->use1.b[z] |= bit.b[z];
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r->set.b[z] |= bit.b[z];
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}
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break;
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}
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bit = mkvar(r, &p->to);
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if(bany(&bit))
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switch(p->as) {
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default:
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yyerror("reg: unknown op: %A", p->as);
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break;
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/*
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* right side read
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*/
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case ACMPB:
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case ACMPL:
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case ACMPQ:
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case ACMPW:
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case ACOMISS:
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case ACOMISD:
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case AUCOMISS:
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case AUCOMISD:
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for(z=0; z<BITS; z++)
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r->use2.b[z] |= bit.b[z];
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break;
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/*
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* right side write
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*/
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case ANOP:
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case AMOVL:
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case AMOVQ:
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case AMOVB:
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case AMOVW:
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case AMOVBLSX:
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case AMOVBLZX:
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case AMOVBQSX:
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case AMOVBQZX:
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case AMOVLQSX:
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case AMOVLQZX:
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case AMOVWLSX:
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case AMOVWLZX:
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case AMOVWQSX:
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case AMOVWQZX:
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case AMOVSS:
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case AMOVSD:
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case ACVTSD2SL:
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case ACVTSD2SQ:
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case ACVTSD2SS:
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case ACVTSL2SD:
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case ACVTSL2SS:
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case ACVTSQ2SD:
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case ACVTSQ2SS:
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case ACVTSS2SD:
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case ACVTSS2SL:
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case ACVTSS2SQ:
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case ACVTTSD2SL:
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case ACVTTSD2SQ:
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case ACVTTSS2SL:
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case ACVTTSS2SQ:
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for(z=0; z<BITS; z++)
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r->set.b[z] |= bit.b[z];
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break;
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/*
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* right side read+write
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*/
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case AINCB:
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case AINCL:
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case AINCQ:
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case AINCW:
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case ADECB:
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case ADECL:
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case ADECQ:
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case ADECW:
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case AADDB:
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case AADDL:
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case AADDQ:
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case AADDW:
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case AANDB:
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case AANDL:
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case AANDQ:
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case AANDW:
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case ASUBB:
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case ASUBL:
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case ASUBQ:
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case ASUBW:
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case AORB:
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case AORL:
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case AORQ:
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case AORW:
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case AXORB:
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case AXORL:
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case AXORQ:
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case AXORW:
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case ASALB:
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case ASALL:
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case ASALQ:
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case ASALW:
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case ASARB:
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case ASARL:
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case ASARQ:
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case ASARW:
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case ARCLB:
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case ARCLL:
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case ARCLQ:
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case ARCLW:
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case ARCRB:
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case ARCRL:
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case ARCRQ:
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case ARCRW:
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case AROLB:
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case AROLL:
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case AROLQ:
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case AROLW:
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case ARORB:
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case ARORL:
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case ARORQ:
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case ARORW:
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case ASHLB:
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case ASHLL:
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case ASHLQ:
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case ASHLW:
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case ASHRB:
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case ASHRL:
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case ASHRQ:
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case ASHRW:
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case AIMULL:
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case AIMULQ:
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case AIMULW:
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case ANEGL:
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case ANEGQ:
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case ANOTL:
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case ANOTQ:
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case AADCL:
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case AADCQ:
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case ASBBL:
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case ASBBQ:
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case AXCHGB:
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case AXCHGW:
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case AXCHGL:
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case AXCHGQ:
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case AADDSD:
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case AADDSS:
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case ACMPSD:
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case ACMPSS:
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case ADIVSD:
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case ADIVSS:
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case AMAXSD:
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case AMAXSS:
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case AMINSD:
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case AMINSS:
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case AMULSD:
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case AMULSS:
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case ARCPSS:
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case ARSQRTSS:
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case ASQRTSD:
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case ASQRTSS:
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case ASUBSD:
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case ASUBSS:
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case AXORPD:
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for(z=0; z<BITS; z++) {
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r->set.b[z] |= bit.b[z];
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r->use2.b[z] |= bit.b[z];
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}
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break;
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/*
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* funny
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*/
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case ACALL:
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setaddrs(bit);
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break;
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}
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switch(p->as) {
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case AIMULL:
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case AIMULQ:
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case AIMULW:
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if(p->to.type != D_NONE)
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break;
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case AIDIVB:
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case AIDIVL:
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case AIDIVQ:
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case AIDIVW:
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case AIMULB:
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case ADIVB:
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case ADIVL:
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case ADIVQ:
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case ADIVW:
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case AMULB:
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case AMULL:
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case AMULQ:
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case AMULW:
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case ACWD:
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case ACDQ:
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case ACQO:
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r->regu |= RtoB(D_AX) | RtoB(D_DX);
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break;
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case AREP:
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case AREPN:
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case ALOOP:
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case ALOOPEQ:
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case ALOOPNE:
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r->regu |= RtoB(D_CX);
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break;
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case AMOVSB:
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case AMOVSL:
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case AMOVSQ:
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case AMOVSW:
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case ACMPSB:
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case ACMPSL:
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case ACMPSQ:
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case ACMPSW:
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r->regu |= RtoB(D_SI) | RtoB(D_DI);
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break;
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case ASTOSB:
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case ASTOSL:
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case ASTOSQ:
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case ASTOSW:
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case ASCASB:
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case ASCASL:
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case ASCASQ:
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case ASCASW:
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r->regu |= RtoB(D_AX) | RtoB(D_DI);
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break;
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case AINSB:
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case AINSL:
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case AINSW:
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case AOUTSB:
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case AOUTSL:
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case AOUTSW:
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r->regu |= RtoB(D_DI) | RtoB(D_DX);
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break;
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}
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}
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if(firstr == R)
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return;
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for(i=0; i<nvar; i++) {
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Var *v = var+i;
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if(v->addr) {
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bit = blsh(i);
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for(z=0; z<BITS; z++)
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addrs.b[z] |= bit.b[z];
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}
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|
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// print("bit=%2d addr=%d et=%-6E w=%-2d s=%S + %lld\n",
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// i, v->addr, v->etype, v->width, v->sym, v->offset);
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}
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if(debug['R'] && debug['v'])
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dumpit("pass1", firstr);
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/*
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* pass 2
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* turn branch references to pointers
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* build back pointers
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*/
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for(r=firstr; r!=R; r=r->link) {
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p = r->prog;
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if(p->to.type == D_BRANCH) {
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if(p->to.branch == P)
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fatal("pnil %P", p);
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r1 = p->to.branch->reg;
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if(r1 == R)
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fatal("rnil %P", p);
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if(r1 == r) {
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//fatal("ref to self %P", p);
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continue;
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}
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r->s2 = r1;
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r->p2link = r1->p2;
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r1->p2 = r;
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}
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}
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|
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if(debug['R'] && debug['v'])
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dumpit("pass2", firstr);
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|
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/*
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* pass 2.5
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* find looping structure
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*/
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for(r = firstr; r != R; r = r->link)
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r->active = 0;
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change = 0;
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loopit(firstr, nr);
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|
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if(debug['R'] && debug['v'])
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dumpit("pass2.5", firstr);
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|
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/*
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* pass 3
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* iterate propagating usage
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* back until flow graph is complete
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*/
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loop1:
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change = 0;
|
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for(r = firstr; r != R; r = r->link)
|
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r->active = 0;
|
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for(r = firstr; r != R; r = r->link)
|
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if(r->prog->as == ARET)
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prop(r, zbits, zbits);
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loop11:
|
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/* pick up unreachable code */
|
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i = 0;
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for(r = firstr; r != R; r = r1) {
|
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r1 = r->link;
|
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if(r1 && r1->active && !r->active) {
|
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prop(r, zbits, zbits);
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i = 1;
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}
|
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}
|
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if(i)
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goto loop11;
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if(change)
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goto loop1;
|
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|
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if(debug['R'] && debug['v'])
|
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dumpit("pass3", firstr);
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|
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/*
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* pass 4
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* iterate propagating register/variable synchrony
|
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* forward until graph is complete
|
|
*/
|
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loop2:
|
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change = 0;
|
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for(r = firstr; r != R; r = r->link)
|
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r->active = 0;
|
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synch(firstr, zbits);
|
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if(change)
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goto loop2;
|
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|
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if(debug['R'] && debug['v'])
|
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dumpit("pass4", firstr);
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|
|
/*
|
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* pass 5
|
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* isolate regions
|
|
* calculate costs (paint1)
|
|
*/
|
|
r = firstr;
|
|
if(r) {
|
|
for(z=0; z<BITS; z++)
|
|
bit.b[z] = (r->refahead.b[z] | r->calahead.b[z]) &
|
|
~(externs.b[z] | params.b[z] | addrs.b[z] | consts.b[z]);
|
|
if(bany(&bit) && !r->refset) {
|
|
// should never happen - all variables are preset
|
|
if(debug['w'])
|
|
print("%L: used and not set: %Q\n", r->prog->lineno, bit);
|
|
r->refset = 1;
|
|
}
|
|
}
|
|
for(r = firstr; r != R; r = r->link)
|
|
r->act = zbits;
|
|
rgp = region;
|
|
nregion = 0;
|
|
for(r = firstr; r != R; r = r->link) {
|
|
for(z=0; z<BITS; z++)
|
|
bit.b[z] = r->set.b[z] &
|
|
~(r->refahead.b[z] | r->calahead.b[z] | addrs.b[z]);
|
|
if(bany(&bit) && !r->refset) {
|
|
if(debug['w'])
|
|
print("%L: set and not used: %Q\n", r->prog->lineno, bit);
|
|
r->refset = 1;
|
|
excise(r);
|
|
}
|
|
for(z=0; z<BITS; z++)
|
|
bit.b[z] = LOAD(r) & ~(r->act.b[z] | addrs.b[z]);
|
|
while(bany(&bit)) {
|
|
i = bnum(bit);
|
|
rgp->enter = r;
|
|
rgp->varno = i;
|
|
change = 0;
|
|
paint1(r, i);
|
|
bit.b[i/32] &= ~(1L<<(i%32));
|
|
if(change <= 0)
|
|
continue;
|
|
rgp->cost = change;
|
|
nregion++;
|
|
if(nregion >= NRGN) {
|
|
if(debug['R'] && debug['v'])
|
|
print("too many regions\n");
|
|
goto brk;
|
|
}
|
|
rgp++;
|
|
}
|
|
}
|
|
brk:
|
|
qsort(region, nregion, sizeof(region[0]), rcmp);
|
|
|
|
/*
|
|
* pass 6
|
|
* determine used registers (paint2)
|
|
* replace code (paint3)
|
|
*/
|
|
rgp = region;
|
|
for(i=0; i<nregion; i++) {
|
|
bit = blsh(rgp->varno);
|
|
vreg = paint2(rgp->enter, rgp->varno);
|
|
vreg = allreg(vreg, rgp);
|
|
if(rgp->regno != 0)
|
|
paint3(rgp->enter, rgp->varno, vreg, rgp->regno);
|
|
rgp++;
|
|
}
|
|
|
|
if(debug['R'] && debug['v'])
|
|
dumpit("pass6", firstr);
|
|
|
|
/*
|
|
* pass 7
|
|
* peep-hole on basic block
|
|
*/
|
|
if(!debug['R'] || debug['P']) {
|
|
peep();
|
|
}
|
|
|
|
/*
|
|
* eliminate nops
|
|
* free aux structures
|
|
*/
|
|
for(p=firstp; p!=P; p=p->link) {
|
|
while(p->link != P && p->link->as == ANOP)
|
|
p->link = p->link->link;
|
|
if(p->to.type == D_BRANCH)
|
|
while(p->to.branch != P && p->to.branch->as == ANOP)
|
|
p->to.branch = p->to.branch->link;
|
|
}
|
|
|
|
if(r1 != R) {
|
|
r1->link = freer;
|
|
freer = firstr;
|
|
}
|
|
|
|
if(debug['R']) {
|
|
if(ostats.ncvtreg ||
|
|
ostats.nspill ||
|
|
ostats.nreload ||
|
|
ostats.ndelmov ||
|
|
ostats.nvar ||
|
|
ostats.naddr ||
|
|
0)
|
|
print("\nstats\n");
|
|
|
|
if(ostats.ncvtreg)
|
|
print(" %4d cvtreg\n", ostats.ncvtreg);
|
|
if(ostats.nspill)
|
|
print(" %4d spill\n", ostats.nspill);
|
|
if(ostats.nreload)
|
|
print(" %4d reload\n", ostats.nreload);
|
|
if(ostats.ndelmov)
|
|
print(" %4d delmov\n", ostats.ndelmov);
|
|
if(ostats.nvar)
|
|
print(" %4d delmov\n", ostats.nvar);
|
|
if(ostats.naddr)
|
|
print(" %4d delmov\n", ostats.naddr);
|
|
|
|
memset(&ostats, 0, sizeof(ostats));
|
|
}
|
|
}
|
|
|
|
/*
|
|
* add mov b,rn
|
|
* just after r
|
|
*/
|
|
void
|
|
addmove(Reg *r, int bn, int rn, int f)
|
|
{
|
|
Prog *p, *p1;
|
|
Adr *a;
|
|
Var *v;
|
|
|
|
p1 = mal(sizeof(*p1));
|
|
clearp(p1);
|
|
p1->loc = 9999;
|
|
|
|
p = r->prog;
|
|
p1->link = p->link;
|
|
p->link = p1;
|
|
p1->lineno = p->lineno;
|
|
|
|
v = var + bn;
|
|
|
|
a = &p1->to;
|
|
a->sym = v->sym;
|
|
a->offset = v->offset;
|
|
a->etype = v->etype;
|
|
a->type = v->name;
|
|
a->gotype = v->gotype;
|
|
|
|
// need to clean this up with wptr and
|
|
// some of the defaults
|
|
p1->as = AMOVL;
|
|
switch(v->etype) {
|
|
default:
|
|
fatal("unknown type\n");
|
|
case TINT8:
|
|
case TUINT8:
|
|
case TBOOL:
|
|
p1->as = AMOVB;
|
|
break;
|
|
case TINT16:
|
|
case TUINT16:
|
|
p1->as = AMOVW;
|
|
break;
|
|
case TINT64:
|
|
case TUINT64:
|
|
case TUINTPTR:
|
|
case TPTR64:
|
|
p1->as = AMOVQ;
|
|
break;
|
|
case TFLOAT:
|
|
case TFLOAT32:
|
|
p1->as = AMOVSS;
|
|
break;
|
|
case TFLOAT64:
|
|
p1->as = AMOVSD;
|
|
break;
|
|
case TINT:
|
|
case TUINT:
|
|
case TINT32:
|
|
case TUINT32:
|
|
case TPTR32:
|
|
break;
|
|
}
|
|
|
|
p1->from.type = rn;
|
|
if(!f) {
|
|
p1->from = *a;
|
|
*a = zprog.from;
|
|
a->type = rn;
|
|
if(v->etype == TUINT8)
|
|
p1->as = AMOVB;
|
|
if(v->etype == TUINT16)
|
|
p1->as = AMOVW;
|
|
}
|
|
if(debug['R'] && debug['v'])
|
|
print("%P ===add=== %P\n", p, p1);
|
|
ostats.nspill++;
|
|
}
|
|
|
|
uint32
|
|
doregbits(int r)
|
|
{
|
|
uint32 b;
|
|
|
|
b = 0;
|
|
if(r >= D_INDIR)
|
|
r -= D_INDIR;
|
|
if(r >= D_AX && r <= D_R15)
|
|
b |= RtoB(r);
|
|
else
|
|
if(r >= D_AL && r <= D_R15B)
|
|
b |= RtoB(r-D_AL+D_AX);
|
|
else
|
|
if(r >= D_AH && r <= D_BH)
|
|
b |= RtoB(r-D_AH+D_AX);
|
|
else
|
|
if(r >= D_X0 && r <= D_X0+15)
|
|
b |= FtoB(r);
|
|
return b;
|
|
}
|
|
|
|
static int
|
|
overlap(int32 o1, int w1, int32 o2, int w2)
|
|
{
|
|
int32 t1, t2;
|
|
|
|
t1 = o1+w1;
|
|
t2 = o2+w2;
|
|
|
|
if(!(t1 > o2 && t2 > o1))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
Bits
|
|
mkvar(Reg *r, Adr *a)
|
|
{
|
|
Var *v;
|
|
int i, t, n, et, z, w, flag;
|
|
int32 o;
|
|
Bits bit;
|
|
Sym *s;
|
|
|
|
/*
|
|
* mark registers used
|
|
*/
|
|
t = a->type;
|
|
if(t == D_NONE)
|
|
goto none;
|
|
|
|
if(r != R) {
|
|
r->regu |= doregbits(t);
|
|
r->regu |= doregbits(a->index);
|
|
}
|
|
|
|
switch(t) {
|
|
default:
|
|
goto none;
|
|
|
|
case D_ADDR:
|
|
a->type = a->index;
|
|
bit = mkvar(r, a);
|
|
setaddrs(bit);
|
|
a->type = t;
|
|
ostats.naddr++;
|
|
goto none;
|
|
|
|
case D_EXTERN:
|
|
case D_STATIC:
|
|
case D_PARAM:
|
|
case D_AUTO:
|
|
n = t;
|
|
break;
|
|
}
|
|
s = a->sym;
|
|
if(s == S)
|
|
goto none;
|
|
if(s->name[0] == '.')
|
|
goto none;
|
|
et = a->etype;
|
|
o = a->offset;
|
|
w = a->width;
|
|
|
|
flag = 0;
|
|
for(i=0; i<nvar; i++) {
|
|
v = var+i;
|
|
if(v->sym == s && v->name == n) {
|
|
if(v->offset == o)
|
|
if(v->etype == et)
|
|
if(v->width == w)
|
|
return blsh(i);
|
|
|
|
// if they overlaps, disable both
|
|
if(overlap(v->offset, v->width, o, w)) {
|
|
v->addr = 1;
|
|
flag = 1;
|
|
}
|
|
}
|
|
}
|
|
if(a->pun)
|
|
flag = 1;
|
|
|
|
switch(et) {
|
|
case 0:
|
|
case TFUNC:
|
|
goto none;
|
|
}
|
|
|
|
if(nvar >= NVAR) {
|
|
if(debug['w'] > 1 && s)
|
|
fatal("variable not optimized: %D", a);
|
|
goto none;
|
|
}
|
|
|
|
i = nvar;
|
|
nvar++;
|
|
v = var+i;
|
|
v->sym = s;
|
|
v->offset = o;
|
|
v->name = n;
|
|
v->gotype = a->gotype;
|
|
v->etype = et;
|
|
v->width = w;
|
|
v->addr = flag; // funny punning
|
|
|
|
if(debug['R'])
|
|
print("bit=%2d et=%2d w=%d %S %D\n", i, et, w, s, a);
|
|
ostats.nvar++;
|
|
|
|
bit = blsh(i);
|
|
if(n == D_EXTERN || n == D_STATIC)
|
|
for(z=0; z<BITS; z++)
|
|
externs.b[z] |= bit.b[z];
|
|
if(n == D_PARAM)
|
|
for(z=0; z<BITS; z++)
|
|
params.b[z] |= bit.b[z];
|
|
|
|
return bit;
|
|
|
|
none:
|
|
return zbits;
|
|
}
|
|
|
|
void
|
|
prop(Reg *r, Bits ref, Bits cal)
|
|
{
|
|
Reg *r1, *r2;
|
|
int z;
|
|
|
|
for(r1 = r; r1 != R; r1 = r1->p1) {
|
|
for(z=0; z<BITS; z++) {
|
|
ref.b[z] |= r1->refahead.b[z];
|
|
if(ref.b[z] != r1->refahead.b[z]) {
|
|
r1->refahead.b[z] = ref.b[z];
|
|
change++;
|
|
}
|
|
cal.b[z] |= r1->calahead.b[z];
|
|
if(cal.b[z] != r1->calahead.b[z]) {
|
|
r1->calahead.b[z] = cal.b[z];
|
|
change++;
|
|
}
|
|
}
|
|
switch(r1->prog->as) {
|
|
case ACALL:
|
|
if(noreturn(r1->prog))
|
|
break;
|
|
for(z=0; z<BITS; z++) {
|
|
cal.b[z] |= ref.b[z] | externs.b[z];
|
|
ref.b[z] = 0;
|
|
}
|
|
break;
|
|
|
|
case ATEXT:
|
|
for(z=0; z<BITS; z++) {
|
|
cal.b[z] = 0;
|
|
ref.b[z] = 0;
|
|
}
|
|
break;
|
|
|
|
case ARET:
|
|
for(z=0; z<BITS; z++) {
|
|
cal.b[z] = externs.b[z] | ovar.b[z];
|
|
ref.b[z] = 0;
|
|
}
|
|
break;
|
|
}
|
|
for(z=0; z<BITS; z++) {
|
|
ref.b[z] = (ref.b[z] & ~r1->set.b[z]) |
|
|
r1->use1.b[z] | r1->use2.b[z];
|
|
cal.b[z] &= ~(r1->set.b[z] | r1->use1.b[z] | r1->use2.b[z]);
|
|
r1->refbehind.b[z] = ref.b[z];
|
|
r1->calbehind.b[z] = cal.b[z];
|
|
}
|
|
if(r1->active)
|
|
break;
|
|
r1->active = 1;
|
|
}
|
|
for(; r != r1; r = r->p1)
|
|
for(r2 = r->p2; r2 != R; r2 = r2->p2link)
|
|
prop(r2, r->refbehind, r->calbehind);
|
|
}
|
|
|
|
/*
|
|
* find looping structure
|
|
*
|
|
* 1) find reverse postordering
|
|
* 2) find approximate dominators,
|
|
* the actual dominators if the flow graph is reducible
|
|
* otherwise, dominators plus some other non-dominators.
|
|
* See Matthew S. Hecht and Jeffrey D. Ullman,
|
|
* "Analysis of a Simple Algorithm for Global Data Flow Problems",
|
|
* Conf. Record of ACM Symp. on Principles of Prog. Langs, Boston, Massachusetts,
|
|
* Oct. 1-3, 1973, pp. 207-217.
|
|
* 3) find all nodes with a predecessor dominated by the current node.
|
|
* such a node is a loop head.
|
|
* recursively, all preds with a greater rpo number are in the loop
|
|
*/
|
|
int32
|
|
postorder(Reg *r, Reg **rpo2r, int32 n)
|
|
{
|
|
Reg *r1;
|
|
|
|
r->rpo = 1;
|
|
r1 = r->s1;
|
|
if(r1 && !r1->rpo)
|
|
n = postorder(r1, rpo2r, n);
|
|
r1 = r->s2;
|
|
if(r1 && !r1->rpo)
|
|
n = postorder(r1, rpo2r, n);
|
|
rpo2r[n] = r;
|
|
n++;
|
|
return n;
|
|
}
|
|
|
|
int32
|
|
rpolca(int32 *idom, int32 rpo1, int32 rpo2)
|
|
{
|
|
int32 t;
|
|
|
|
if(rpo1 == -1)
|
|
return rpo2;
|
|
while(rpo1 != rpo2){
|
|
if(rpo1 > rpo2){
|
|
t = rpo2;
|
|
rpo2 = rpo1;
|
|
rpo1 = t;
|
|
}
|
|
while(rpo1 < rpo2){
|
|
t = idom[rpo2];
|
|
if(t >= rpo2)
|
|
fatal("bad idom");
|
|
rpo2 = t;
|
|
}
|
|
}
|
|
return rpo1;
|
|
}
|
|
|
|
int
|
|
doms(int32 *idom, int32 r, int32 s)
|
|
{
|
|
while(s > r)
|
|
s = idom[s];
|
|
return s == r;
|
|
}
|
|
|
|
int
|
|
loophead(int32 *idom, Reg *r)
|
|
{
|
|
int32 src;
|
|
|
|
src = r->rpo;
|
|
if(r->p1 != R && doms(idom, src, r->p1->rpo))
|
|
return 1;
|
|
for(r = r->p2; r != R; r = r->p2link)
|
|
if(doms(idom, src, r->rpo))
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
loopmark(Reg **rpo2r, int32 head, Reg *r)
|
|
{
|
|
if(r->rpo < head || r->active == head)
|
|
return;
|
|
r->active = head;
|
|
r->loop += LOOP;
|
|
if(r->p1 != R)
|
|
loopmark(rpo2r, head, r->p1);
|
|
for(r = r->p2; r != R; r = r->p2link)
|
|
loopmark(rpo2r, head, r);
|
|
}
|
|
|
|
void
|
|
loopit(Reg *r, int32 nr)
|
|
{
|
|
Reg *r1;
|
|
int32 i, d, me;
|
|
|
|
if(nr > maxnr) {
|
|
rpo2r = mal(nr * sizeof(Reg*));
|
|
idom = mal(nr * sizeof(int32));
|
|
maxnr = nr;
|
|
}
|
|
|
|
d = postorder(r, rpo2r, 0);
|
|
if(d > nr)
|
|
fatal("too many reg nodes %d %d", d, nr);
|
|
nr = d;
|
|
for(i = 0; i < nr / 2; i++) {
|
|
r1 = rpo2r[i];
|
|
rpo2r[i] = rpo2r[nr - 1 - i];
|
|
rpo2r[nr - 1 - i] = r1;
|
|
}
|
|
for(i = 0; i < nr; i++)
|
|
rpo2r[i]->rpo = i;
|
|
|
|
idom[0] = 0;
|
|
for(i = 0; i < nr; i++) {
|
|
r1 = rpo2r[i];
|
|
me = r1->rpo;
|
|
d = -1;
|
|
if(r1->p1 != R && r1->p1->rpo < me)
|
|
d = r1->p1->rpo;
|
|
for(r1 = r1->p2; r1 != nil; r1 = r1->p2link)
|
|
if(r1->rpo < me)
|
|
d = rpolca(idom, d, r1->rpo);
|
|
idom[i] = d;
|
|
}
|
|
|
|
for(i = 0; i < nr; i++) {
|
|
r1 = rpo2r[i];
|
|
r1->loop++;
|
|
if(r1->p2 != R && loophead(idom, r1))
|
|
loopmark(rpo2r, i, r1);
|
|
}
|
|
}
|
|
|
|
void
|
|
synch(Reg *r, Bits dif)
|
|
{
|
|
Reg *r1;
|
|
int z;
|
|
|
|
for(r1 = r; r1 != R; r1 = r1->s1) {
|
|
for(z=0; z<BITS; z++) {
|
|
dif.b[z] = (dif.b[z] &
|
|
~(~r1->refbehind.b[z] & r1->refahead.b[z])) |
|
|
r1->set.b[z] | r1->regdiff.b[z];
|
|
if(dif.b[z] != r1->regdiff.b[z]) {
|
|
r1->regdiff.b[z] = dif.b[z];
|
|
change++;
|
|
}
|
|
}
|
|
if(r1->active)
|
|
break;
|
|
r1->active = 1;
|
|
for(z=0; z<BITS; z++)
|
|
dif.b[z] &= ~(~r1->calbehind.b[z] & r1->calahead.b[z]);
|
|
if(r1->s2 != R)
|
|
synch(r1->s2, dif);
|
|
}
|
|
}
|
|
|
|
uint32
|
|
allreg(uint32 b, Rgn *r)
|
|
{
|
|
Var *v;
|
|
int i;
|
|
|
|
v = var + r->varno;
|
|
r->regno = 0;
|
|
switch(v->etype) {
|
|
|
|
default:
|
|
fatal("unknown etype %d/%E", bitno(b), v->etype);
|
|
break;
|
|
|
|
case TINT8:
|
|
case TUINT8:
|
|
case TINT16:
|
|
case TUINT16:
|
|
case TINT32:
|
|
case TUINT32:
|
|
case TINT64:
|
|
case TUINT64:
|
|
case TINT:
|
|
case TUINT:
|
|
case TUINTPTR:
|
|
case TBOOL:
|
|
case TPTR32:
|
|
case TPTR64:
|
|
i = BtoR(~b);
|
|
if(i && r->cost > 0) {
|
|
r->regno = i;
|
|
return RtoB(i);
|
|
}
|
|
break;
|
|
|
|
case TFLOAT32:
|
|
case TFLOAT64:
|
|
case TFLOAT:
|
|
i = BtoF(~b);
|
|
if(i && r->cost > 0) {
|
|
r->regno = i;
|
|
return FtoB(i);
|
|
}
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
paint1(Reg *r, int bn)
|
|
{
|
|
Reg *r1;
|
|
Prog *p;
|
|
int z;
|
|
uint32 bb;
|
|
|
|
z = bn/32;
|
|
bb = 1L<<(bn%32);
|
|
if(r->act.b[z] & bb)
|
|
return;
|
|
for(;;) {
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
r1 = r->p1;
|
|
if(r1 == R)
|
|
break;
|
|
if(!(r1->refahead.b[z] & bb))
|
|
break;
|
|
if(r1->act.b[z] & bb)
|
|
break;
|
|
r = r1;
|
|
}
|
|
|
|
if(LOAD(r) & ~(r->set.b[z]&~(r->use1.b[z]|r->use2.b[z])) & bb) {
|
|
change -= CLOAD * r->loop;
|
|
}
|
|
for(;;) {
|
|
r->act.b[z] |= bb;
|
|
p = r->prog;
|
|
|
|
if(r->use1.b[z] & bb) {
|
|
change += CREF * r->loop;
|
|
}
|
|
|
|
if((r->use2.b[z]|r->set.b[z]) & bb) {
|
|
change += CREF * r->loop;
|
|
}
|
|
|
|
if(STORE(r) & r->regdiff.b[z] & bb) {
|
|
change -= CLOAD * r->loop;
|
|
}
|
|
|
|
if(r->refbehind.b[z] & bb)
|
|
for(r1 = r->p2; r1 != R; r1 = r1->p2link)
|
|
if(r1->refahead.b[z] & bb)
|
|
paint1(r1, bn);
|
|
|
|
if(!(r->refahead.b[z] & bb))
|
|
break;
|
|
r1 = r->s2;
|
|
if(r1 != R)
|
|
if(r1->refbehind.b[z] & bb)
|
|
paint1(r1, bn);
|
|
r = r->s1;
|
|
if(r == R)
|
|
break;
|
|
if(r->act.b[z] & bb)
|
|
break;
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
}
|
|
}
|
|
|
|
uint32
|
|
regset(Reg *r, uint32 bb)
|
|
{
|
|
uint32 b, set;
|
|
Adr v;
|
|
int c;
|
|
|
|
set = 0;
|
|
v = zprog.from;
|
|
while(b = bb & ~(bb-1)) {
|
|
v.type = b & 0xFFFF? BtoR(b): BtoF(b);
|
|
if(v.type == 0)
|
|
fatal("zero v.type for %#ux", b);
|
|
c = copyu(r->prog, &v, A);
|
|
if(c == 3)
|
|
set |= b;
|
|
bb &= ~b;
|
|
}
|
|
return set;
|
|
}
|
|
|
|
uint32
|
|
reguse(Reg *r, uint32 bb)
|
|
{
|
|
uint32 b, set;
|
|
Adr v;
|
|
int c;
|
|
|
|
set = 0;
|
|
v = zprog.from;
|
|
while(b = bb & ~(bb-1)) {
|
|
v.type = b & 0xFFFF? BtoR(b): BtoF(b);
|
|
c = copyu(r->prog, &v, A);
|
|
if(c == 1 || c == 2 || c == 4)
|
|
set |= b;
|
|
bb &= ~b;
|
|
}
|
|
return set;
|
|
}
|
|
|
|
uint32
|
|
paint2(Reg *r, int bn)
|
|
{
|
|
Reg *r1;
|
|
int z;
|
|
uint32 bb, vreg, x;
|
|
|
|
z = bn/32;
|
|
bb = 1L << (bn%32);
|
|
vreg = regbits;
|
|
if(!(r->act.b[z] & bb))
|
|
return vreg;
|
|
for(;;) {
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
r1 = r->p1;
|
|
if(r1 == R)
|
|
break;
|
|
if(!(r1->refahead.b[z] & bb))
|
|
break;
|
|
if(!(r1->act.b[z] & bb))
|
|
break;
|
|
r = r1;
|
|
}
|
|
for(;;) {
|
|
r->act.b[z] &= ~bb;
|
|
|
|
vreg |= r->regu;
|
|
|
|
if(r->refbehind.b[z] & bb)
|
|
for(r1 = r->p2; r1 != R; r1 = r1->p2link)
|
|
if(r1->refahead.b[z] & bb)
|
|
vreg |= paint2(r1, bn);
|
|
|
|
if(!(r->refahead.b[z] & bb))
|
|
break;
|
|
r1 = r->s2;
|
|
if(r1 != R)
|
|
if(r1->refbehind.b[z] & bb)
|
|
vreg |= paint2(r1, bn);
|
|
r = r->s1;
|
|
if(r == R)
|
|
break;
|
|
if(!(r->act.b[z] & bb))
|
|
break;
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
}
|
|
|
|
bb = vreg;
|
|
for(; r; r=r->s1) {
|
|
x = r->regu & ~bb;
|
|
if(x) {
|
|
vreg |= reguse(r, x);
|
|
bb |= regset(r, x);
|
|
}
|
|
}
|
|
return vreg;
|
|
}
|
|
|
|
void
|
|
paint3(Reg *r, int bn, int32 rb, int rn)
|
|
{
|
|
Reg *r1;
|
|
Prog *p;
|
|
int z;
|
|
uint32 bb;
|
|
|
|
z = bn/32;
|
|
bb = 1L << (bn%32);
|
|
if(r->act.b[z] & bb)
|
|
return;
|
|
for(;;) {
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
r1 = r->p1;
|
|
if(r1 == R)
|
|
break;
|
|
if(!(r1->refahead.b[z] & bb))
|
|
break;
|
|
if(r1->act.b[z] & bb)
|
|
break;
|
|
r = r1;
|
|
}
|
|
|
|
if(LOAD(r) & ~(r->set.b[z] & ~(r->use1.b[z]|r->use2.b[z])) & bb)
|
|
addmove(r, bn, rn, 0);
|
|
for(;;) {
|
|
r->act.b[z] |= bb;
|
|
p = r->prog;
|
|
|
|
if(r->use1.b[z] & bb) {
|
|
if(debug['R'] && debug['v'])
|
|
print("%P", p);
|
|
addreg(&p->from, rn);
|
|
if(debug['R'] && debug['v'])
|
|
print(" ===change== %P\n", p);
|
|
}
|
|
if((r->use2.b[z]|r->set.b[z]) & bb) {
|
|
if(debug['R'] && debug['v'])
|
|
print("%P", p);
|
|
addreg(&p->to, rn);
|
|
if(debug['R'] && debug['v'])
|
|
print(" ===change== %P\n", p);
|
|
}
|
|
|
|
if(STORE(r) & r->regdiff.b[z] & bb)
|
|
addmove(r, bn, rn, 1);
|
|
r->regu |= rb;
|
|
|
|
if(r->refbehind.b[z] & bb)
|
|
for(r1 = r->p2; r1 != R; r1 = r1->p2link)
|
|
if(r1->refahead.b[z] & bb)
|
|
paint3(r1, bn, rb, rn);
|
|
|
|
if(!(r->refahead.b[z] & bb))
|
|
break;
|
|
r1 = r->s2;
|
|
if(r1 != R)
|
|
if(r1->refbehind.b[z] & bb)
|
|
paint3(r1, bn, rb, rn);
|
|
r = r->s1;
|
|
if(r == R)
|
|
break;
|
|
if(r->act.b[z] & bb)
|
|
break;
|
|
if(!(r->refbehind.b[z] & bb))
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
addreg(Adr *a, int rn)
|
|
{
|
|
|
|
a->sym = 0;
|
|
a->offset = 0;
|
|
a->type = rn;
|
|
|
|
ostats.ncvtreg++;
|
|
}
|
|
|
|
int32
|
|
RtoB(int r)
|
|
{
|
|
|
|
if(r < D_AX || r > D_R15)
|
|
return 0;
|
|
return 1L << (r-D_AX);
|
|
}
|
|
|
|
int
|
|
BtoR(int32 b)
|
|
{
|
|
b &= 0x3fffL; // no R14 or R15
|
|
if(b == 0)
|
|
return 0;
|
|
return bitno(b) + D_AX;
|
|
}
|
|
|
|
/*
|
|
* bit reg
|
|
* 16 X5 (FREGMIN)
|
|
* ...
|
|
* 26 X15 (FREGEXT)
|
|
*/
|
|
int32
|
|
FtoB(int f)
|
|
{
|
|
if(f < FREGMIN || f > FREGEXT)
|
|
return 0;
|
|
return 1L << (f - FREGMIN + 16);
|
|
}
|
|
|
|
int
|
|
BtoF(int32 b)
|
|
{
|
|
|
|
b &= 0xFF0000L;
|
|
if(b == 0)
|
|
return 0;
|
|
return bitno(b) - 16 + FREGMIN;
|
|
}
|
|
|
|
void
|
|
dumpone(Reg *r)
|
|
{
|
|
int z;
|
|
Bits bit;
|
|
|
|
print("%d:%P", r->loop, r->prog);
|
|
for(z=0; z<BITS; z++)
|
|
bit.b[z] =
|
|
r->set.b[z] |
|
|
r->use1.b[z] |
|
|
r->use2.b[z] |
|
|
r->refbehind.b[z] |
|
|
r->refahead.b[z] |
|
|
r->calbehind.b[z] |
|
|
r->calahead.b[z] |
|
|
r->regdiff.b[z] |
|
|
r->act.b[z] |
|
|
0;
|
|
if(bany(&bit)) {
|
|
print("\t");
|
|
if(bany(&r->set))
|
|
print(" s:%Q", r->set);
|
|
if(bany(&r->use1))
|
|
print(" u1:%Q", r->use1);
|
|
if(bany(&r->use2))
|
|
print(" u2:%Q", r->use2);
|
|
if(bany(&r->refbehind))
|
|
print(" rb:%Q ", r->refbehind);
|
|
if(bany(&r->refahead))
|
|
print(" ra:%Q ", r->refahead);
|
|
if(bany(&r->calbehind))
|
|
print("cb:%Q ", r->calbehind);
|
|
if(bany(&r->calahead))
|
|
print(" ca:%Q ", r->calahead);
|
|
if(bany(&r->regdiff))
|
|
print(" d:%Q ", r->regdiff);
|
|
if(bany(&r->act))
|
|
print(" a:%Q ", r->act);
|
|
}
|
|
print("\n");
|
|
}
|
|
|
|
void
|
|
dumpit(char *str, Reg *r0)
|
|
{
|
|
Reg *r, *r1;
|
|
|
|
print("\n%s\n", str);
|
|
for(r = r0; r != R; r = r->link) {
|
|
dumpone(r);
|
|
r1 = r->p2;
|
|
if(r1 != R) {
|
|
print(" pred:");
|
|
for(; r1 != R; r1 = r1->p2link)
|
|
print(" %.4ud", r1->prog->loc);
|
|
print("\n");
|
|
}
|
|
// r1 = r->s1;
|
|
// if(r1 != R) {
|
|
// print(" succ:");
|
|
// for(; r1 != R; r1 = r1->s1)
|
|
// print(" %.4ud", r1->prog->loc);
|
|
// print("\n");
|
|
// }
|
|
}
|
|
}
|
|
|
|
static Sym* symlist[10];
|
|
|
|
int
|
|
noreturn(Prog *p)
|
|
{
|
|
Sym *s;
|
|
int i;
|
|
|
|
if(symlist[0] == S) {
|
|
symlist[0] = pkglookup("panicindex", runtimepkg);
|
|
symlist[1] = pkglookup("panicslice", runtimepkg);
|
|
symlist[2] = pkglookup("throwinit", runtimepkg);
|
|
symlist[3] = pkglookup("panic", runtimepkg);
|
|
}
|
|
|
|
s = p->to.sym;
|
|
if(s == S)
|
|
return 0;
|
|
for(i=0; symlist[i]!=S; i++)
|
|
if(s == symlist[i])
|
|
return 1;
|
|
return 0;
|
|
}
|