b97b1456ae
For mips32 currently, we are using FP32, while the gcc may be FPXX, which may generate .MIPS.abiflags and .gnu.attributes section with value as FPXX. So the kernel will treat the exe as FPXX, and may choose to use FR=1 FPU mode for it. Currently, in Go, we use 2 lwc1 to load both half of a double value to a pair of even-odd FPR. This behavior can only work with FR=0 mode. In FR=1 mode, all of 32 FPR are 64bit. If we lwc1 the high-half of a double value to an odd FPR, and try to use the previous even FPR to compute, the real high-half of even FPR will be unpredicatable. We set -mfp32 to force the gcc generate FP32 code and section value. More details about FP32/FPXX/FP64 are explained in: https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking When GOMIPS/GOMIPS64 is set as softfloat, we should also pass -msoft-float to gcc. Here we also add -mno-odd-spreg option, since Loongson's CPU cannot use odd-number FR in FR=0 mode. Fixes #39435 Change-Id: I54026ad416a815fe43a9261ebf6d02e5519c3930 Reviewed-on: https://go-review.googlesource.com/c/go/+/237058 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Trust: Meng Zhuo <mzh@golangcn.org> |
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