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https://github.com/golang/go
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70c7fb75e9
The code generation on riscv64 will currently result in incorrect assembly when a 32 bit integer is right shifted by an amount that exceeds the size of the type. In particular, this occurs when an int32 or uint32 is cast to a 64 bit type and right shifted by a value larger than 31. Fix this by moving the SRAW/SRLW conversion into the right shift rules and removing the SignExt32to64/ZeroExt32to64. Add additional rules that rewrite to SRAIW/SRLIW when the shift is less than the size of the type, or replace/eliminate the shift when it exceeds the size of the type. Add SSA tests that would have caught this issue. Also add additional codegen tests to ensure that the resulting assembly is what we expect in these overflow cases. Fixes #64285 Change-Id: Ie97b05668597cfcb91413afefaab18ee1aa145ec Reviewed-on: https://go-review.googlesource.com/c/go/+/545035 Reviewed-by: Russ Cox <rsc@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: M Zhuo <mzh@golangcn.org> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Run-TryBot: Joel Sing <joel@sing.id.au> TryBot-Result: Gopher Robot <gobot@golang.org>
477 lines
11 KiB
Go
477 lines
11 KiB
Go
// asmcheck
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// Copyright 2018 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package codegen
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// ------------------ //
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// constant shifts //
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// ------------------ //
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func lshConst64x64(v int64) int64 {
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// ppc64x:"SLD"
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// riscv64:"SLLI",-"AND",-"SLTIU"
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return v << uint64(33)
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}
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func rshConst64Ux64(v uint64) uint64 {
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// ppc64x:"SRD"
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// riscv64:"SRLI\t",-"AND",-"SLTIU"
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return v >> uint64(33)
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}
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func rshConst64Ux64Overflow32(v uint32) uint64 {
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// riscv64:"MOV\t\\$0,",-"SRL"
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return uint64(v) >> 32
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}
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func rshConst64Ux64Overflow16(v uint16) uint64 {
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// riscv64:"MOV\t\\$0,",-"SRL"
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return uint64(v) >> 16
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}
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func rshConst64Ux64Overflow8(v uint8) uint64 {
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// riscv64:"MOV\t\\$0,",-"SRL"
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return uint64(v) >> 8
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}
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func rshConst64x64(v int64) int64 {
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// ppc64x:"SRAD"
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// riscv64:"SRAI\t",-"OR",-"SLTIU"
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return v >> uint64(33)
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}
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func rshConst64x64Overflow32(v int32) int64 {
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// riscv64:"SRAIW",-"SLLI",-"SRAI\t"
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return int64(v) >> 32
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}
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func rshConst64x64Overflow16(v int16) int64 {
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// riscv64:"SLLI","SRAI",-"SRAIW"
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return int64(v) >> 16
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}
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func rshConst64x64Overflow8(v int8) int64 {
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// riscv64:"SLLI","SRAI",-"SRAIW"
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return int64(v) >> 8
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}
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func lshConst32x64(v int32) int32 {
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// ppc64x:"SLW"
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// riscv64:"SLLI",-"AND",-"SLTIU", -"MOVW"
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return v << uint64(29)
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}
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func rshConst32Ux64(v uint32) uint32 {
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// ppc64x:"SRW"
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// riscv64:"SRLIW",-"AND",-"SLTIU", -"MOVW"
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return v >> uint64(29)
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}
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func rshConst32x64(v int32) int32 {
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// ppc64x:"SRAW"
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// riscv64:"SRAIW",-"OR",-"SLTIU", -"MOVW"
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return v >> uint64(29)
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}
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func lshConst64x32(v int64) int64 {
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// ppc64x:"SLD"
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// riscv64:"SLLI",-"AND",-"SLTIU"
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return v << uint32(33)
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}
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func rshConst64Ux32(v uint64) uint64 {
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// ppc64x:"SRD"
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// riscv64:"SRLI\t",-"AND",-"SLTIU"
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return v >> uint32(33)
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}
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func rshConst64x32(v int64) int64 {
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// ppc64x:"SRAD"
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// riscv64:"SRAI\t",-"OR",-"SLTIU"
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return v >> uint32(33)
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}
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// ------------------ //
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// masked shifts //
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// ------------------ //
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func lshMask64x64(v int64, s uint64) int64 {
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// arm64:"LSL",-"AND"
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SLL",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v << (s & 63)
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}
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func rshMask64Ux64(v uint64, s uint64) uint64 {
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// arm64:"LSR",-"AND",-"CSEL"
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SRL\t",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func rshMask64x64(v int64, s uint64) int64 {
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// arm64:"ASR",-"AND",-"CSEL"
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SRA\t",-"OR",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func lshMask32x64(v int32, s uint64) int32 {
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// arm64:"LSL",-"AND"
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// ppc64x:"ISEL",-"ORN"
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// riscv64:"SLL",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v << (s & 63)
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}
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func rshMask32Ux64(v uint32, s uint64) uint32 {
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// arm64:"LSR",-"AND"
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// ppc64x:"ISEL",-"ORN"
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// riscv64:"SRLW","SLTIU","NEG","AND\t",-"SRL\t"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func rsh5Mask32Ux64(v uint32, s uint64) uint32 {
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// riscv64:"SRLW",-"AND\t",-"SLTIU",-"SRL\t"
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return v >> (s & 31)
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}
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func rshMask32x64(v int32, s uint64) int32 {
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// arm64:"ASR",-"AND"
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// ppc64x:"ISEL",-"ORN"
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// riscv64:"SRAW","OR","SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func rsh5Mask32x64(v int32, s uint64) int32 {
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// riscv64:"SRAW",-"OR",-"SLTIU"
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return v >> (s & 31)
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}
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func lshMask64x32(v int64, s uint32) int64 {
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// arm64:"LSL",-"AND"
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// ppc64x:"RLDICL",-"ORN"
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// riscv64:"SLL",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v << (s & 63)
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}
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func rshMask64Ux32(v uint64, s uint32) uint64 {
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// arm64:"LSR",-"AND",-"CSEL"
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// ppc64x:"RLDICL",-"ORN"
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// riscv64:"SRL\t",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func rshMask64x32(v int64, s uint32) int64 {
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// arm64:"ASR",-"AND",-"CSEL"
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SRA\t",-"OR",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> (s & 63)
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}
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func lshMask64x32Ext(v int64, s int32) int64 {
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SLL",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v << uint(s&63)
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}
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func rshMask64Ux32Ext(v uint64, s int32) uint64 {
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SRL\t",-"AND\t",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> uint(s&63)
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}
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func rshMask64x32Ext(v int64, s int32) int64 {
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// ppc64x:"RLDICL",-"ORN",-"ISEL"
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// riscv64:"SRA\t",-"OR",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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return v >> uint(s&63)
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}
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// --------------- //
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// signed shifts //
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// --------------- //
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// We do want to generate a test + panicshift for these cases.
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func lshSigned(v8 int8, v16 int16, v32 int32, v64 int64, x int) {
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// amd64:"TESTB"
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_ = x << v8
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// amd64:"TESTW"
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_ = x << v16
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// amd64:"TESTL"
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_ = x << v32
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// amd64:"TESTQ"
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_ = x << v64
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}
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// We want to avoid generating a test + panicshift for these cases.
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func lshSignedMasked(v8 int8, v16 int16, v32 int32, v64 int64, x int) {
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// amd64:-"TESTB"
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_ = x << (v8 & 7)
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// amd64:-"TESTW"
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_ = x << (v16 & 15)
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// amd64:-"TESTL"
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_ = x << (v32 & 31)
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// amd64:-"TESTQ"
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_ = x << (v64 & 63)
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}
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// ------------------ //
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// bounded shifts //
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// ------------------ //
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func lshGuarded64(v int64, s uint) int64 {
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if s < 64 {
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// riscv64:"SLL",-"AND",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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// wasm:-"Select",-".*LtU"
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// arm64:"LSL",-"CSEL"
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return v << s
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}
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panic("shift too large")
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}
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func rshGuarded64U(v uint64, s uint) uint64 {
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if s < 64 {
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// riscv64:"SRL\t",-"AND",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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// wasm:-"Select",-".*LtU"
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// arm64:"LSR",-"CSEL"
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return v >> s
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}
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panic("shift too large")
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}
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func rshGuarded64(v int64, s uint) int64 {
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if s < 64 {
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// riscv64:"SRA\t",-"OR",-"SLTIU"
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// s390x:-"RISBGZ",-"AND",-"LOCGR"
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// wasm:-"Select",-".*LtU"
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// arm64:"ASR",-"CSEL"
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return v >> s
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}
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panic("shift too large")
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}
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func provedUnsignedShiftLeft(val64 uint64, val32 uint32, val16 uint16, val8 uint8, shift int) (r1 uint64, r2 uint32, r3 uint16, r4 uint8) {
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if shift >= 0 && shift < 64 {
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// arm64:"LSL",-"CSEL"
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r1 = val64 << shift
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}
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if shift >= 0 && shift < 32 {
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// arm64:"LSL",-"CSEL"
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r2 = val32 << shift
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}
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if shift >= 0 && shift < 16 {
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// arm64:"LSL",-"CSEL"
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r3 = val16 << shift
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}
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if shift >= 0 && shift < 8 {
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// arm64:"LSL",-"CSEL"
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r4 = val8 << shift
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}
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return r1, r2, r3, r4
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}
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func provedSignedShiftLeft(val64 int64, val32 int32, val16 int16, val8 int8, shift int) (r1 int64, r2 int32, r3 int16, r4 int8) {
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if shift >= 0 && shift < 64 {
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// arm64:"LSL",-"CSEL"
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r1 = val64 << shift
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}
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if shift >= 0 && shift < 32 {
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// arm64:"LSL",-"CSEL"
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r2 = val32 << shift
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}
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if shift >= 0 && shift < 16 {
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// arm64:"LSL",-"CSEL"
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r3 = val16 << shift
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}
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if shift >= 0 && shift < 8 {
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// arm64:"LSL",-"CSEL"
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r4 = val8 << shift
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}
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return r1, r2, r3, r4
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}
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func provedUnsignedShiftRight(val64 uint64, val32 uint32, val16 uint16, val8 uint8, shift int) (r1 uint64, r2 uint32, r3 uint16, r4 uint8) {
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if shift >= 0 && shift < 64 {
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// arm64:"LSR",-"CSEL"
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r1 = val64 >> shift
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}
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if shift >= 0 && shift < 32 {
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// arm64:"LSR",-"CSEL"
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r2 = val32 >> shift
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}
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if shift >= 0 && shift < 16 {
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// arm64:"LSR",-"CSEL"
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r3 = val16 >> shift
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}
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if shift >= 0 && shift < 8 {
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// arm64:"LSR",-"CSEL"
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r4 = val8 >> shift
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}
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return r1, r2, r3, r4
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}
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func provedSignedShiftRight(val64 int64, val32 int32, val16 int16, val8 int8, shift int) (r1 int64, r2 int32, r3 int16, r4 int8) {
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if shift >= 0 && shift < 64 {
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// arm64:"ASR",-"CSEL"
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r1 = val64 >> shift
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}
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if shift >= 0 && shift < 32 {
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// arm64:"ASR",-"CSEL"
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r2 = val32 >> shift
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}
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if shift >= 0 && shift < 16 {
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// arm64:"ASR",-"CSEL"
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r3 = val16 >> shift
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}
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if shift >= 0 && shift < 8 {
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// arm64:"ASR",-"CSEL"
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r4 = val8 >> shift
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}
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return r1, r2, r3, r4
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}
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func checkUnneededTrunc(tab *[100000]uint32, d uint64, v uint32, h uint16, b byte) (uint32, uint64) {
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f := tab[byte(v)^b]
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f += tab[byte(v)&b]
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f += tab[byte(v)|b]
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f += tab[uint16(v)&h]
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f += tab[uint16(v)^h]
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// ppc64x:-".*RLWINM",-".*RLDICR",".*CLRLSLDI"
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f += tab[uint16(v)|h]
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// ppc64x:-".*AND",-"RLDICR",".*CLRLSLDI"
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f += tab[v&0xff]
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// ppc64x:-".*AND",".*CLRLSLWI"
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f += 2 * uint32(uint16(d))
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// ppc64x:-".*AND",-"RLDICR",".*CLRLSLDI"
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g := 2 * uint64(uint32(d))
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return f, g
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}
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func checkCombinedShifts(v8 uint8, v16 uint16, v32 uint32, x32 int32, v64 uint64) (uint8, uint16, uint32, uint64, int64) {
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// ppc64x:-"AND","CLRLSLWI"
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f := (v8 & 0xF) << 2
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// ppc64x:"CLRLSLWI"
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f += byte(v16) << 3
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// ppc64x:-"AND","CLRLSLWI"
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g := (v16 & 0xFF) << 3
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// ppc64x:-"AND","CLRLSLWI"
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h := (v32 & 0xFFFFF) << 2
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// ppc64x:"CLRLSLDI"
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i := (v64 & 0xFFFFFFFF) << 5
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// ppc64x:-"CLRLSLDI"
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i += (v64 & 0xFFFFFFF) << 38
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// ppc64x/power9:-"CLRLSLDI"
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i += (v64 & 0xFFFF00) << 10
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// ppc64x/power9:-"SLD","EXTSWSLI"
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j := int64(x32+32) * 8
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return f, g, h, i, j
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}
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func checkWidenAfterShift(v int64, u uint64) (int64, uint64) {
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// ppc64x:-".*MOVW"
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f := int32(v >> 32)
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// ppc64x:".*MOVW"
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f += int32(v >> 31)
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// ppc64x:-".*MOVH"
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g := int16(v >> 48)
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// ppc64x:".*MOVH"
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g += int16(v >> 30)
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// ppc64x:-".*MOVH"
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g += int16(f >> 16)
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// ppc64x:-".*MOVB"
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h := int8(v >> 56)
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// ppc64x:".*MOVB"
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h += int8(v >> 28)
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// ppc64x:-".*MOVB"
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h += int8(f >> 24)
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// ppc64x:".*MOVB"
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h += int8(f >> 16)
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return int64(h), uint64(g)
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}
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func checkShiftAndMask32(v []uint32) {
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i := 0
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// ppc64x: "RLWNM\t[$]24, R[0-9]+, [$]12, [$]19, R[0-9]+"
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v[i] = (v[i] & 0xFF00000) >> 8
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i++
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// ppc64x: "RLWNM\t[$]26, R[0-9]+, [$]22, [$]29, R[0-9]+"
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v[i] = (v[i] & 0xFF00) >> 6
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i++
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// ppc64x: "MOVW\tR0"
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v[i] = (v[i] & 0xFF) >> 8
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i++
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// ppc64x: "MOVW\tR0"
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v[i] = (v[i] & 0xF000000) >> 28
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i++
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// ppc64x: "RLWNM\t[$]26, R[0-9]+, [$]24, [$]31, R[0-9]+"
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v[i] = (v[i] >> 6) & 0xFF
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i++
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// ppc64x: "RLWNM\t[$]26, R[0-9]+, [$]12, [$]19, R[0-9]+"
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v[i] = (v[i] >> 6) & 0xFF000
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i++
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// ppc64x: "MOVW\tR0"
|
|
v[i] = (v[i] >> 20) & 0xFF000
|
|
i++
|
|
// ppc64x: "MOVW\tR0"
|
|
v[i] = (v[i] >> 24) & 0xFF00
|
|
i++
|
|
}
|
|
|
|
func checkMergedShifts32(a [256]uint32, b [256]uint64, u uint32, v uint32) {
|
|
// ppc64x: -"CLRLSLDI", "RLWNM\t[$]10, R[0-9]+, [$]22, [$]29, R[0-9]+"
|
|
a[0] = a[uint8(v>>24)]
|
|
// ppc64x: -"CLRLSLDI", "RLWNM\t[$]11, R[0-9]+, [$]21, [$]28, R[0-9]+"
|
|
b[0] = b[uint8(v>>24)]
|
|
// ppc64x: -"CLRLSLDI", "RLWNM\t[$]15, R[0-9]+, [$]21, [$]28, R[0-9]+"
|
|
b[1] = b[(v>>20)&0xFF]
|
|
// ppc64x: -"SLD", "RLWNM\t[$]10, R[0-9]+, [$]22, [$]28, R[0-9]+"
|
|
b[2] = b[v>>25]
|
|
}
|
|
|
|
// 128 bit shifts
|
|
|
|
func check128bitShifts(x, y uint64, bits uint) (uint64, uint64) {
|
|
s := bits & 63
|
|
ŝ := (64 - bits) & 63
|
|
// check that the shift operation has two commas (three operands)
|
|
// amd64:"SHRQ.*,.*,"
|
|
shr := x>>s | y<<ŝ
|
|
// amd64:"SHLQ.*,.*,"
|
|
shl := x<<s | y>>ŝ
|
|
return shr, shl
|
|
}
|
|
|
|
func checkShiftToMask(u []uint64, s []int64) {
|
|
// amd64:-"SHR",-"SHL","ANDQ"
|
|
u[0] = u[0] >> 5 << 5
|
|
// amd64:-"SAR",-"SHL","ANDQ"
|
|
s[0] = s[0] >> 5 << 5
|
|
// amd64:-"SHR",-"SHL","ANDQ"
|
|
u[1] = u[1] << 5 >> 5
|
|
}
|