751a817ccc
This CL adding primitive asm support of Loong64 LSX [1] and LASX [2], by introducing new
sets of register V0-V31 (C_VREG), X0-X31 (C_XREG) and 8 new instructions.
On Loong64, VLD,XVLD,VST,XVST implement vector memory access operations using immediate
values offset. VLDX, XVLDX, VSTX, XVSTX implement vector memory access operations using
register offset.
Go asm syntax:
VMOVQ n(RJ), RV (128bit vector load)
XVMOVQ n(RJ), RX (256bit vector load)
VMOVQ RV, n(RJ) (128bit vector store)
XVMOVQ RX, n(RJ) (256bit vector store)
VMOVQ (RJ)(RK), RV (128bit vector load)
XVMOVQ (RJ)(RK), RX (256bit vector load)
VMOVQ RV, (RJ)(RK) (128bit vector store)
XVMOVQ RX, (RJ)(RK) (256bit vector store)
Equivalent platform assembler syntax:
vld vd, rj, si12
xvld xd, rj, si12
vst vd, rj, si12
xvst xd, rj, si12
vldx vd, rj, rk
xvldx xd, rj, rk
vstx vd, rj, rk
xvstx xd, rj, rk
[1]: LSX: Loongson SIMD Extension, 128bit
[2]: LASX: Loongson Advanced SIMD Extension, 256bit
Change-Id: Ibaf5ddfd29b77670c3c44cc32bead36b2c8b8003
Reviewed-on: https://go-review.googlesource.com/c/go/+/616075
Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
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| src | ||
| test | ||
| .gitattributes | ||
| .gitignore | ||
| codereview.cfg | ||
| CONTRIBUTING.md | ||
| go.env | ||
| LICENSE | ||
| PATENTS | ||
| README.md | ||
| SECURITY.md | ||
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