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519474451a
This is a subset of https://golang.org/cl/20022 with only the copyright header lines, so the next CL will be smaller and more reviewable. Go policy has been single space after periods in comments for some time. The copyright header template at: https://golang.org/doc/contribute.html#copyright also uses a single space. Make them all consistent. Change-Id: Icc26c6b8495c3820da6b171ca96a74701b4a01b0 Reviewed-on: https://go-review.googlesource.com/20111 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> Reviewed-by: Ian Lance Taylor <iant@golang.org> Reviewed-by: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
218 lines
5.5 KiB
ArmAsm
218 lines
5.5 KiB
ArmAsm
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//
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// ARM version of md5block.go
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#include "textflag.h"
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// SHA1 block routine. See sha1block.go for Go equivalent.
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//
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// There are 80 rounds of 4 types:
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// - rounds 0-15 are type 1 and load data (ROUND1 macro).
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// - rounds 16-19 are type 1 and do not load data (ROUND1x macro).
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// - rounds 20-39 are type 2 and do not load data (ROUND2 macro).
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// - rounds 40-59 are type 3 and do not load data (ROUND3 macro).
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// - rounds 60-79 are type 4 and do not load data (ROUND4 macro).
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//
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// Each round loads or shuffles the data, then computes a per-round
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// function of b, c, d, and then mixes the result into and rotates the
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// five registers a, b, c, d, e holding the intermediate results.
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//
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// The register rotation is implemented by rotating the arguments to
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// the round macros instead of by explicit move instructions.
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// Register definitions
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#define Rdata R0 // Pointer to incoming data
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#define Rconst R1 // Current constant for SHA round
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#define Ra R2 // SHA1 accumulator
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#define Rb R3 // SHA1 accumulator
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#define Rc R4 // SHA1 accumulator
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#define Rd R5 // SHA1 accumulator
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#define Re R6 // SHA1 accumulator
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#define Rt0 R7 // Temporary
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#define Rt1 R8 // Temporary
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// r9, r10 are forbidden
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// r11 is OK provided you check the assembler that no synthetic instructions use it
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#define Rt2 R11 // Temporary
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#define Rctr R12 // loop counter
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#define Rw R14 // point to w buffer
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// func block(dig *digest, p []byte)
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// 0(FP) is *digest
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// 4(FP) is p.array (struct Slice)
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// 8(FP) is p.len
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//12(FP) is p.cap
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//
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// Stack frame
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#define p_end end-4(SP) // pointer to the end of data
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#define p_data data-8(SP) // current data pointer (unused?)
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#define w_buf buf-(8+4*80)(SP) //80 words temporary buffer w uint32[80]
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#define saved abcde-(8+4*80+4*5)(SP) // saved sha1 registers a,b,c,d,e - these must be last (unused?)
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// Total size +4 for saved LR is 352
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// w[i] = p[j]<<24 | p[j+1]<<16 | p[j+2]<<8 | p[j+3]
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// e += w[i]
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#define LOAD(Re) \
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MOVBU 2(Rdata), Rt0 ; \
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MOVBU 3(Rdata), Rt1 ; \
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MOVBU 1(Rdata), Rt2 ; \
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ORR Rt0<<8, Rt1, Rt0 ; \
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MOVBU.P 4(Rdata), Rt1 ; \
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ORR Rt2<<16, Rt0, Rt0 ; \
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ORR Rt1<<24, Rt0, Rt0 ; \
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MOVW.P Rt0, 4(Rw) ; \
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ADD Rt0, Re, Re
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// tmp := w[(i-3)&0xf] ^ w[(i-8)&0xf] ^ w[(i-14)&0xf] ^ w[(i)&0xf]
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// w[i&0xf] = tmp<<1 | tmp>>(32-1)
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// e += w[i&0xf]
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#define SHUFFLE(Re) \
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MOVW (-16*4)(Rw), Rt0 ; \
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MOVW (-14*4)(Rw), Rt1 ; \
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MOVW (-8*4)(Rw), Rt2 ; \
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EOR Rt0, Rt1, Rt0 ; \
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MOVW (-3*4)(Rw), Rt1 ; \
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EOR Rt2, Rt0, Rt0 ; \
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EOR Rt0, Rt1, Rt0 ; \
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MOVW Rt0@>(32-1), Rt0 ; \
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MOVW.P Rt0, 4(Rw) ; \
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ADD Rt0, Re, Re
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// t1 = (b & c) | ((~b) & d)
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#define FUNC1(Ra, Rb, Rc, Rd, Re) \
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MVN Rb, Rt1 ; \
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AND Rb, Rc, Rt0 ; \
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AND Rd, Rt1, Rt1 ; \
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ORR Rt0, Rt1, Rt1
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// t1 = b ^ c ^ d
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#define FUNC2(Ra, Rb, Rc, Rd, Re) \
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EOR Rb, Rc, Rt1 ; \
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EOR Rd, Rt1, Rt1
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// t1 = (b & c) | (b & d) | (c & d) =
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// t1 = (b & c) | ((b | c) & d)
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#define FUNC3(Ra, Rb, Rc, Rd, Re) \
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ORR Rb, Rc, Rt0 ; \
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AND Rb, Rc, Rt1 ; \
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AND Rd, Rt0, Rt0 ; \
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ORR Rt0, Rt1, Rt1
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#define FUNC4 FUNC2
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// a5 := a<<5 | a>>(32-5)
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// b = b<<30 | b>>(32-30)
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// e = a5 + t1 + e + const
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#define MIX(Ra, Rb, Rc, Rd, Re) \
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ADD Rt1, Re, Re ; \
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MOVW Rb@>(32-30), Rb ; \
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ADD Ra@>(32-5), Re, Re ; \
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ADD Rconst, Re, Re
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#define ROUND1(Ra, Rb, Rc, Rd, Re) \
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LOAD(Re) ; \
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FUNC1(Ra, Rb, Rc, Rd, Re) ; \
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MIX(Ra, Rb, Rc, Rd, Re)
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#define ROUND1x(Ra, Rb, Rc, Rd, Re) \
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SHUFFLE(Re) ; \
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FUNC1(Ra, Rb, Rc, Rd, Re) ; \
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MIX(Ra, Rb, Rc, Rd, Re)
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#define ROUND2(Ra, Rb, Rc, Rd, Re) \
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SHUFFLE(Re) ; \
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FUNC2(Ra, Rb, Rc, Rd, Re) ; \
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MIX(Ra, Rb, Rc, Rd, Re)
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#define ROUND3(Ra, Rb, Rc, Rd, Re) \
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SHUFFLE(Re) ; \
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FUNC3(Ra, Rb, Rc, Rd, Re) ; \
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MIX(Ra, Rb, Rc, Rd, Re)
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#define ROUND4(Ra, Rb, Rc, Rd, Re) \
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SHUFFLE(Re) ; \
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FUNC4(Ra, Rb, Rc, Rd, Re) ; \
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MIX(Ra, Rb, Rc, Rd, Re)
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// func block(dig *digest, p []byte)
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TEXT ·block(SB), 0, $352-16
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MOVW p+4(FP), Rdata // pointer to the data
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MOVW p_len+8(FP), Rt0 // number of bytes
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ADD Rdata, Rt0
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MOVW Rt0, p_end // pointer to end of data
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// Load up initial SHA1 accumulator
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MOVW dig+0(FP), Rt0
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MOVM.IA (Rt0), [Ra,Rb,Rc,Rd,Re]
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loop:
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// Save registers at SP+4 onwards
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MOVM.IB [Ra,Rb,Rc,Rd,Re], (R13)
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MOVW $w_buf, Rw
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MOVW $0x5A827999, Rconst
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MOVW $3, Rctr
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loop1: ROUND1(Ra, Rb, Rc, Rd, Re)
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ROUND1(Re, Ra, Rb, Rc, Rd)
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ROUND1(Rd, Re, Ra, Rb, Rc)
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ROUND1(Rc, Rd, Re, Ra, Rb)
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ROUND1(Rb, Rc, Rd, Re, Ra)
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SUB.S $1, Rctr
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BNE loop1
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ROUND1(Ra, Rb, Rc, Rd, Re)
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ROUND1x(Re, Ra, Rb, Rc, Rd)
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ROUND1x(Rd, Re, Ra, Rb, Rc)
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ROUND1x(Rc, Rd, Re, Ra, Rb)
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ROUND1x(Rb, Rc, Rd, Re, Ra)
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MOVW $0x6ED9EBA1, Rconst
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MOVW $4, Rctr
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loop2: ROUND2(Ra, Rb, Rc, Rd, Re)
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ROUND2(Re, Ra, Rb, Rc, Rd)
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ROUND2(Rd, Re, Ra, Rb, Rc)
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ROUND2(Rc, Rd, Re, Ra, Rb)
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ROUND2(Rb, Rc, Rd, Re, Ra)
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SUB.S $1, Rctr
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BNE loop2
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MOVW $0x8F1BBCDC, Rconst
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MOVW $4, Rctr
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loop3: ROUND3(Ra, Rb, Rc, Rd, Re)
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ROUND3(Re, Ra, Rb, Rc, Rd)
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ROUND3(Rd, Re, Ra, Rb, Rc)
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ROUND3(Rc, Rd, Re, Ra, Rb)
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ROUND3(Rb, Rc, Rd, Re, Ra)
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SUB.S $1, Rctr
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BNE loop3
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MOVW $0xCA62C1D6, Rconst
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MOVW $4, Rctr
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loop4: ROUND4(Ra, Rb, Rc, Rd, Re)
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ROUND4(Re, Ra, Rb, Rc, Rd)
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ROUND4(Rd, Re, Ra, Rb, Rc)
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ROUND4(Rc, Rd, Re, Ra, Rb)
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ROUND4(Rb, Rc, Rd, Re, Ra)
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SUB.S $1, Rctr
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BNE loop4
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// Accumulate - restoring registers from SP+4
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MOVM.IB (R13), [Rt0,Rt1,Rt2,Rctr,Rw]
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ADD Rt0, Ra
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ADD Rt1, Rb
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ADD Rt2, Rc
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ADD Rctr, Rd
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ADD Rw, Re
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MOVW p_end, Rt0
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CMP Rt0, Rdata
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BLO loop
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// Save final SHA1 accumulator
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MOVW dig+0(FP), Rt0
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MOVM.IA [Ra,Rb,Rc,Rd,Re], (Rt0)
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RET
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