41e8679611
According to the ARM Architecture Reference Manual, LDADDx-like instructions can take rt as zr when the encode A bit is 0. They are used by the alias STADDx-like instructions. The current assembler adds incorrect constraints for them, which is rt can't be zr when field.enc A is 0. This patch removes it. Add test cases. Reported by Matt Horsnell <matt.horsnell@arm.com> The reference: https://developer.arm.com/documentation/ddi0602/2022-12/Base-Instructions Change-Id: Ia2487a5e3900e32994fc14edaf03deeb245e70c6 Reviewed-on: https://go-review.googlesource.com/c/go/+/462295 Reviewed-by: Matt Horsnell <matthew.horsnell@gmail.com> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> |
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SECURITY.md |
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