mirror of
https://github.com/golang/go
synced 2024-11-19 20:54:39 -07:00
3e3fa7b5f1
benchmark old ns/op new ns/op delta BenchmarkUint32Div7 281 75 -73.06% BenchmarkUint32Div37 281 75 -73.02% BenchmarkUint32Div123 281 75 -73.02% BenchmarkUint32Div763 280 75 -72.89% BenchmarkUint32Div1247 280 75 -72.93% BenchmarkUint32Div9305 281 75 -73.02% BenchmarkUint32Div13307 281 75 -73.06% BenchmarkUint32Div52513 281 75 -72.99% BenchmarkUint32Div60978747 281 63 -77.33% BenchmarkUint32Div106956295 280 63 -77.21% BenchmarkUint32Mod7 280 77 -72.21% BenchmarkUint32Mod37 280 77 -72.18% BenchmarkUint32Mod123 280 77 -72.25% BenchmarkUint32Mod763 280 77 -72.18% BenchmarkUint32Mod1247 280 77 -72.21% BenchmarkUint32Mod9305 280 77 -72.21% BenchmarkUint32Mod13307 280 77 -72.25% BenchmarkUint32Mod52513 280 77 -72.18% BenchmarkUint32Mod60978747 280 63 -77.25% BenchmarkUint32Mod106956295 280 63 -77.21% R=dave, rsc CC=dave, golang-dev, rsc https://golang.org/cl/6717043
251 lines
6.7 KiB
ArmAsm
251 lines
6.7 KiB
ArmAsm
// Inferno's libkern/vlop-arm.s
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// http://code.google.com/p/inferno-os/source/browse/libkern/vlop-arm.s
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Revisions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com). All rights reserved.
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// Portions Copyright 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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arg=0
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/* replaced use of R10 by R11 because the former can be the data segment base register */
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TEXT _mulv(SB), $0
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MOVW 0(FP), R0
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MOVW 4(FP), R2 /* l0 */
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MOVW 8(FP), R11 /* h0 */
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MOVW 12(FP), R4 /* l1 */
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MOVW 16(FP), R5 /* h1 */
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MULLU R4, R2, (R7,R6)
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MUL R11, R4, R8
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ADD R8, R7
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MUL R2, R5, R8
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ADD R8, R7
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MOVW R6, 0(R(arg))
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MOVW R7, 4(R(arg))
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RET
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// trampoline for _sfloat2. passes LR as arg0 and
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// saves registers R0-R13 and CPSR on the stack. R0-R12 and CPSR flags can
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// be changed by _sfloat2.
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TEXT _sfloat(SB), 7, $64 // 4 arg + 14*4 saved regs + cpsr
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MOVW R14, 4(R13)
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MOVW R0, 8(R13)
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MOVW $12(R13), R0
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MOVM.IA.W [R1-R12], (R0)
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MOVW $68(R13), R1 // correct for frame size
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MOVW R1, 60(R13)
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WORD $0xe10f1000 // mrs r1, cpsr
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MOVW R1, 64(R13)
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BL runtime·_sfloat2(SB)
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MOVW R0, 0(R13)
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MOVW 64(R13), R1
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WORD $0xe128f001 // msr cpsr_f, r1
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MOVW $12(R13), R0
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MOVM.IA.W (R0), [R1-R12]
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MOVW 8(R13), R0
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RET
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// func udiv(n, d uint32) (q, r uint32)
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// Reference:
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// Sloss, Andrew et. al; ARM System Developer's Guide: Designing and Optimizing System Software
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// Morgan Kaufmann; 1 edition (April 8, 2004), ISBN 978-1558608740
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q = 0 // input d, output q
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r = 1 // input n, output r
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s = 2 // three temporary variables
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m = 3
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a = 11
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// Please be careful when changing this, it is pretty fragile:
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// 1, don't use unconditional branch as the linker is free to reorder the blocks;
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// 2. if a == 11, beware that the linker will use R11 if you use certain instructions.
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TEXT udiv<>(SB),7,$-4
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CLZ R(q), R(s) // find normalizing shift
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MOVW.S R(q)<<R(s), R(a)
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ADD R(a)>>25, PC, R(a) // most significant 7 bits of divisor
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MOVBU.NE (4*36-64)(R(a)), R(a) // 36 == number of inst. between fast_udiv_tab and begin
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begin:
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SUB.S $7, R(s)
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RSB $0, R(q), R(m) // m = -q
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MOVW.PL R(a)<<R(s), R(q)
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// 1st Newton iteration
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MUL.PL R(m), R(q), R(a) // a = -q*d
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BMI udiv_by_large_d
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MULAWT R(a), R(q), R(q), R(q) // q approx q-(q*q*d>>32)
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TEQ R(m)->1, R(m) // check for d=0 or d=1
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// 2nd Newton iteration
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MUL.NE R(m), R(q), R(a)
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MOVW.NE $0, R(s)
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MULAL.NE R(q), R(a), (R(q),R(s))
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BEQ udiv_by_0_or_1
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// q now accurate enough for a remainder r, 0<=r<3*d
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MULLU R(q), R(r), (R(q),R(s)) // q = (r * q) >> 32
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ADD R(m), R(r), R(r) // r = n - d
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MULA R(m), R(q), R(r), R(r) // r = n - (q+1)*d
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// since 0 <= n-q*d < 3*d; thus -d <= r < 2*d
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CMN R(m), R(r) // t = r-d
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SUB.CS R(m), R(r), R(r) // if (t<-d || t>=0) r=r+d
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ADD.CC $1, R(q)
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ADD.PL R(m)<<1, R(r)
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ADD.PL $2, R(q)
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// return, can't use RET here or fast_udiv_tab will be dropped during linking
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MOVW R14, R15
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udiv_by_large_d:
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// at this point we know d>=2^(31-6)=2^25
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SUB $4, R(a), R(a)
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RSB $0, R(s), R(s)
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MOVW R(a)>>R(s), R(q)
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MULLU R(q), R(r), (R(q),R(s))
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MULA R(m), R(q), R(r), R(r)
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// q now accurate enough for a remainder r, 0<=r<4*d
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CMN R(r)>>1, R(m) // if(r/2 >= d)
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ADD.CS R(m)<<1, R(r)
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ADD.CS $2, R(q)
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CMN R(r), R(m)
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ADD.CS R(m), R(r)
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ADD.CS $1, R(q)
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// return, can't use RET here or fast_udiv_tab will be dropped during linking
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MOVW R14, R15
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udiv_by_0_or_1:
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// carry set if d==1, carry clear if d==0
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MOVW.CS R(r), R(q)
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MOVW.CS $0, R(r)
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BL.CC runtime·panicdivide(SB) // no way back
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// return, can't use RET here or fast_udiv_tab will be dropped during linking
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MOVW R14, R15
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fast_udiv_tab:
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// var tab [64]byte
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// tab[0] = 255; for i := 1; i <= 63; i++ { tab[i] = (1<<14)/(64+i) }
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// laid out here as little-endian uint32s
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WORD $0xf4f8fcff
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WORD $0xe6eaedf0
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WORD $0xdadde0e3
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WORD $0xcfd2d4d7
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WORD $0xc5c7cacc
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WORD $0xbcbec0c3
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WORD $0xb4b6b8ba
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WORD $0xacaeb0b2
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WORD $0xa5a7a8aa
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WORD $0x9fa0a2a3
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WORD $0x999a9c9d
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WORD $0x93949697
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WORD $0x8e8f9092
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WORD $0x898a8c8d
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WORD $0x85868788
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WORD $0x81828384
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// The linker will pass numerator in R(TMP), and it also
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// expects the result in R(TMP)
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TMP = 11
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TEXT _divu(SB), 7, $16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(m), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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BL udiv<>(SB)
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MOVW R(q), R(TMP)
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(m)
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RET
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TEXT _modu(SB), 7, $16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(m), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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BL udiv<>(SB)
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MOVW R(r), R(TMP)
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(m)
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RET
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TEXT _div(SB),7,$16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(m), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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CMP $0, R(r)
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BGE d1
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RSB $0, R(r), R(r)
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CMP $0, R(q)
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BGE d2
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RSB $0, R(q), R(q)
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d0:
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BL udiv<>(SB) /* none/both neg */
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MOVW R(q), R(TMP)
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B out
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d1:
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CMP $0, R(q)
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BGE d0
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RSB $0, R(q), R(q)
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d2:
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BL udiv<>(SB) /* one neg */
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RSB $0, R(q), R(TMP)
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B out
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TEXT _mod(SB),7,$16
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MOVW R(q), 4(R13)
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MOVW R(r), 8(R13)
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MOVW R(s), 12(R13)
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MOVW R(m), 16(R13)
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MOVW R(TMP), R(r) /* numerator */
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MOVW 0(FP), R(q) /* denominator */
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CMP $0, R(q)
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RSB.LT $0, R(q), R(q)
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CMP $0, R(r)
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BGE m1
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RSB $0, R(r), R(r)
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BL udiv<>(SB) /* neg numerator */
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RSB $0, R(r), R(TMP)
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B out
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m1:
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BL udiv<>(SB) /* pos numerator */
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MOVW R(r), R(TMP)
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out:
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MOVW 4(R13), R(q)
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MOVW 8(R13), R(r)
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MOVW 12(R13), R(s)
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MOVW 16(R13), R(m)
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RET
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