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69ddb7a408
Several .s files for ARM had several properties the new assembler will not support. These include: - mentioning SP or PC as a hardware register These are always pseudo-registers except that in some contexts they're not, and it's confusing because the context should not affect which register you mean. Change the references to the hardware registers to be explicit: R13 for SP, R15 for PC. - constant creation using assignment The files say a=b when they could instead say #define a b. There is no reason to have both mechanisms. - R(0) to refer to R0. Some macros use this to a great extent. Again, it's easy just to use a #define to rename a register. Change-Id: I002335ace8e876c5b63c71c2560533eb835346d2 Reviewed-on: https://go-review.googlesource.com/4822 Reviewed-by: Dave Cheney <dave@cheney.net>
262 lines
5.8 KiB
ArmAsm
262 lines
5.8 KiB
ArmAsm
// Inferno's libkern/memmove-arm.s
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// http://code.google.com/p/inferno-os/source/browse/libkern/memmove-arm.s
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Revisions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com). All rights reserved.
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// Portions Copyright 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#include "textflag.h"
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// TE or TS are spilled to the stack during bulk register moves.
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#define TS R0
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#define TE R8
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// Warning: the linker will use R11 to synthesize certain instructions. Please
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// take care and double check with objdump.
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#define FROM R11
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#define N R12
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#define TMP R12 /* N and TMP don't overlap */
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#define TMP1 R5
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#define RSHIFT R5
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#define LSHIFT R6
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#define OFFSET R7
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#define BR0 R0 /* shared with TS */
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#define BW0 R1
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#define BR1 R1
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#define BW1 R2
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#define BR2 R2
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#define BW2 R3
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#define BR3 R3
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#define BW3 R4
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#define FW0 R1
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#define FR0 R2
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#define FW1 R2
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#define FR1 R3
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#define FW2 R3
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#define FR2 R4
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#define FW3 R4
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#define FR3 R8 /* shared with TE */
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TEXT runtime·memmove(SB), NOSPLIT, $4-12
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_memmove:
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MOVW to+0(FP), TS
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MOVW from+4(FP), FROM
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MOVW n+8(FP), N
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ADD N, TS, TE /* to end pointer */
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CMP FROM, TS
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BLS _forward
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_back:
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ADD N, FROM /* from end pointer */
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CMP $4, N /* need at least 4 bytes to copy */
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BLT _b1tail
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_b4align: /* align destination on 4 */
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AND.S $3, TE, TMP
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BEQ _b4aligned
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MOVBU.W -1(FROM), TMP /* pre-indexed */
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MOVBU.W TMP, -1(TE) /* pre-indexed */
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B _b4align
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_b4aligned: /* is source now aligned? */
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AND.S $3, FROM, TMP
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BNE _bunaligned
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ADD $31, TS, TMP /* do 32-byte chunks if possible */
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MOVW TS, savedts-4(SP)
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_b32loop:
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CMP TMP, TE
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BLS _b4tail
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MOVM.DB.W (FROM), [R0-R7]
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MOVM.DB.W [R0-R7], (TE)
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B _b32loop
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_b4tail: /* do remaining words if possible */
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MOVW savedts-4(SP), TS
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ADD $3, TS, TMP
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_b4loop:
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CMP TMP, TE
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BLS _b1tail
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MOVW.W -4(FROM), TMP1 /* pre-indexed */
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MOVW.W TMP1, -4(TE) /* pre-indexed */
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B _b4loop
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_b1tail: /* remaining bytes */
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CMP TE, TS
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BEQ _return
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MOVBU.W -1(FROM), TMP /* pre-indexed */
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MOVBU.W TMP, -1(TE) /* pre-indexed */
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B _b1tail
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_forward:
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CMP $4, N /* need at least 4 bytes to copy */
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BLT _f1tail
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_f4align: /* align destination on 4 */
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AND.S $3, TS, TMP
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BEQ _f4aligned
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MOVBU.P 1(FROM), TMP /* implicit write back */
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MOVBU.P TMP, 1(TS) /* implicit write back */
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B _f4align
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_f4aligned: /* is source now aligned? */
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AND.S $3, FROM, TMP
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BNE _funaligned
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SUB $31, TE, TMP /* do 32-byte chunks if possible */
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MOVW TE, savedte-4(SP)
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_f32loop:
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CMP TMP, TS
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BHS _f4tail
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MOVM.IA.W (FROM), [R1-R8]
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MOVM.IA.W [R1-R8], (TS)
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B _f32loop
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_f4tail:
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MOVW savedte-4(SP), TE
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SUB $3, TE, TMP /* do remaining words if possible */
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_f4loop:
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CMP TMP, TS
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BHS _f1tail
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MOVW.P 4(FROM), TMP1 /* implicit write back */
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MOVW.P TMP1, 4(TS) /* implicit write back */
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B _f4loop
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_f1tail:
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CMP TS, TE
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BEQ _return
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MOVBU.P 1(FROM), TMP /* implicit write back */
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MOVBU.P TMP, 1(TS) /* implicit write back */
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B _f1tail
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_return:
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MOVW to+0(FP), R0
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RET
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_bunaligned:
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CMP $2, TMP /* is TMP < 2 ? */
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MOVW.LT $8, RSHIFT /* (R(n)<<24)|(R(n-1)>>8) */
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MOVW.LT $24, LSHIFT
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MOVW.LT $1, OFFSET
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MOVW.EQ $16, RSHIFT /* (R(n)<<16)|(R(n-1)>>16) */
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MOVW.EQ $16, LSHIFT
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MOVW.EQ $2, OFFSET
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MOVW.GT $24, RSHIFT /* (R(n)<<8)|(R(n-1)>>24) */
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MOVW.GT $8, LSHIFT
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MOVW.GT $3, OFFSET
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ADD $16, TS, TMP /* do 16-byte chunks if possible */
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CMP TMP, TE
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BLS _b1tail
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BIC $3, FROM /* align source */
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MOVW TS, savedts-4(SP)
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MOVW (FROM), BR0 /* prime first block register */
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_bu16loop:
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CMP TMP, TE
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BLS _bu1tail
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MOVW BR0<<LSHIFT, BW3
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MOVM.DB.W (FROM), [BR0-BR3]
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ORR BR3>>RSHIFT, BW3
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MOVW BR3<<LSHIFT, BW2
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ORR BR2>>RSHIFT, BW2
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MOVW BR2<<LSHIFT, BW1
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ORR BR1>>RSHIFT, BW1
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MOVW BR1<<LSHIFT, BW0
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ORR BR0>>RSHIFT, BW0
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MOVM.DB.W [BW0-BW3], (TE)
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B _bu16loop
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_bu1tail:
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MOVW savedts-4(SP), TS
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ADD OFFSET, FROM
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B _b1tail
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_funaligned:
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CMP $2, TMP
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MOVW.LT $8, RSHIFT /* (R(n+1)<<24)|(R(n)>>8) */
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MOVW.LT $24, LSHIFT
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MOVW.LT $3, OFFSET
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MOVW.EQ $16, RSHIFT /* (R(n+1)<<16)|(R(n)>>16) */
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MOVW.EQ $16, LSHIFT
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MOVW.EQ $2, OFFSET
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MOVW.GT $24, RSHIFT /* (R(n+1)<<8)|(R(n)>>24) */
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MOVW.GT $8, LSHIFT
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MOVW.GT $1, OFFSET
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SUB $16, TE, TMP /* do 16-byte chunks if possible */
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CMP TMP, TS
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BHS _f1tail
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BIC $3, FROM /* align source */
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MOVW TE, savedte-4(SP)
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MOVW.P 4(FROM), FR3 /* prime last block register, implicit write back */
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_fu16loop:
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CMP TMP, TS
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BHS _fu1tail
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MOVW FR3>>RSHIFT, FW0
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MOVM.IA.W (FROM), [FR0,FR1,FR2,FR3]
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ORR FR0<<LSHIFT, FW0
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MOVW FR0>>RSHIFT, FW1
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ORR FR1<<LSHIFT, FW1
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MOVW FR1>>RSHIFT, FW2
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ORR FR2<<LSHIFT, FW2
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MOVW FR2>>RSHIFT, FW3
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ORR FR3<<LSHIFT, FW3
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MOVM.IA.W [FW0,FW1,FW2,FW3], (TS)
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B _fu16loop
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_fu1tail:
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MOVW savedte-4(SP), TE
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SUB OFFSET, FROM
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B _f1tail
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