Revision 63f7abcae015 introduced a bug caused by
code assuming registers started at X5, not X0.
Fixes#4138.
R=rsc
CC=golang-dev, remy
https://golang.org/cl/6558043
Broke tests on 386.
««« original CL description
6l/8l: emit correct opcodes to F(SUB|DIV)R?D.
When the destination was not F0, 6l and 8l swapped FSUBD/FSUBRD and
FDIVD/FDIVRD.
R=golang-dev, dave, rsc
CC=golang-dev
https://golang.org/cl/6498092
»»»
R=golang-dev
CC=golang-dev
https://golang.org/cl/6492100