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cmd/compile: arm64 intrinsics for math/bits.OnesCount
This adds math/bits intrinsics for OnesCount on arm64. name old time/op new time/op delta OnesCount 3.81ns ± 0% 1.60ns ± 0% -57.96% (p=0.000 n=7+8) OnesCount8 1.60ns ± 0% 1.60ns ± 0% ~ (all equal) OnesCount16 2.41ns ± 0% 1.60ns ± 0% -33.61% (p=0.000 n=8+8) OnesCount32 4.17ns ± 0% 1.60ns ± 0% -61.58% (p=0.000 n=8+8) OnesCount64 3.80ns ± 0% 1.60ns ± 0% -57.84% (p=0.000 n=8+8) Update #18616 Conflicts: src/cmd/compile/internal/gc/asm_test.go Change-Id: I63ac2f63acafdb1f60656ab8a56be0b326eec5cb Reviewed-on: https://go-review.googlesource.com/90835 Run-TryBot: Cherry Zhang <cherryyz@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Balaram Makam
Cherry Zhang
parent
c26fac88d4
commit
fcba05148f
1
src/cmd/asm/internal/asm/testdata/arm64enc.s
vendored
1
src/cmd/asm/internal/asm/testdata/arm64enc.s
vendored
@ -388,6 +388,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
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UMULL R18, R22, R19 // d37eb29b
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UXTBW R2, R6 // 461c0053
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UXTHW R7, R20 // f43c0053
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VCNT V0.B8, V0.B8 // 0058200e
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WFE // 5f2003d5
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WFI // 7f2003d5
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YIELD // 3f2003d5
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@ -530,6 +530,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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fallthrough
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case ssa.OpARM64MVN,
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ssa.OpARM64NEG,
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ssa.OpARM64FMOVDfpgp,
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ssa.OpARM64FMOVDgpfp,
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ssa.OpARM64FNEGS,
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ssa.OpARM64FNEGD,
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ssa.OpARM64FSQRTD,
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@ -563,6 +565,18 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpARM64VCNT:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = (v.Args[0].Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = (v.Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5)
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case ssa.OpARM64VUADDLV:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = (v.Args[0].Reg()-arm64.REG_F0)&31 + arm64.REG_ARNG + ((arm64.ARNG_8B & 15) << 5)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg() - arm64.REG_F0 + arm64.REG_V0
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case ssa.OpARM64CSELULT,
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ssa.OpARM64CSELULT0:
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r1 := int16(arm64.REGZERO)
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@ -2751,6 +2751,30 @@ var linuxARM64Tests = []*asmTest{
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`,
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pos: []string{"TBZ"},
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},
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{
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fn: `
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func $(x uint64) int {
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return bits.OnesCount64(x)
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}
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`,
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pos: []string{"\tVCNT\t", "\tVUADDLV\t"},
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},
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{
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fn: `
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func $(x uint32) int {
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return bits.OnesCount32(x)
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}
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`,
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pos: []string{"\tVCNT\t", "\tVUADDLV\t"},
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},
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{
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fn: `
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func $(x uint16) int {
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return bits.OnesCount16(x)
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}
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`,
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pos: []string{"\tVCNT\t", "\tVUADDLV\t"},
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},
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// Load-combining tests.
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{
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fn: `
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@ -3156,7 +3156,7 @@ func init() {
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func(s *state, n *Node, args []*ssa.Value) *ssa.Value {
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return s.newValue1(ssa.OpPopCount64, types.Types[TINT], args[0])
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},
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sys.PPC64)
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sys.PPC64, sys.ARM64)
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addF("math/bits", "OnesCount32",
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makeOnesCountAMD64(ssa.OpPopCount32, ssa.OpPopCount32),
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sys.AMD64)
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@ -3164,10 +3164,15 @@ func init() {
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func(s *state, n *Node, args []*ssa.Value) *ssa.Value {
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return s.newValue1(ssa.OpPopCount32, types.Types[TINT], args[0])
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},
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sys.PPC64)
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sys.PPC64, sys.ARM64)
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addF("math/bits", "OnesCount16",
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makeOnesCountAMD64(ssa.OpPopCount16, ssa.OpPopCount16),
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sys.AMD64)
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addF("math/bits", "OnesCount16",
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func(s *state, n *Node, args []*ssa.Value) *ssa.Value {
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return s.newValue1(ssa.OpPopCount16, types.Types[TINT], args[0])
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},
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sys.ARM64)
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// Note: no OnesCount8, the Go implementation is faster - just a table load.
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addF("math/bits", "OnesCount",
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makeOnesCountAMD64(ssa.OpPopCount64, ssa.OpPopCount32),
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@ -86,6 +86,16 @@
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(Ctz64 <t> x) -> (CLZ (RBIT <t> x))
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(Ctz32 <t> x) -> (CLZW (RBITW <t> x))
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(PopCount64 <t> x) -> (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> x))))
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(PopCount32 <t> x) -> (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt32to64 x)))))
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(PopCount16 <t> x) -> (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt16to64 x)))))
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// Load args directly into the register class where it will be used.
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(FMOVDgpfp <t> (Arg [off] {sym})) -> @b.Func.Entry (Arg <t> [off] {sym})
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// Similarly for stores, if we see a store after FPR <-> GPR move, then redirect store to use the other register set.
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(MOVDstore ptr (FMOVDfpgp val) mem) -> (FMOVDstore ptr val mem)
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(FMOVDstore ptr (FMOVDgpfp val) mem) -> (MOVDstore ptr val mem)
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(BitLen64 x) -> (SUB (MOVDconst [64]) (CLZ <typ.Int> x))
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(Bswap64 x) -> (REV x)
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@ -211,6 +211,8 @@ func init() {
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{name: "RBITW", argLength: 1, reg: gp11, asm: "RBITW"}, // bit reverse, 32-bit
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{name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, // count leading zero, 64-bit
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{name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"}, // count leading zero, 32-bit
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{name: "VCNT", argLength: 1, reg: fp11, asm: "VCNT"}, // count set bits for each 8-bit unit and store the result in each 8-bit unit
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{name: "VUADDLV", argLength: 1, reg: fp11, asm: "VUADDLV"}, // unsigned sum of eight bytes in a 64-bit value, zero extended to 64-bit.
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// shifts
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{name: "SLL", argLength: 2, reg: gp21, asm: "LSL"}, // arg0 << arg1, shift amount is mod 64
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@ -288,6 +290,9 @@ func init() {
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{name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of zero to arg0 + auxInt + aux. arg1=mem.
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{name: "MOVQstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "STP", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 16 bytes of zero to arg0 + auxInt + aux. arg1=mem.
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{name: "FMOVDgpfp", argLength: 1, reg: gpfp, asm: "FMOVD"}, // move int64 to float64 (no conversion)
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{name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion)
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// conversions
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{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte
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{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
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@ -999,6 +999,8 @@ const (
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OpARM64RBITW
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OpARM64CLZ
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OpARM64CLZW
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OpARM64VCNT
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OpARM64VUADDLV
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OpARM64SLL
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OpARM64SLLconst
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OpARM64SRL
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@ -1063,6 +1065,8 @@ const (
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OpARM64MOVWstorezero
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OpARM64MOVDstorezero
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OpARM64MOVQstorezero
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OpARM64FMOVDgpfp
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OpARM64FMOVDfpgp
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OpARM64MOVBreg
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OpARM64MOVBUreg
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OpARM64MOVHreg
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@ -12689,6 +12693,32 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "VCNT",
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argLen: 1,
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asm: arm64.AVCNT,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "VUADDLV",
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argLen: 1,
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asm: arm64.AVUADDLV,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "SLL",
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argLen: 2,
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@ -13577,6 +13607,32 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "FMOVDgpfp",
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argLen: 1,
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asm: arm64.AFMOVD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
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},
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outputs: []outputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "FMOVDfpgp",
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argLen: 1,
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asm: arm64.AFMOVD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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outputs: []outputInfo{
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{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
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},
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},
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},
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{
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name: "MOVBreg",
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argLen: 1,
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@ -69,6 +69,8 @@ func rewriteValueARM64(v *Value) bool {
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return rewriteValueARM64_OpARM64DIVW_0(v)
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case OpARM64Equal:
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return rewriteValueARM64_OpARM64Equal_0(v)
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case OpARM64FMOVDgpfp:
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return rewriteValueARM64_OpARM64FMOVDgpfp_0(v)
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case OpARM64FMOVDload:
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return rewriteValueARM64_OpARM64FMOVDload_0(v)
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case OpARM64FMOVDstore:
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@ -599,6 +601,12 @@ func rewriteValueARM64(v *Value) bool {
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return rewriteValueARM64_OpOr8_0(v)
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case OpOrB:
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return rewriteValueARM64_OpOrB_0(v)
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case OpPopCount16:
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return rewriteValueARM64_OpPopCount16_0(v)
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case OpPopCount32:
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return rewriteValueARM64_OpPopCount32_0(v)
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case OpPopCount64:
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return rewriteValueARM64_OpPopCount64_0(v)
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case OpRound32F:
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return rewriteValueARM64_OpRound32F_0(v)
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case OpRound64F:
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@ -2871,6 +2879,30 @@ func rewriteValueARM64_OpARM64Equal_0(v *Value) bool {
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}
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return false
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}
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func rewriteValueARM64_OpARM64FMOVDgpfp_0(v *Value) bool {
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b := v.Block
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_ = b
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// match: (FMOVDgpfp <t> (Arg [off] {sym}))
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// cond:
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// result: @b.Func.Entry (Arg <t> [off] {sym})
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for {
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t := v.Type
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v_0 := v.Args[0]
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if v_0.Op != OpArg {
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break
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}
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off := v_0.AuxInt
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sym := v_0.Aux
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b = b.Func.Entry
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v0 := b.NewValue0(v.Pos, OpArg, t)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = off
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v0.Aux = sym
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return true
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}
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return false
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}
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func rewriteValueARM64_OpARM64FMOVDload_0(v *Value) bool {
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b := v.Block
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_ = b
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@ -2932,6 +2964,24 @@ func rewriteValueARM64_OpARM64FMOVDstore_0(v *Value) bool {
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_ = b
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config := b.Func.Config
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_ = config
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// match: (FMOVDstore ptr (FMOVDgpfp val) mem)
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// cond:
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// result: (MOVDstore ptr val mem)
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for {
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_ = v.Args[2]
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpARM64FMOVDgpfp {
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break
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}
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val := v_1.Args[0]
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mem := v.Args[2]
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v.reset(OpARM64MOVDstore)
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v.AddArg(ptr)
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v.AddArg(val)
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v.AddArg(mem)
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return true
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}
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// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
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// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
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// result: (FMOVDstore [off1+off2] {sym} ptr val mem)
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@ -4600,6 +4650,24 @@ func rewriteValueARM64_OpARM64MOVDstore_0(v *Value) bool {
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_ = b
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config := b.Func.Config
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_ = config
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// match: (MOVDstore ptr (FMOVDfpgp val) mem)
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// cond:
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// result: (FMOVDstore ptr val mem)
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for {
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_ = v.Args[2]
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpARM64FMOVDfpgp {
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break
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}
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val := v_1.Args[0]
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mem := v.Args[2]
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v.reset(OpARM64FMOVDstore)
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v.AddArg(ptr)
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v.AddArg(val)
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v.AddArg(mem)
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return true
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}
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// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
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// cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)
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// result: (MOVDstore [off1+off2] {sym} ptr val mem)
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@ -14576,6 +14644,79 @@ func rewriteValueARM64_OpOrB_0(v *Value) bool {
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return true
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}
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}
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func rewriteValueARM64_OpPopCount16_0(v *Value) bool {
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b := v.Block
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_ = b
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typ := &b.Func.Config.Types
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_ = typ
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// match: (PopCount16 <t> x)
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// cond:
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// result: (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt16to64 x)))))
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for {
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t := v.Type
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x := v.Args[0]
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v.reset(OpARM64FMOVDfpgp)
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v.Type = t
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v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64)
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v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64)
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v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64)
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v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
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v3.AddArg(x)
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v2.AddArg(v3)
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v1.AddArg(v2)
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v0.AddArg(v1)
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v.AddArg(v0)
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return true
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}
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}
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func rewriteValueARM64_OpPopCount32_0(v *Value) bool {
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b := v.Block
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_ = b
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typ := &b.Func.Config.Types
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_ = typ
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// match: (PopCount32 <t> x)
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// cond:
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||||
// result: (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt32to64 x)))))
|
||||
for {
|
||||
t := v.Type
|
||||
x := v.Args[0]
|
||||
v.reset(OpARM64FMOVDfpgp)
|
||||
v.Type = t
|
||||
v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64)
|
||||
v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64)
|
||||
v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64)
|
||||
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
|
||||
v3.AddArg(x)
|
||||
v2.AddArg(v3)
|
||||
v1.AddArg(v2)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpPopCount64_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
typ := &b.Func.Config.Types
|
||||
_ = typ
|
||||
// match: (PopCount64 <t> x)
|
||||
// cond:
|
||||
// result: (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> x))))
|
||||
for {
|
||||
t := v.Type
|
||||
x := v.Args[0]
|
||||
v.reset(OpARM64FMOVDfpgp)
|
||||
v.Type = t
|
||||
v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64)
|
||||
v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64)
|
||||
v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64)
|
||||
v2.AddArg(x)
|
||||
v1.AddArg(v2)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpRound32F_0(v *Value) bool {
|
||||
// match: (Round32F x)
|
||||
// cond:
|
||||
|
||||
@ -753,6 +753,7 @@ const (
|
||||
AVADDP
|
||||
AVAND
|
||||
AVCMEQ
|
||||
AVCNT
|
||||
AVEOR
|
||||
AVMOV
|
||||
AVLD1
|
||||
|
||||
@ -370,6 +370,7 @@ var Anames = []string{
|
||||
"VADDP",
|
||||
"VAND",
|
||||
"VCMEQ",
|
||||
"VCNT",
|
||||
"VEOR",
|
||||
"VMOV",
|
||||
"VLD1",
|
||||
|
||||
@ -598,6 +598,7 @@ var optab = []Optab{
|
||||
{AVST1, C_LIST, C_NONE, C_ROFF, 84, 4, 0, 0, C_XPOST},
|
||||
{AVDUP, C_ELEM, C_NONE, C_ARNG, 79, 4, 0, 0, 0},
|
||||
{AVADDV, C_ARNG, C_NONE, C_VREG, 85, 4, 0, 0, 0},
|
||||
{AVCNT, C_ARNG, C_NONE, C_ARNG, 29, 4, 0, 0, 0},
|
||||
{AVMOVI, C_ADDCON, C_NONE, C_ARNG, 86, 4, 0, 0, 0},
|
||||
|
||||
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 90, 4, 0, 0, 0},
|
||||
@ -2126,6 +2127,7 @@ func buildop(ctxt *obj.Link) {
|
||||
oprangeset(AVUADDLV, t)
|
||||
|
||||
case ASHA1H,
|
||||
AVCNT,
|
||||
AVMOV,
|
||||
AVLD1,
|
||||
AVREV32,
|
||||
@ -4323,6 +4325,9 @@ func (c *ctxt7) oprrr(p *obj.Prog, a obj.As) uint32 {
|
||||
case AVCMEQ:
|
||||
return 1<<29 | 0x71<<21 | 0x23<<10
|
||||
|
||||
case AVCNT:
|
||||
return 0<<31 | 0<<29 | 0xE<<24 | 0x10<<17 | 5<<12 | 2<<10
|
||||
|
||||
case AVEOR:
|
||||
return 1<<29 | 0x71<<21 | 7<<10
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user