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cmd/internal/obj: remove ppc64 msr support from MOV* insns

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These are privileged instructions, and thus will never work with
usermode code. I don't think there is a case where this isn't
true.  The motivation is to simplify handling of MOV* opcodes.

Assembler support for recognizing the MSR as a register is
retained.

Change-Id: Ic33f021a20057b64e69df8ea125e23dd8937e38d
Reviewed-on: https://go-review.googlesource.com/c/go/+/307814
Run-TryBot: Paul Murphy <murp@ibm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Trust: Carlos Eduardo Seo <carlos.seo@linaro.org>
This commit is contained in:
Paul E. Murphy 2021-03-09 16:55:09 -06:00 committed by Lynn Boger
parent e306d06063
commit fca51ba24a
3 changed files with 0 additions and 22 deletions
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1
src/cmd/internal/obj/ppc64/a.out.go
View File

@ -377,7 +377,6 @@ const (
C_SOREG // D/DS form memory operation
C_LOREG // 32 bit addis + D/DS-form memory operation
C_FPSCR
C_MSR
C_XER
C_LR
C_CTR

1
src/cmd/internal/obj/ppc64/anames9.go
View File

@ -29,7 +29,6 @@ var cnames9 = []string{
"SOREG",
"LOREG",
"FPSCR",
"MSR",
"XER",
"LR",
"CTR",

20
src/cmd/internal/obj/ppc64/asm9.go
View File

@ -233,11 +233,9 @@ var optab = []Optab{
{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 8},
{as: AMOVD, a1: C_TOCADDR, a6: C_REG, type_: 95, size: 8},
{as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
{as: AMOVD, a1: C_MSR, a6: C_REG, type_: 54, size: 4}, /* mfmsr */
{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8},
{as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
{as: AMOVD, a1: C_REG, a6: C_MSR, type_: 54, size: 4}, /* mtmsrd */
{as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
{as: AMOVD, a1: C_REG, a6: C_REG, type_: 1, size: 4},
@ -274,7 +272,6 @@ var optab = []Optab{
{as: AMOVWZ, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
{as: AMOVWZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
{as: AMOVWZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
{as: AMOVWZ, a1: C_REG, a6: C_MSR, type_: 54, size: 4}, /* mtmsr */
{as: AMOVWZ, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
{as: AMOVWZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
@ -807,9 +804,6 @@ func (c *ctxt9) aclass(a *obj.Addr) int {
if a.Reg == REG_FPSCR {
return C_FPSCR
}
if a.Reg == REG_MSR {
return C_MSR
}
return C_GOK
case obj.TYPE_MEM:
@ -2166,15 +2160,12 @@ const (
OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0
OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0
OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0
OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
@ -3251,17 +3242,6 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
case 53: /* mffsX ,fr1 */
o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
case 54: /* mov msr,r1; mov r1, msr*/
if oclass(&p.From) == C_REG {
if p.As == AMOVD {
o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0)
} else {
o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0)
}
} else {
o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0)
}
case 55: /* op Rb, Rd */
o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))