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https://github.com/golang/go
synced 2024-09-30 08:18:40 -06:00
cmd/internal/obj/mips: added support for GOARCH=mips64{,le}
MIPS64 has 32 general purpose 64-bit integer registers (R0-R31), 32 64-bit floating point registers (F0-F31). Instructions are fixed-width, and are 32-bit wide. Instructions are all in standard 1-, 2-, 3-operand forms. MIPS64-specific relocations are added. For this reason, test data of cmd/newlink are regenerated. No other changes are made to portable structures. Branch delay slots are current filled with NOP instructions. The function for instruction scheduling (try to fill the delay slot with a useful instruction) is implemented but disabled for now. Change-Id: Ic364999c7a33245260c1381fc26a2fa8972d38b3 Reviewed-on: https://go-review.googlesource.com/14442 Reviewed-by: Minux Ma <minux@golang.org>
This commit is contained in:
Yao Zhang
Minux Ma
parent
a9bebd91c9
commit
fa6a1ecd63
@ -411,12 +411,18 @@ const (
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// low 16 bits into that of the second instruction.
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R_ADDRPOWER
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R_ADDRARM64
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// R_ADDRMIPS (only used on mips64) resolves to a 32-bit external address,
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// by loading the address into a register with two instructions (lui, ori).
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R_ADDRMIPS
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R_SIZE
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R_CALL
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R_CALLARM
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R_CALLARM64
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R_CALLIND
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R_CALLPOWER
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// R_CALLMIPS (only used on mips64) resolves to non-PC-relative target address
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// of a CALL (JAL) instruction, by encoding the address into the instruction.
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R_CALLMIPS
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R_CONST
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R_PCREL
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// R_TLS_LE, used on 386, amd64, and ARM, resolves to the offset of the
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@ -437,6 +443,10 @@ const (
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R_USEFIELD
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R_POWER_TOC
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R_GOTPCREL
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// R_JMPMIPS (only used on mips64) resolves to non-PC-relative target address
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// of a JMP instruction, by encoding the address into the instruction.
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// The stack nosplit check ignores this since it is not a function call.
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R_JMPMIPS
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// Platform dependent relocations. Architectures with fixed width instructions
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// have the inherent issue that a 32-bit (or 64-bit!) displacement cannot be
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@ -27,14 +27,14 @@
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package ppc64
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package mips
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import "cmd/internal/obj"
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
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/*
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* powerpc 64
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* mips 64
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*/
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const (
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NSNAME = 8
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@ -44,7 +44,7 @@ const (
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)
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const (
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REG_R0 = obj.RBasePPC64 + iota
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REG_R0 = obj.RBaseMIPS64 + iota
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REG_R1
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REG_R2
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REG_R3
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@ -110,90 +110,128 @@ const (
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REG_F30
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REG_F31
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REG_CR0
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REG_CR1
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REG_CR2
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REG_CR3
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REG_CR4
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REG_CR5
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REG_CR6
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REG_CR7
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REG_HI
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REG_LO
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REG_MSR
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REG_FPSCR
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REG_CR
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// co-processor 0 control registers
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REG_M0 = obj.RBaseMIPS64 + 1024 + iota
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REG_M1
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REG_M2
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REG_M3
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REG_M4
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REG_M5
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REG_M6
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REG_M7
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REG_M8
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REG_M9
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REG_M10
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REG_M11
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REG_M12
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REG_M13
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REG_M14
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REG_M15
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REG_M16
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REG_M17
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REG_M18
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REG_M19
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REG_M20
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REG_M21
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REG_M22
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REG_M23
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REG_M24
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REG_M25
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REG_M26
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REG_M27
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REG_M28
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REG_M29
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REG_M30
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REG_M31
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REG_SPECIAL = REG_CR0
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// FPU control registers
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REG_FCR0 = obj.RBaseMIPS64 + 2048 + iota
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REG_FCR1
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REG_FCR2
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REG_FCR3
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REG_FCR4
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REG_FCR5
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REG_FCR6
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REG_FCR7
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REG_FCR8
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REG_FCR9
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REG_FCR10
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REG_FCR11
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REG_FCR12
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REG_FCR13
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REG_FCR14
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REG_FCR15
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REG_FCR16
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REG_FCR17
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REG_FCR18
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REG_FCR19
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REG_FCR20
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REG_FCR21
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REG_FCR22
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REG_FCR23
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REG_FCR24
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REG_FCR25
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REG_FCR26
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REG_FCR27
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REG_FCR28
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REG_FCR29
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REG_FCR30
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REG_FCR31
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REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
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REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers
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REG_XER = REG_SPR0 + 1
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REG_LR = REG_SPR0 + 8
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REG_CTR = REG_SPR0 + 9
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REG_SPECIAL = REG_M0
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REGZERO = REG_R0 /* set to zero */
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REGSP = REG_R1
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REGSB = REG_R2
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REGRET = REG_R3
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REGSP = REG_R29
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REGSB = REG_R30
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REGLINK = REG_R31
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REGRET = REG_R1
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REGARG = -1 /* -1 disables passing the first argument in register */
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REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */
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REGRT2 = REG_R4 /* reserved for runtime, duffcopy */
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REGMIN = REG_R7 /* register variables allocated from here to REGMAX */
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REGCTXT = REG_R11 /* context for closures */
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REGTLS = REG_R13 /* C ABI TLS base pointer */
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REGMAX = REG_R27
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REGEXT = REG_R30 /* external registers allocated from here down */
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REGRT1 = REG_R1 /* reserved for runtime, duffzero and duffcopy */
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REGRT2 = REG_R2 /* reserved for runtime, duffcopy */
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REGCTXT = REG_R22 /* context for closures */
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REGG = REG_R30 /* G */
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REGTMP = REG_R31 /* used by the linker */
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REGTMP = REG_R28 /* used by the linker */
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FREGRET = REG_F0
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FREGMIN = REG_F17 /* first register variable */
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FREGMAX = REG_F26 /* last register variable for 9g only */
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FREGEXT = REG_F26 /* first external register */
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FREGCVI = REG_F27 /* floating conversion constant */
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FREGZERO = REG_F28 /* both float and double */
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FREGHALF = REG_F29 /* double */
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FREGONE = REG_F30 /* double */
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FREGTWO = REG_F31 /* double */
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FREGZERO = REG_F24 /* both float and double */
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FREGHALF = REG_F26 /* double */
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FREGONE = REG_F28 /* double */
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FREGTWO = REG_F30 /* double */
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)
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/*
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* GENERAL:
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*
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* compiler allocates R3 up as temps
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* compiler allocates register variables R7-R27
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* compiler allocates external registers R30 down
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*
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* compiler allocates register variables F17-F26
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* compiler allocates external registers F26 down
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*/
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const (
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BIG = 32768 - 8
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BIG = 32766
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)
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const (
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/* mark flags */
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LABEL = 1 << 0
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LEAF = 1 << 1
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FLOAT = 1 << 2
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BRANCH = 1 << 3
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LOAD = 1 << 4
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FCMP = 1 << 5
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SYNC = 1 << 6
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LIST = 1 << 7
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FOLL = 1 << 8
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NOSCHED = 1 << 9
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FOLL = 1 << 0
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LABEL = 1 << 1
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LEAF = 1 << 2
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SYNC = 1 << 3
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BRANCH = 1 << 4
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LOAD = 1 << 5
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FCMP = 1 << 6
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NOSCHED = 1 << 7
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NSCHED = 20
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)
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const (
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C_NONE = iota
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C_REG
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C_FREG
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C_CREG
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C_SPR /* special processor register */
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C_FCREG
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C_MREG /* special processor register */
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C_HI
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C_LO
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C_ZCON
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C_SCON /* 16 bit signed */
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C_UCON /* 32 bit signed, low 16 bits 0 */
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C_ADD0CON
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C_AND0CON
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C_ADDCON /* -0x8000 <= v < 0 */
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C_ANDCON /* 0 < v <= 0xFFFF */
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C_LCON /* other 32 */
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@ -212,12 +250,6 @@ const (
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C_ZOREG
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C_SOREG
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C_LOREG
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C_FPSCR
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C_MSR
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C_XER
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C_LR
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C_CTR
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C_ANY
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C_GOK
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C_ADDR
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C_TEXTSIZE
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@ -226,313 +258,117 @@ const (
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)
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const (
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AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
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AADDCC
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AADDV
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AADDVCC
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AADDC
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AADDCCC
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AADDCV
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AADDCVCC
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AADDME
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AADDMECC
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AADDMEVCC
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AADDMEV
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AADDE
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AADDECC
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AADDEVCC
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AADDEV
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AADDZE
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AADDZECC
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AADDZEVCC
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AADDZEV
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AABSD = obj.ABaseMIPS64 + obj.A_ARCHSPECIFIC + iota
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AABSF
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AABSW
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AADD
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AADDD
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AADDF
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AADDU
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AADDW
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AAND
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AANDCC
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AANDN
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AANDNCC
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ABC
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ABCL
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ABEQ
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ABGE
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ABGT
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ABLE
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ABLT
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ABFPF
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ABFPT
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ABGEZ
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ABGEZAL
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ABGTZ
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ABLEZ
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ABLTZ
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ABLTZAL
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ABNE
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ABVC
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ABVS
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ACMP
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ACMPU
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ACNTLZW
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ACNTLZWCC
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ACRAND
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ACRANDN
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ACREQV
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ACRNAND
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ACRNOR
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ACROR
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ACRORN
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ACRXOR
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ABREAK
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ACMPEQD
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ACMPEQF
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ACMPGED
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ACMPGEF
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ACMPGTD
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ACMPGTF
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ADIV
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ADIVD
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ADIVF
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ADIVU
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ADIVW
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ADIVWCC
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ADIVWVCC
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ADIVWV
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ADIVWU
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ADIVWUCC
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ADIVWUVCC
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ADIVWUV
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AEQV
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AEQVCC
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AEXTSB
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AEXTSBCC
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AEXTSH
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AEXTSHCC
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AFABS
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AFABSCC
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AFADD
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AFADDCC
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AFADDS
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AFADDSCC
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AFCMPO
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AFCMPU
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AFCTIW
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AFCTIWCC
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AFCTIWZ
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AFCTIWZCC
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AFDIV
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AFDIVCC
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AFDIVS
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AFDIVSCC
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AFMADD
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AFMADDCC
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AFMADDS
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AFMADDSCC
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AFMOVD
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AFMOVDCC
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AFMOVDU
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AFMOVS
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AFMOVSU
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AFMSUB
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AFMSUBCC
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AFMSUBS
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AFMSUBSCC
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AFMUL
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AFMULCC
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AFMULS
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AFMULSCC
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AFNABS
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AFNABSCC
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AFNEG
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AFNEGCC
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AFNMADD
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AFNMADDCC
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AFNMADDS
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AFNMADDSCC
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AFNMSUB
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AFNMSUBCC
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AFNMSUBS
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AFNMSUBSCC
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AFRSP
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AFRSPCC
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AFSUB
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AFSUBCC
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AFSUBS
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AFSUBSCC
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AMOVMW
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ALSW
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ALWAR
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AMOVWBR
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AGOK
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AMOVB
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AMOVBU
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AMOVBZ
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AMOVBZU
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AMOVD
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AMOVDF
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AMOVDW
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AMOVF
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AMOVFD
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AMOVFW
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AMOVH
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AMOVHBR
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AMOVHU
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AMOVHZ
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AMOVHZU
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AMOVW
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AMOVWU
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AMOVFL
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AMOVCRFS
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AMTFSB0
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AMTFSB0CC
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AMTFSB1
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AMTFSB1CC
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AMULHW
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AMULHWCC
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AMULHWU
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AMULHWUCC
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AMULLW
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AMULLWCC
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AMULLWVCC
|
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AMULLWV
|
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ANAND
|
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ANANDCC
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ANEG
|
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ANEGCC
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ANEGVCC
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ANEGV
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AMOVWD
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AMOVWF
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AMOVWL
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AMOVWR
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AMUL
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AMULD
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AMULF
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AMULU
|
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AMULW
|
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ANEGD
|
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ANEGF
|
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ANEGW
|
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ANOR
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ANORCC
|
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AOR
|
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AORCC
|
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AORN
|
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AORNCC
|
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AREM
|
||||
AREMCC
|
||||
AREMV
|
||||
AREMVCC
|
||||
AREMU
|
||||
AREMUCC
|
||||
AREMUV
|
||||
AREMUVCC
|
||||
ARFI
|
||||
ARLWMI
|
||||
ARLWMICC
|
||||
ARLWNM
|
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ARLWNMCC
|
||||
ASLW
|
||||
ASLWCC
|
||||
ASRW
|
||||
ASRAW
|
||||
ASRAWCC
|
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ASRWCC
|
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ASTSW
|
||||
ASTWCCC
|
||||
ARFE
|
||||
ASGT
|
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ASGTU
|
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ASLL
|
||||
ASRA
|
||||
ASRL
|
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ASUB
|
||||
ASUBCC
|
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ASUBVCC
|
||||
ASUBC
|
||||
ASUBCCC
|
||||
ASUBCV
|
||||
ASUBCVCC
|
||||
ASUBME
|
||||
ASUBMECC
|
||||
ASUBMEVCC
|
||||
ASUBMEV
|
||||
ASUBV
|
||||
ASUBE
|
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ASUBECC
|
||||
ASUBEV
|
||||
ASUBEVCC
|
||||
ASUBZE
|
||||
ASUBZECC
|
||||
ASUBZEVCC
|
||||
ASUBZEV
|
||||
ASYNC
|
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AXOR
|
||||
AXORCC
|
||||
|
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ADCBF
|
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ADCBI
|
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ADCBST
|
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ADCBT
|
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ADCBTST
|
||||
ADCBZ
|
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AECIWX
|
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AECOWX
|
||||
AEIEIO
|
||||
AICBI
|
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AISYNC
|
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APTESYNC
|
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ATLBIE
|
||||
ATLBIEL
|
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ATLBSYNC
|
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ATW
|
||||
|
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ASUBD
|
||||
ASUBF
|
||||
ASUBU
|
||||
ASUBW
|
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ASYSCALL
|
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ATLBP
|
||||
ATLBR
|
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ATLBWI
|
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ATLBWR
|
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AWORD
|
||||
|
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ARFCI
|
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|
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/* optional on 32-bit */
|
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AFRES
|
||||
AFRESCC
|
||||
AFRSQRTE
|
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AFRSQRTECC
|
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AFSEL
|
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AFSELCC
|
||||
AFSQRT
|
||||
AFSQRTCC
|
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AFSQRTS
|
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AFSQRTSCC
|
||||
AXOR
|
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|
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/* 64-bit */
|
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AMOVV
|
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AMOVVL
|
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AMOVVR
|
||||
ASLLV
|
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ASRAV
|
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ASRLV
|
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ADIVV
|
||||
ADIVVU
|
||||
AREMV
|
||||
AREMVU
|
||||
AMULV
|
||||
AMULVU
|
||||
AADDV
|
||||
AADDVU
|
||||
ASUBV
|
||||
ASUBVU
|
||||
|
||||
ACNTLZD
|
||||
ACNTLZDCC
|
||||
ACMPW /* CMP with L=0 */
|
||||
ACMPWU
|
||||
ADIVD
|
||||
ADIVDCC
|
||||
ADIVDVCC
|
||||
ADIVDV
|
||||
ADIVDU
|
||||
ADIVDUCC
|
||||
ADIVDUVCC
|
||||
ADIVDUV
|
||||
AEXTSW
|
||||
AEXTSWCC
|
||||
/* AFCFIW; AFCFIWCC */
|
||||
AFCFID
|
||||
AFCFIDCC
|
||||
AFCTID
|
||||
AFCTIDCC
|
||||
AFCTIDZ
|
||||
AFCTIDZCC
|
||||
ALDAR
|
||||
AMOVD
|
||||
AMOVDU
|
||||
AMOVWZ
|
||||
AMOVWZU
|
||||
AMULHD
|
||||
AMULHDCC
|
||||
AMULHDU
|
||||
AMULHDUCC
|
||||
AMULLD
|
||||
AMULLDCC
|
||||
AMULLDVCC
|
||||
AMULLDV
|
||||
ARFID
|
||||
ARLDMI
|
||||
ARLDMICC
|
||||
ARLDC
|
||||
ARLDCCC
|
||||
ARLDCR
|
||||
ARLDCRCC
|
||||
ARLDCL
|
||||
ARLDCLCC
|
||||
ASLBIA
|
||||
ASLBIE
|
||||
ASLBMFEE
|
||||
ASLBMFEV
|
||||
ASLBMTE
|
||||
ASLD
|
||||
ASLDCC
|
||||
ASRD
|
||||
ASRAD
|
||||
ASRADCC
|
||||
ASRDCC
|
||||
ASTDCCC
|
||||
ATD
|
||||
|
||||
/* 64-bit pseudo operation */
|
||||
ADWORD
|
||||
AREMD
|
||||
AREMDCC
|
||||
AREMDV
|
||||
AREMDVCC
|
||||
AREMDU
|
||||
AREMDUCC
|
||||
AREMDUV
|
||||
AREMDUVCC
|
||||
|
||||
/* more 64-bit operations */
|
||||
AHRFID
|
||||
/* 64-bit FP */
|
||||
ATRUNCFV
|
||||
ATRUNCDV
|
||||
ATRUNCFW
|
||||
ATRUNCDW
|
||||
AMOVWU
|
||||
AMOVFV
|
||||
AMOVDV
|
||||
AMOVVF
|
||||
AMOVVD
|
||||
|
||||
ALAST
|
||||
|
||||
// aliases
|
||||
ABR = obj.AJMP
|
||||
ABL = obj.ACALL
|
||||
AJMP = obj.AJMP
|
||||
AJAL = obj.ACALL
|
||||
ARET = obj.ARET
|
||||
)
|
||||
|
||||
@ -1,300 +1,112 @@
|
||||
// Generated by stringer -i a.out.go -o anames.go -p ppc64
|
||||
// Generated by stringer -i a.out.go -o anames.go -p mips
|
||||
// Do not edit.
|
||||
|
||||
package ppc64
|
||||
package mips
|
||||
|
||||
import "cmd/internal/obj"
|
||||
|
||||
var Anames = []string{
|
||||
obj.A_ARCHSPECIFIC: "ADD",
|
||||
"ADDCC",
|
||||
"ADDV",
|
||||
"ADDVCC",
|
||||
"ADDC",
|
||||
"ADDCCC",
|
||||
"ADDCV",
|
||||
"ADDCVCC",
|
||||
"ADDME",
|
||||
"ADDMECC",
|
||||
"ADDMEVCC",
|
||||
"ADDMEV",
|
||||
"ADDE",
|
||||
"ADDECC",
|
||||
"ADDEVCC",
|
||||
"ADDEV",
|
||||
"ADDZE",
|
||||
"ADDZECC",
|
||||
"ADDZEVCC",
|
||||
"ADDZEV",
|
||||
obj.A_ARCHSPECIFIC: "ABSD",
|
||||
"ABSF",
|
||||
"ABSW",
|
||||
"ADD",
|
||||
"ADDD",
|
||||
"ADDF",
|
||||
"ADDU",
|
||||
"ADDW",
|
||||
"AND",
|
||||
"ANDCC",
|
||||
"ANDN",
|
||||
"ANDNCC",
|
||||
"BC",
|
||||
"BCL",
|
||||
"BEQ",
|
||||
"BGE",
|
||||
"BGT",
|
||||
"BLE",
|
||||
"BLT",
|
||||
"BFPF",
|
||||
"BFPT",
|
||||
"BGEZ",
|
||||
"BGEZAL",
|
||||
"BGTZ",
|
||||
"BLEZ",
|
||||
"BLTZ",
|
||||
"BLTZAL",
|
||||
"BNE",
|
||||
"BVC",
|
||||
"BVS",
|
||||
"CMP",
|
||||
"CMPU",
|
||||
"CNTLZW",
|
||||
"CNTLZWCC",
|
||||
"CRAND",
|
||||
"CRANDN",
|
||||
"CREQV",
|
||||
"CRNAND",
|
||||
"CRNOR",
|
||||
"CROR",
|
||||
"CRORN",
|
||||
"CRXOR",
|
||||
"BREAK",
|
||||
"CMPEQD",
|
||||
"CMPEQF",
|
||||
"CMPGED",
|
||||
"CMPGEF",
|
||||
"CMPGTD",
|
||||
"CMPGTF",
|
||||
"DIV",
|
||||
"DIVD",
|
||||
"DIVF",
|
||||
"DIVU",
|
||||
"DIVW",
|
||||
"DIVWCC",
|
||||
"DIVWVCC",
|
||||
"DIVWV",
|
||||
"DIVWU",
|
||||
"DIVWUCC",
|
||||
"DIVWUVCC",
|
||||
"DIVWUV",
|
||||
"EQV",
|
||||
"EQVCC",
|
||||
"EXTSB",
|
||||
"EXTSBCC",
|
||||
"EXTSH",
|
||||
"EXTSHCC",
|
||||
"FABS",
|
||||
"FABSCC",
|
||||
"FADD",
|
||||
"FADDCC",
|
||||
"FADDS",
|
||||
"FADDSCC",
|
||||
"FCMPO",
|
||||
"FCMPU",
|
||||
"FCTIW",
|
||||
"FCTIWCC",
|
||||
"FCTIWZ",
|
||||
"FCTIWZCC",
|
||||
"FDIV",
|
||||
"FDIVCC",
|
||||
"FDIVS",
|
||||
"FDIVSCC",
|
||||
"FMADD",
|
||||
"FMADDCC",
|
||||
"FMADDS",
|
||||
"FMADDSCC",
|
||||
"FMOVD",
|
||||
"FMOVDCC",
|
||||
"FMOVDU",
|
||||
"FMOVS",
|
||||
"FMOVSU",
|
||||
"FMSUB",
|
||||
"FMSUBCC",
|
||||
"FMSUBS",
|
||||
"FMSUBSCC",
|
||||
"FMUL",
|
||||
"FMULCC",
|
||||
"FMULS",
|
||||
"FMULSCC",
|
||||
"FNABS",
|
||||
"FNABSCC",
|
||||
"FNEG",
|
||||
"FNEGCC",
|
||||
"FNMADD",
|
||||
"FNMADDCC",
|
||||
"FNMADDS",
|
||||
"FNMADDSCC",
|
||||
"FNMSUB",
|
||||
"FNMSUBCC",
|
||||
"FNMSUBS",
|
||||
"FNMSUBSCC",
|
||||
"FRSP",
|
||||
"FRSPCC",
|
||||
"FSUB",
|
||||
"FSUBCC",
|
||||
"FSUBS",
|
||||
"FSUBSCC",
|
||||
"MOVMW",
|
||||
"LSW",
|
||||
"LWAR",
|
||||
"MOVWBR",
|
||||
"GOK",
|
||||
"MOVB",
|
||||
"MOVBU",
|
||||
"MOVBZ",
|
||||
"MOVBZU",
|
||||
"MOVH",
|
||||
"MOVHBR",
|
||||
"MOVHU",
|
||||
"MOVHZ",
|
||||
"MOVHZU",
|
||||
"MOVW",
|
||||
"MOVWU",
|
||||
"MOVFL",
|
||||
"MOVCRFS",
|
||||
"MTFSB0",
|
||||
"MTFSB0CC",
|
||||
"MTFSB1",
|
||||
"MTFSB1CC",
|
||||
"MULHW",
|
||||
"MULHWCC",
|
||||
"MULHWU",
|
||||
"MULHWUCC",
|
||||
"MULLW",
|
||||
"MULLWCC",
|
||||
"MULLWVCC",
|
||||
"MULLWV",
|
||||
"NAND",
|
||||
"NANDCC",
|
||||
"NEG",
|
||||
"NEGCC",
|
||||
"NEGVCC",
|
||||
"NEGV",
|
||||
"NOR",
|
||||
"NORCC",
|
||||
"OR",
|
||||
"ORCC",
|
||||
"ORN",
|
||||
"ORNCC",
|
||||
"REM",
|
||||
"REMCC",
|
||||
"REMV",
|
||||
"REMVCC",
|
||||
"REMU",
|
||||
"REMUCC",
|
||||
"REMUV",
|
||||
"REMUVCC",
|
||||
"RFI",
|
||||
"RLWMI",
|
||||
"RLWMICC",
|
||||
"RLWNM",
|
||||
"RLWNMCC",
|
||||
"SLW",
|
||||
"SLWCC",
|
||||
"SRW",
|
||||
"SRAW",
|
||||
"SRAWCC",
|
||||
"SRWCC",
|
||||
"STSW",
|
||||
"STWCCC",
|
||||
"SUB",
|
||||
"SUBCC",
|
||||
"SUBVCC",
|
||||
"SUBC",
|
||||
"SUBCCC",
|
||||
"SUBCV",
|
||||
"SUBCVCC",
|
||||
"SUBME",
|
||||
"SUBMECC",
|
||||
"SUBMEVCC",
|
||||
"SUBMEV",
|
||||
"SUBV",
|
||||
"SUBE",
|
||||
"SUBECC",
|
||||
"SUBEV",
|
||||
"SUBEVCC",
|
||||
"SUBZE",
|
||||
"SUBZECC",
|
||||
"SUBZEVCC",
|
||||
"SUBZEV",
|
||||
"SYNC",
|
||||
"XOR",
|
||||
"XORCC",
|
||||
"DCBF",
|
||||
"DCBI",
|
||||
"DCBST",
|
||||
"DCBT",
|
||||
"DCBTST",
|
||||
"DCBZ",
|
||||
"ECIWX",
|
||||
"ECOWX",
|
||||
"EIEIO",
|
||||
"ICBI",
|
||||
"ISYNC",
|
||||
"PTESYNC",
|
||||
"TLBIE",
|
||||
"TLBIEL",
|
||||
"TLBSYNC",
|
||||
"TW",
|
||||
"SYSCALL",
|
||||
"WORD",
|
||||
"RFCI",
|
||||
"FRES",
|
||||
"FRESCC",
|
||||
"FRSQRTE",
|
||||
"FRSQRTECC",
|
||||
"FSEL",
|
||||
"FSELCC",
|
||||
"FSQRT",
|
||||
"FSQRTCC",
|
||||
"FSQRTS",
|
||||
"FSQRTSCC",
|
||||
"CNTLZD",
|
||||
"CNTLZDCC",
|
||||
"CMPW",
|
||||
"CMPWU",
|
||||
"DIVD",
|
||||
"DIVDCC",
|
||||
"DIVDVCC",
|
||||
"DIVDV",
|
||||
"DIVDU",
|
||||
"DIVDUCC",
|
||||
"DIVDUVCC",
|
||||
"DIVDUV",
|
||||
"EXTSW",
|
||||
"EXTSWCC",
|
||||
"FCFID",
|
||||
"FCFIDCC",
|
||||
"FCTID",
|
||||
"FCTIDCC",
|
||||
"FCTIDZ",
|
||||
"FCTIDZCC",
|
||||
"LDAR",
|
||||
"MOVD",
|
||||
"MOVDU",
|
||||
"MOVWZ",
|
||||
"MOVWZU",
|
||||
"MULHD",
|
||||
"MULHDCC",
|
||||
"MULHDU",
|
||||
"MULHDUCC",
|
||||
"MULLD",
|
||||
"MULLDCC",
|
||||
"MULLDVCC",
|
||||
"MULLDV",
|
||||
"RFID",
|
||||
"RLDMI",
|
||||
"RLDMICC",
|
||||
"RLDC",
|
||||
"RLDCCC",
|
||||
"RLDCR",
|
||||
"RLDCRCC",
|
||||
"RLDCL",
|
||||
"RLDCLCC",
|
||||
"SLBIA",
|
||||
"SLBIE",
|
||||
"SLBMFEE",
|
||||
"SLBMFEV",
|
||||
"SLBMTE",
|
||||
"SLD",
|
||||
"SLDCC",
|
||||
"SRD",
|
||||
"SRAD",
|
||||
"SRADCC",
|
||||
"SRDCC",
|
||||
"STDCCC",
|
||||
"TD",
|
||||
"DWORD",
|
||||
"REMD",
|
||||
"REMDCC",
|
||||
"REMDV",
|
||||
"REMDVCC",
|
||||
"REMDU",
|
||||
"REMDUCC",
|
||||
"REMDUV",
|
||||
"REMDUVCC",
|
||||
"HRFID",
|
||||
"MOVDF",
|
||||
"MOVDW",
|
||||
"MOVF",
|
||||
"MOVFD",
|
||||
"MOVFW",
|
||||
"MOVH",
|
||||
"MOVHU",
|
||||
"MOVW",
|
||||
"MOVWD",
|
||||
"MOVWF",
|
||||
"MOVWL",
|
||||
"MOVWR",
|
||||
"MUL",
|
||||
"MULD",
|
||||
"MULF",
|
||||
"MULU",
|
||||
"MULW",
|
||||
"NEGD",
|
||||
"NEGF",
|
||||
"NEGW",
|
||||
"NOR",
|
||||
"OR",
|
||||
"REM",
|
||||
"REMU",
|
||||
"RFE",
|
||||
"SGT",
|
||||
"SGTU",
|
||||
"SLL",
|
||||
"SRA",
|
||||
"SRL",
|
||||
"SUB",
|
||||
"SUBD",
|
||||
"SUBF",
|
||||
"SUBU",
|
||||
"SUBW",
|
||||
"SYSCALL",
|
||||
"TLBP",
|
||||
"TLBR",
|
||||
"TLBWI",
|
||||
"TLBWR",
|
||||
"WORD",
|
||||
"XOR",
|
||||
"MOVV",
|
||||
"MOVVL",
|
||||
"MOVVR",
|
||||
"SLLV",
|
||||
"SRAV",
|
||||
"SRLV",
|
||||
"DIVV",
|
||||
"DIVVU",
|
||||
"REMV",
|
||||
"REMVU",
|
||||
"MULV",
|
||||
"MULVU",
|
||||
"ADDV",
|
||||
"ADDVU",
|
||||
"SUBV",
|
||||
"SUBVU",
|
||||
"TRUNCFV",
|
||||
"TRUNCDV",
|
||||
"TRUNCFW",
|
||||
"TRUNCDW",
|
||||
"MOVWU",
|
||||
"MOVFV",
|
||||
"MOVDV",
|
||||
"MOVVF",
|
||||
"MOVVD",
|
||||
"LAST",
|
||||
}
|
||||
|
||||
@ -1,14 +1,18 @@
|
||||
package ppc64
|
||||
package mips
|
||||
|
||||
var cnames9 = []string{
|
||||
var cnames0 = []string{
|
||||
"NONE",
|
||||
"REG",
|
||||
"FREG",
|
||||
"CREG",
|
||||
"SPR",
|
||||
"FCREG",
|
||||
"MREG",
|
||||
"HI",
|
||||
"LO",
|
||||
"ZCON",
|
||||
"SCON",
|
||||
"UCON",
|
||||
"ADD0CON",
|
||||
"AND0CON",
|
||||
"ADDCON",
|
||||
"ANDCON",
|
||||
"LCON",
|
||||
@ -27,12 +31,6 @@ var cnames9 = []string{
|
||||
"ZOREG",
|
||||
"SOREG",
|
||||
"LOREG",
|
||||
"FPSCR",
|
||||
"MSR",
|
||||
"XER",
|
||||
"LR",
|
||||
"CTR",
|
||||
"ANY",
|
||||
"GOK",
|
||||
"ADDR",
|
||||
"TEXTSIZE",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -27,7 +27,7 @@
|
||||
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
// THE SOFTWARE.
|
||||
|
||||
package ppc64
|
||||
package mips
|
||||
|
||||
import (
|
||||
"cmd/internal/obj"
|
||||
@ -35,8 +35,8 @@ import (
|
||||
)
|
||||
|
||||
func init() {
|
||||
obj.RegisterRegister(obj.RBasePPC64, REG_DCR0+1024, Rconv)
|
||||
obj.RegisterOpcode(obj.ABasePPC64, Anames)
|
||||
obj.RegisterRegister(obj.RBaseMIPS64, REG_FCR0+1024, Rconv)
|
||||
obj.RegisterOpcode(obj.ABaseMIPS64, Anames)
|
||||
}
|
||||
|
||||
func Rconv(r int) string {
|
||||
@ -53,44 +53,26 @@ func Rconv(r int) string {
|
||||
if REG_F0 <= r && r <= REG_F31 {
|
||||
return fmt.Sprintf("F%d", r-REG_F0)
|
||||
}
|
||||
if REG_CR0 <= r && r <= REG_CR7 {
|
||||
return fmt.Sprintf("CR%d", r-REG_CR0)
|
||||
if REG_M0 <= r && r <= REG_M31 {
|
||||
return fmt.Sprintf("M%d", r-REG_M0)
|
||||
}
|
||||
if r == REG_CR {
|
||||
return "CR"
|
||||
if REG_FCR0 <= r && r <= REG_FCR31 {
|
||||
return fmt.Sprintf("FCR%d", r-REG_FCR0)
|
||||
}
|
||||
if REG_SPR0 <= r && r <= REG_SPR0+1023 {
|
||||
switch r {
|
||||
case REG_XER:
|
||||
return "XER"
|
||||
|
||||
case REG_LR:
|
||||
return "LR"
|
||||
|
||||
case REG_CTR:
|
||||
return "CTR"
|
||||
if r == REG_HI {
|
||||
return "HI"
|
||||
}
|
||||
if r == REG_LO {
|
||||
return "LO"
|
||||
}
|
||||
|
||||
return fmt.Sprintf("SPR(%d)", r-REG_SPR0)
|
||||
}
|
||||
|
||||
if REG_DCR0 <= r && r <= REG_DCR0+1023 {
|
||||
return fmt.Sprintf("DCR(%d)", r-REG_DCR0)
|
||||
}
|
||||
if r == REG_FPSCR {
|
||||
return "FPSCR"
|
||||
}
|
||||
if r == REG_MSR {
|
||||
return "MSR"
|
||||
}
|
||||
|
||||
return fmt.Sprintf("Rgok(%d)", r-obj.RBasePPC64)
|
||||
return fmt.Sprintf("Rgok(%d)", r-obj.RBaseMIPS64)
|
||||
}
|
||||
|
||||
func DRconv(a int) string {
|
||||
s := "C_??"
|
||||
if a >= C_NONE && a <= C_NCLASS {
|
||||
s = cnames9[a]
|
||||
s = cnames0[a]
|
||||
}
|
||||
var fp string
|
||||
fp += s
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -528,7 +528,8 @@ const (
|
||||
RBaseAMD64 = 2 * 1024
|
||||
RBaseARM = 3 * 1024
|
||||
RBasePPC64 = 4 * 1024 // range [4k, 8k)
|
||||
RBaseARM64 = 8 * 1024 // range [8k, 12k)
|
||||
RBaseARM64 = 8 * 1024 // range [8k, 13k)
|
||||
RBaseMIPS64 = 13 * 1024 // range [13k, 16k)
|
||||
)
|
||||
|
||||
// RegisterRegister binds a pretty-printer (Rconv) for register
|
||||
@ -588,6 +589,7 @@ const (
|
||||
ABaseAMD64
|
||||
ABasePPC64
|
||||
ABaseARM64
|
||||
ABaseMIPS64
|
||||
AMask = 1<<12 - 1 // AND with this to use the opcode as an array index.
|
||||
)
|
||||
|
||||
|
||||
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src/cmd/newlink/testdata/autoweak.6
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src/cmd/newlink/testdata/dead.6
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src/cmd/newlink/testdata/hello.6
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src/cmd/newlink/testdata/pclntab.6
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src/cmd/newlink/testdata/pclntab.6
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Loading…
Reference in New Issue
Block a user